JPH0779137B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0779137B2 JPH0779137B2 JP63146185A JP14618588A JPH0779137B2 JP H0779137 B2 JPH0779137 B2 JP H0779137B2 JP 63146185 A JP63146185 A JP 63146185A JP 14618588 A JP14618588 A JP 14618588A JP H0779137 B2 JPH0779137 B2 JP H0779137B2
- Authority
- JP
- Japan
- Prior art keywords
- wiring layer
- aluminum
- contact hole
- semiconductor device
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 14
- 239000010410 layer Substances 0.000 claims description 25
- 239000011229 interlayer Substances 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 15
- 229910052782 aluminium Inorganic materials 0.000 description 15
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 239000000758 substrate Substances 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- AZDRQVAHHNSJOQ-UHFFFAOYSA-N alumane Chemical group [AlH3] AZDRQVAHHNSJOQ-UHFFFAOYSA-N 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置に関し、特に各配線層間を接続する
コンタクト部の構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a structure of a contact portion connecting each wiring layer.
近年多層配線技術を用いて集積度の向上を図った集積回
路デバイスとして例えば第３図に示す様な２層アルミ構
造を有する半導体装置が開発されているが、従来、この
種の半導体装置において第１アルミ電極５と第２アルミ
電極７とのコンタクトはフィールド領域上に形成された
第１アルミ電極５上に開孔されていた。In recent years, a semiconductor device having a two-layer aluminum structure as shown in, for example, FIG. 3 has been developed as an integrated circuit device whose integration degree is improved by using a multilayer wiring technique. The contact between the first aluminum electrode 5 and the second aluminum electrode 7 was opened on the first aluminum electrode 5 formed on the field region.
上述した従来の半導体装置は、コンタクトを開孔する層
間絶縁膜４と、第１アルミ５の下地の層間絶縁膜４、フ
ィールド絶縁膜２とが近年多用されているコンタクトの
異方性プラズマエッチングでの選択比を大きくとる事が
出来ないためコンタクトがフォトリソグラフィ工程にて
目ずれを起こしたり、第１アルミ５が細ったりした場合
に第３図に示した様に半導体基板１にまで達する穴が開
いてしまい、第２アルミ電極７が半導体基板とショート
してしまいという不良が発生し半導体装置の歩留りが大
幅に下がってしまうという欠点がある。The conventional semiconductor device described above uses anisotropic plasma etching of contacts in which the interlayer insulating film 4 for opening a contact, the underlying interlayer insulating film 4 of the first aluminum 5 and the field insulating film 2 are frequently used. Since it is not possible to obtain a large selection ratio for the contact, if the contact is misaligned in the photolithography process or the first aluminum 5 becomes thin, a hole reaching the semiconductor substrate 1 as shown in FIG. There is a disadvantage that the second aluminum electrode 7 is opened and short-circuited with the semiconductor substrate, resulting in a defect that the yield of the semiconductor device is significantly reduced.
本発明は多層配線構造を有する半導体装置において第２
層の配線層上にコンタクト孔が開孔される領域の配線層
下にはこの配線層よりも下層でありかつこのコンタクト
孔よりも大きなパターンの配線層を配置したものであ
る。The present invention relates to a semiconductor device having a multilayer wiring structure.
A wiring layer, which is lower than the wiring layer and has a larger pattern than the contact hole, is arranged below the wiring layer in the region where the contact hole is formed on the wiring layer.
次に、本発明について図面を参照して説明する。 Next, the present invention will be described with reference to the drawings.
第１図は本発明の一実施例の縦断面図である。本実施例
では第１アルミ配線５上にコンタクト孔を開孔し第２ア
ルミ７と接続する場合について述べている。ここでは第
１アルミ配線５上にコンタクト孔が開孔される領域に
は、下に多結晶シリコン３による電極が形成されてい
る。この様にすれば例えコンタクト孔が目ずれ等により
下地の第１アルミ電極５をはずしてしまっても下に位置
する多結晶シリコン電極３があるためコンタクトのエッ
チングがこの多結晶シリコンのところで止まり下の半導
体基板１と第２アルミ配線７がショートしてしまうとい
う事はない。ここで下の多結晶シリコン３をフローティ
ングか又は第1,2アルミ配線層と同電位としておけば装
置が不良となる事はない。FIG. 1 is a vertical sectional view of an embodiment of the present invention. In the present embodiment, the case where a contact hole is opened on the first aluminum wiring 5 and is connected to the second aluminum 7 is described. Here, in the region where the contact hole is formed on the first aluminum wiring 5, an electrode made of polycrystalline silicon 3 is formed below. By doing so, even if the underlying first aluminum electrode 5 is removed due to misalignment of the contact hole or the like, there is the polycrystalline silicon electrode 3 located below, so that the etching of the contact is stopped at this polycrystalline silicon. The semiconductor substrate 1 and the second aluminum wiring 7 are not short-circuited. If the lower polycrystalline silicon 3 is floated or has the same potential as the first and second aluminum wiring layers, the device will not be defective.
第２図は本発明の第２の実施例を示す縦断面図である。
ここでは、第１アルミ５上にコンタクトを開孔する領域
の下にはｎ型拡散層８が配置されている。本実施例では
Ｐ型半導体基板１上に形成されたｎ型拡散層領域８を用
いているため第１の実施例で述べた効果のほかに多結晶
シリコン配線層３をこのコンタクト孔の近くでもある程
度自由に使用でき設計がより楽になるという効果もあ
る。FIG. 2 is a vertical sectional view showing a second embodiment of the present invention.
Here, the n-type diffusion layer 8 is arranged under the region where the contact is opened on the first aluminum 5. In this embodiment, since the n-type diffusion layer region 8 formed on the P-type semiconductor substrate 1 is used, in addition to the effect described in the first embodiment, the polycrystalline silicon wiring layer 3 is provided even near this contact hole. There is also an effect that it can be used freely to some extent and design becomes easier.
以上述べたように本発明は多層配線を有する半導体装置
において配線層上にコンタクトを開孔する場合この領域
に下層の配線層を配置することにより、コンタクトが配
線層をはずして外抜きになった場合でも各層間がショー
トしてしまうという不良を防止でき半導体装置の歩留り
を向上させる事が出来るという効果がある。As described above, according to the present invention, in the case of forming a contact on a wiring layer in a semiconductor device having a multilayer wiring, by disposing the lower wiring layer in this region, the contact is removed by removing the wiring layer. Even in such a case, it is possible to prevent a defect that each layer is short-circuited and improve the yield of the semiconductor device.
第１図は本発明の一実施例の縦断面図、第２図は本発明
の第２の実施例を示す縦断面図、第３図は従来例の縦断
面図である。 １……Ｐ型半導体基板、２……フィールド絶縁膜、３…
…多結晶シリコン配線層、4,6……層間絶縁膜、５……
第１アルミ配線層、７……第２アルミ配線層、８……ｎ
型拡散層。FIG. 1 is a vertical sectional view of an embodiment of the present invention, FIG. 2 is a vertical sectional view showing a second embodiment of the present invention, and FIG. 3 is a vertical sectional view of a conventional example. 1 ... P-type semiconductor substrate, 2 ... field insulating film, 3 ...
… Polycrystalline silicon wiring layer, 4,6 …… Interlayer insulating film, 5 ……
First aluminum wiring layer, 7 ... Second aluminum wiring layer, 8 ... n
Type diffusion layer.
Claims (1)
膜を介して前記第１の配線層より上層に設けられた第２
の配線層とを有する半導体装置において、前記第１の配
線層と前記第２の配線層との電気的接続を行うために前
記第１の層間絶縁膜に形成されたコンタクト孔と、前記
コンタクト孔形成領域下に第２の層間絶縁膜を介して前
記コンタクト孔よりも大きなパターンを有する導電層を
有し、前記導電層は前記コンタクト孔形成領域直下以外
の場所でいずれの他の配線又は素子と電気的接続されて
いないことを特徴とする半導体装置。1. A second layer provided above the first wiring layer via at least a first wiring layer and a first interlayer insulating film.
A contact hole formed in the first interlayer insulating film for electrically connecting the first wiring layer and the second wiring layer, and the contact hole. A conductive layer having a pattern larger than that of the contact hole is provided below the formation region via a second interlayer insulating film, and the conductive layer is connected to any other wiring or element at a position other than directly below the contact hole formation region. A semiconductor device, which is not electrically connected.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63146185A JPH0779137B2 (en) | 1988-06-13 | 1988-06-13 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63146185A JPH0779137B2 (en) | 1988-06-13 | 1988-06-13 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01313959A JPH01313959A (en) | 1989-12-19 |
| JPH0779137B2 true JPH0779137B2 (en) | 1995-08-23 |
Family
ID=15402060
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63146185A Expired - Lifetime JPH0779137B2 (en) | 1988-06-13 | 1988-06-13 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0779137B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR930007752B1 (en) * | 1990-11-21 | 1993-08-18 | 현대전자산업 주식회사 | Semiconductor device connection device and manufacturing method |
| JP5212683B2 (en) * | 2007-03-20 | 2013-06-19 | カシオ計算機株式会社 | Transistor panel and manufacturing method thereof |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57201050A (en) * | 1981-06-05 | 1982-12-09 | Seiko Epson Corp | Multilayer wiring structure |
| JPS58213449A (en) * | 1982-06-04 | 1983-12-12 | Nec Corp | Semiconductor integrated circuit device |
| JPS5935450A (en) * | 1982-08-23 | 1984-02-27 | Nec Corp | Semiconductor device |
| JPS62118543A (en) * | 1985-11-18 | 1987-05-29 | Nec Corp | Semiconductor integrated circuit device |
-
1988
- 1988-06-13 JP JP63146185A patent/JPH0779137B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01313959A (en) | 1989-12-19 |
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