JPH078104B2 - Zero-phase measuring device - Google Patents

Zero-phase measuring device

Info

Publication number
JPH078104B2
JPH078104B2 JP62047322A JP4732287A JPH078104B2 JP H078104 B2 JPH078104 B2 JP H078104B2 JP 62047322 A JP62047322 A JP 62047322A JP 4732287 A JP4732287 A JP 4732287A JP H078104 B2 JPH078104 B2 JP H078104B2
Authority
JP
Japan
Prior art keywords
zero
output
phase
adder
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP62047322A
Other languages
Japanese (ja)
Other versions
JPS63213408A (en
Inventor
勝広 細江
俊治 宮本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Original Assignee
Sumitomo Electric Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Electric Industries Ltd filed Critical Sumitomo Electric Industries Ltd
Priority to JP62047322A priority Critical patent/JPH078104B2/en
Publication of JPS63213408A publication Critical patent/JPS63213408A/en
Publication of JPH078104B2 publication Critical patent/JPH078104B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)
  • Measuring Instrument Details And Bridges, And Automatic Balancing Devices (AREA)
  • Transformers For Measuring Instruments (AREA)
  • Emergency Protection Circuit Devices (AREA)

Description

【発明の詳細な説明】 (イ)利用分野 この発明は送電線及び配電線の地絡事故時に発生する零
相電圧又は零相電流を計測する零相計測装置に関する。
DETAILED DESCRIPTION OF THE INVENTION (a) Field of Use The present invention relates to a zero-phase measuring device for measuring a zero-phase voltage or a zero-phase current generated when a ground fault occurs in a transmission line and a distribution line.

(ロ)従来技術 従来、零相計測装置として第3図に示す構成が知られて
いる。第3図において、3相の送電線1R1S,1Tには夫々
磁界センサ2R,2S,2Tが設けられており、各磁界センサは
各送電線に流れる電流によって生じる磁界の変化を検出
し、夫々対応して増幅器3R,3S,,3Tに検出出力する。前
記磁界センサからの検出出力が光の場合には前記増幅器
の替わりに光電変換器が使用される。各増幅器3R,3S,3T
からの出力は夫々対応して増幅器4R,4S,4Tに入力され
る。増幅器4R,4Tには利得調整用の可変抵抗5R,5Tが接続
され、その増幅器の利得が調整される。各増幅器4R,4S,
4Tの各R,S,T相に流れる電流に対応する出力は加算器6
に入力されて加算される。この加算器6からの加算出力
は零相電流を表示するものとしてメータ7により指示さ
れる。なお、零相電圧を計測する場合にも上述と同様の
構成で測定を行なっていた。
(B) Prior Art Conventionally, a configuration shown in FIG. 3 is known as a zero-phase measuring device. In FIG. 3, magnetic field sensors 2R, 2S, 2T are provided on the three-phase power transmission lines 1R1S, 1T, respectively, and each magnetic field sensor detects a change in the magnetic field caused by the current flowing through each power transmission line, and responds respectively. The output is detected and output to the amplifiers 3R, 3S, and 3T. When the detection output from the magnetic field sensor is light, a photoelectric converter is used instead of the amplifier. Each amplifier 3R, 3S, 3T
The outputs from are correspondingly input to the amplifiers 4R, 4S, 4T. Variable resistors 5R and 5T for gain adjustment are connected to the amplifiers 4R and 4T, and the gain of the amplifier is adjusted. Each amplifier 4R, 4S,
The output corresponding to the current flowing in each R, S, and T phase of 4T is the adder 6
Is input to and added. The addition output from the adder 6 is indicated by the meter 7 as an indication of zero-phase current. When measuring the zero-phase voltage, the measurement was performed with the same configuration as described above.

(ハ)この発明が解決しようとする問題点 第4図(A)は、送電線1R,1S,1Tの通常時の送電電流又
は送電電圧を示し、R相,S相,T相の3相が平衡している
通常時には理想的は零相電圧又は零相電流は零であるか
ら、加算器6の出力は零となる。しかし、3相の各磁界
センサ2R,2S,2T又は増幅器3R,3S,3T及び4R,4S,4Tにわず
かにゲイン、位相に差異がある場合には、加算器6の加
算出力は、3相の増幅器4R,4S,4Tの出力のうち、最も利
得の大きい相の出力にその出力波形が近似する。このこ
とは、装置の組み立て段階において、3相の増幅器及び
電圧又は電流の検出器の利得を完全に一致させる調整を
行なった場合にも、種々の要因により零相出力が現れ、
変化する。これを残留分と称し、その要因としては次の
ものが挙げられる。(i)磁界センサを送配電線に取付
けた時の取付状態による感度のばらつきと温度の経時変
化による変動、(ii)増幅器の温度特性のばらつき、
(iii)送配電系統の対地間インピーダンスの不平衡に
よる系統の零相電圧の発生とその変動、(iv)上記
(i)および(ii)の理由により3相間のゲイン、位相
に差異がある場合、負荷電流の変化により零相電流出力
が現れる、などである。これらの要因は全く規則性は無
く、かついつどのように発生するかは予測できない。即
ち、第4図(B)に示すように、加算器からは通常時に
おいても零相出力が発生することがかなりの頻度で起こ
り得る。
(C) Problems to be solved by the present invention FIG. 4 (A) shows a normal transmission current or transmission voltage of the transmission lines 1R, 1S, 1T, and three phases of R phase, S phase, and T phase. Since the zero-phase voltage or the zero-phase current is ideally zero in the normal state where B is balanced, the output of the adder 6 becomes zero. However, when there are slight differences in gain and phase between the three-phase magnetic field sensors 2R, 2S, 2T or the amplifiers 3R, 3S, 3T and 4R, 4S, 4T, the addition output of the adder 6 is three-phase. Among the outputs of the amplifiers 4R, 4S, and 4T, the output waveform approximates the output of the phase with the largest gain. This means that even when adjustment is made so that the gains of the three-phase amplifier and the voltage or current detector are perfectly matched in the assembly stage of the device, the zero-phase output appears due to various factors.
Change. This is referred to as the residual component, and the factors are as follows. (I) Variations in sensitivity due to the mounting state when the magnetic field sensor is attached to the transmission and distribution lines and variations due to changes in temperature over time, (ii) Variations in the temperature characteristics of the amplifier,
(Iii) Generation and fluctuation of zero-phase voltage in the system due to unbalanced impedance of the transmission / distribution system to ground, (iv) Gain and phase differences among the three phases due to reasons (i) and (ii) above , A zero-phase current output appears due to a change in load current. These factors have no regularity, and it is impossible to predict when and how they will occur. That is, as shown in FIG. 4 (B), the zero-phase output may occur from the adder even in a normal time with a considerable frequency.

上述の状態において、地絡事故が発生し、検出すべき零
相電圧又は零相電流が生じても、この零相の検出出力
は、第4図(C)に示すように、常時の加算器の出力に
埋もれてしまい、事故発生Gの情報を正確に計測できな
い問題があった。
In the above-mentioned state, even if a ground fault occurs and a zero-phase voltage or a zero-phase current to be detected occurs, the zero-phase detection output is always added by an adder as shown in FIG. 4 (C). There was a problem that the information of the accident occurrence G could not be accurately measured because it was buried in the output of.

この発明の目的は、三相交流で各検出器及び増幅器の利
得の不平衡に影響されることなく、零相電流又は零相電
圧を精度良く計測することができる零相計測装置を提供
することである。
An object of the present invention is to provide a zero-phase measuring device capable of accurately measuring a zero-phase current or a zero-phase voltage without being affected by gain imbalance of each detector and amplifier in a three-phase alternating current. Is.

(ニ)問題点を解決するための手段 この発明は、三相交流の夫々の電圧又は電流を検出する
検出手段、各検出出力を増幅する増幅器、各増幅器から
の出力を加算する加算器、加算出力を監視する監視手
段、監視出力が基準地を越えた場合に、零相電圧または
零相電流が検出されるための十分な時間が遅延された後
に制御信号を出力する処理手段、前記制御信号に基づい
て前記加算出力が一定範囲に収まるように前記増幅器の
利得を調整する利得調整手段とを備えている。
(D) Means for Solving the Problems The present invention relates to detection means for detecting respective voltages or currents of a three-phase alternating current, amplifiers for amplifying respective detection outputs, adders for adding outputs from the amplifiers, and addition Monitoring means for monitoring the output, processing means for outputting a control signal after a sufficient time for detecting the zero-phase voltage or zero-phase current is delayed when the monitored output exceeds the reference ground, the control signal And a gain adjusting means for adjusting the gain of the amplifier so that the added output falls within a certain range.

(ホ)作用 加算器の加算出力を常時、監視手段により監視し、監視
出力が基準値を越えた場合には零相電圧または零相電流
が検出されるための十分な時間が遅延された後に、加算
出力が一定範囲に収まるように増幅器の利得を自動的に
調整することにより、該遅延時間経過後の加算器の平常
時の出力を一定範囲内に収める。これにより、平常時の
三相交流の検出、増幅による利得の不平衡に伴う加算器
出力が改善され、地絡事故時に生じる零相電圧又は零相
電流の加算器の出力が精度良く計測できる。
(E) Action The addition output of the adder is constantly monitored by the monitoring means, and if the monitoring output exceeds the reference value, after a sufficient time for detecting the zero-phase voltage or zero-phase current is delayed, By automatically adjusting the gain of the amplifier so that the added output falls within a certain range, the normal output of the adder after the delay time elapses falls within a certain range. As a result, the output of the adder due to the imbalance of the gain due to the detection and amplification of the three-phase alternating current in the normal state is improved, and the output of the adder of the zero-phase voltage or the zero-phase current generated at the time of the ground fault can be accurately measured.

(ヘ)実施例 第1図はこの発明の一実施例を示し、同図において3相
の送電線1R,1S,1Tに流れる三相交流は夫々対応する前述
の磁界センサ2R,2S,2Tによって検出され、夫々前述の増
幅器3R,3S,3Tを経て増幅器11R,11S,11Tに入力される。
増幅器11R,11S,11Tは演算増幅器によって構成され、こ
のうち増幅器11R及び11Tには利得調整用のディジタル/
アナログ(D/A)変換器12R,12Tがその入力と出力の間に
接続されている。各増幅器11R,11S,11Tの出力は加算器1
3に入力されて加算される。この加算器13は演算増幅器
によって構成されている。、加算器13の出力は零相電流
又は零相電圧の計測出力として取り出されると共に、さ
らに演算増幅器14によって増幅された後、実効値/直流
・変換器15に出力される。この実効値/直流・変換器15
に替えて加算出力の平均値又は尖頭値を直流電圧に変換
する変換器を備えても良い。この実効値/直流・変換器
15は入力する交流信号をその実効値に比例した直流電圧
に変換し、サンプルアンドホールド回路16に印加する。
サンプルアンドホールド回路16は一定時間ごとに印加さ
れた直流電圧値を記憶し、その値をアナログ/ディジタ
ル(A/D)変換器17に出力する。アナログ/ディジタル
変換器17は、標準電源18から一定電圧(+5V)の供給を
受け、入力する直流電圧をその値に比例するディジタル
値に変換して、CPU(中央処理装置)19に出力する。標
準電源18が前記利得調整用のディジタル/アナログ変換
器12R,12Tにも標準電圧を印加している。
(F) Embodiment FIG. 1 shows an embodiment of the present invention, in which the three-phase alternating currents flowing through the three-phase transmission lines 1R, 1S, 1T are detected by the corresponding magnetic field sensors 2R, 2S, 2T. The detected signals are input to the amplifiers 11R, 11S, 11T via the amplifiers 3R, 3S, 3T, respectively.
The amplifiers 11R, 11S, and 11T are composed of operational amplifiers, and among them, the amplifiers 11R and 11T include a digital / digital amplifier for gain adjustment.
Analog (D / A) converters 12R, 12T are connected between their inputs and outputs. The output of each amplifier 11R, 11S, 11T is the adder 1
It is input to 3 and added. The adder 13 is composed of an operational amplifier. The output of the adder 13 is taken out as a measurement output of zero-phase current or zero-phase voltage, further amplified by the operational amplifier 14, and then output to the RMS / DC / converter 15. This RMS value / DC / converter 15
Instead of this, a converter for converting the average value or the peak value of the addition output into a DC voltage may be provided. This RMS value / DC / converter
Reference numeral 15 converts the input AC signal into a DC voltage proportional to its effective value and applies it to the sample-and-hold circuit 16.
The sample-and-hold circuit 16 stores the DC voltage value applied every fixed time and outputs the value to the analog / digital (A / D) converter 17. The analog / digital converter 17 is supplied with a constant voltage (+ 5V) from the standard power supply 18, converts the input DC voltage into a digital value proportional to the value, and outputs the digital value to the CPU (central processing unit) 19. The standard power source 18 also applies a standard voltage to the digital / analog converters 12R and 12T for gain adjustment.

前記CPU19は8ビットのワンチップのマイクロコンピュ
ータによって構成され、前記加算器13の出力の実効値と
対応して入力するディジタル値をプリセットされた基準
値と比較し、この基準値を越えた場合には、一定の遅延
の後に制御信号をディジタル/アナログ変換器12R,12T
に夫々出力して各増幅器11R,11Tの利得を調整する。CPU
19に備えられた前記遅延機能は、地絡事故が発生してか
らしゃ断器が動作するまでのほぼ0.1秒間は増幅器11R,1
1Tの利得調整が行なわれないようにして加算器13からの
零相出力を確実に検出するためのもので、好ましくは三
相交流の周期のほぼ10倍に設定される。
The CPU 19 is constituted by an 8-bit one-chip microcomputer, compares the digital value input corresponding to the effective value of the output of the adder 13 with a preset reference value, and when the reference value is exceeded, Is a digital-to-analog converter 12R, 12T that sends a control signal after a certain delay.
To adjust the gain of each amplifier 11R, 11T. CPU
The delay function provided in 19 is amplifier 11R, 1 for approximately 0.1 seconds from the occurrence of a ground fault to the operation of the circuit breaker.
This is for surely detecting the zero-phase output from the adder 13 without performing 1T gain adjustment, and is preferably set to about 10 times the cycle of the three-phase AC.

前述のように構成された零相電流検出装置において、加
算器13からの出力が温度変化等による増幅器11R,11S,11
T等の利得の不平衡に基づいて緩やかに変化し、基準値
より大きくなると、増幅器14、実効値/直流・変換器1
5、サンプルアンドホールド回路16、アナログ/ディジ
タル変換器17、CPU19に入力され、増幅器14の出力が十
分小さいか否か判断し、増幅器出力が設定値よりも大き
いときはD/A変換器12R、12Tの内部の抵抗値を変化さ
せ、増幅器11R、11Tの利得を変化させる。これにより増
幅器14の出力が十分小さくなるように調整する。即ち、
D/A変換器は多数の抵抗とスイッチを組み合わせたもの
であり、CPUからの信号により種々の抵抗値とすること
ができる自動設定可変抵抗の働きをする。この結果、第
2図(A)に示すように平常時においては加算器13の出
力は常時、一定の零に近似する範囲内で変動している。
ところで、送電線1R,1S,1Tのひとつに地絡事故が発生し
た場合には、第2図(B)に示すように事故発生Gと同
時に加算器13から零相検出出力が明確に表われ、この検
出出力はディジタル/アナログ変換器12R,12Tによって
利得制御される前にしゃ断器等の動作に供される。
In the zero-phase current detection device configured as described above, the output from the adder 13 is the amplifier 11R, 11S, 11 due to temperature change or the like.
When it changes gradually based on the gain imbalance of T etc. and becomes larger than the reference value, the amplifier 14, RMS value / DC converter 1
5, sample and hold circuit 16, analog / digital converter 17, input to CPU19, it is judged whether the output of the amplifier 14 is sufficiently small, when the amplifier output is larger than the set value D / A converter 12R, The resistance value inside the 12T is changed to change the gains of the amplifiers 11R and 11T. As a result, the output of the amplifier 14 is adjusted to be sufficiently small. That is,
The D / A converter is a combination of a large number of resistors and switches, and it works as an automatic setting variable resistor that can have various resistance values depending on the signal from the CPU. As a result, as shown in FIG. 2 (A), the output of the adder 13 always fluctuates within a range close to a constant zero in normal times.
By the way, when a ground fault occurs on one of the transmission lines 1R, 1S, 1T, the zero-phase detection output from the adder 13 is clearly shown at the same time as the accident occurrence G as shown in FIG. 2 (B). The detected output is supplied to the operation of a circuit breaker before gain control by the digital / analog converters 12R and 12T.

なお、CPU19に備えた遅延機能は、CPU19から遅延回路を
経てディジタル/アナログ変換器を制御する構成として
も良い。
The delay function provided in the CPU 19 may be configured to control the digital / analog converter from the CPU 19 via a delay circuit.

(ヘ)効果 この発明は、常時、加算器からの出力を監視して平常時
に該出力を零に近い値に制御しているから、地絡事故時
に発生する零相電圧又は零相電流を高感度に取り出すこ
とができる。したがって、温度等による検出上の不平衡
出力に影響されることなく高感度の零相電圧又は零相電
流の検出を行うことができる。
(F) Effect In the present invention, the output from the adder is constantly monitored and the output is controlled to a value close to zero in a normal state. Therefore, the zero-phase voltage or zero-phase current generated at the time of a ground fault accident is high. It can be taken out with sensitivity. Therefore, it is possible to detect the zero-phase voltage or the zero-phase current with high sensitivity without being affected by the unbalanced output in the detection due to the temperature or the like.

【図面の簡単な説明】[Brief description of drawings]

第1図はこの発明の一実施例を示す回路構成図、第2図
(A)(B)は第1図の加算器の出力波形図、第3図は
従来の零相計測装置の回路構成図、第4図(A)(B)
(C)は第3図の零相計測装置の動作を説明する波形図
である。 1R,1S,1T…送電線 2R,2S,2T…磁界センサ 11R,11S,11T…増幅器 12R,12T…ディジタル/アナログ変換器 13…加算器 15…実効値/直流・変換器 16…サンプルアンドホールド回路 17…アナログ/ディジタル変換器 19…CPU
FIG. 1 is a circuit configuration diagram showing an embodiment of the present invention, FIGS. 2A and 2B are output waveform diagrams of the adder of FIG. 1, and FIG. 3 is a circuit configuration of a conventional zero-phase measuring device. Figure, Figure 4 (A) (B)
(C) is a waveform diagram for explaining the operation of the zero-phase measuring device of FIG. 3. 1R, 1S, 1T ... Transmission line 2R, 2S, 2T ... Magnetic field sensor 11R, 11S, 11T ... Amplifier 12R, 12T ... Digital / analog converter 13 ... Adder 15 ... RMS value / DC converter 16 ... Sample and hold Circuit 17 ... Analog / digital converter 19 ... CPU

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】三相交流の夫々の電圧又は電流を検出する
検出手段と、 前記検出手段からの各検出出力を増幅する増幅器と、 前記各増幅器からの出力を加算する加算器と、 前記加算器からの加算出力を監視する監視手段と、 前記監視手段からの監視出力が基準値を越えた場合に、
前記三相交流の電圧または電流の零相電圧または零相電
流を検出するための十分な時間が遅延された後に制御信
号を出力す処理手段と、 前記制御信号に基づいて前記増幅器の利得を調整して前
記加算器の加算出力を一定範囲に収める利得調整手段
と、 を備えてなる零相計測装置。
1. A detection means for detecting each voltage or current of a three-phase alternating current, an amplifier for amplifying each detection output from the detection means, an adder for adding outputs from each amplifier, and the addition. Monitoring means for monitoring the addition output from the vessel, when the monitoring output from the monitoring means exceeds a reference value,
Processing means for outputting a control signal after a sufficient time for detecting the zero-phase voltage or zero-phase current of the three-phase AC voltage or current is delayed; and adjusting the gain of the amplifier based on the control signal. Then, a zero-phase measuring device comprising: a gain adjusting means for keeping the added output of the adder within a fixed range.
【請求項2】前記利得調整手段は二相分の前記増幅器の
利得のみを調整する、特許請求の範囲第1項記載の零相
計測装置。
2. The zero-phase measuring device according to claim 1, wherein the gain adjusting means adjusts only the gains of the amplifiers for two phases.
【請求項3】前記監視手段は前記加算器の加算出力の実
効値又は平均値又は尖頭値を直流電圧に変換する変換手
段及び該変換手段からの出力をディジタル信号に変換す
るアナログ/ディジタル変換器を含み、前記利得調整手
段は前記制御信号の出力に応じて利得を調整するディジ
タル/アナログ変換器を含む、特許請求の範囲第1項に
記載の零相計測器。
3. The converting means converts the effective value, average value or peak value of the addition output of the adder into a DC voltage, and the analog / digital conversion converting the output from the converting means into a digital signal. A zero-phase measuring instrument according to claim 1, further comprising a digital / analog converter, wherein the gain adjusting means includes a digital / analog converter that adjusts a gain according to an output of the control signal.
JP62047322A 1987-03-02 1987-03-02 Zero-phase measuring device Expired - Fee Related JPH078104B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62047322A JPH078104B2 (en) 1987-03-02 1987-03-02 Zero-phase measuring device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62047322A JPH078104B2 (en) 1987-03-02 1987-03-02 Zero-phase measuring device

Publications (2)

Publication Number Publication Date
JPS63213408A JPS63213408A (en) 1988-09-06
JPH078104B2 true JPH078104B2 (en) 1995-01-30

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP62047322A Expired - Fee Related JPH078104B2 (en) 1987-03-02 1987-03-02 Zero-phase measuring device

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JP (1) JPH078104B2 (en)

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57183224A (en) * 1981-05-07 1982-11-11 Tokyo Shibaura Electric Co Distance relay
JPS5855458A (en) * 1981-09-28 1983-04-01 Yasuo Kikukawa Preparation of indole compound

Also Published As

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JPS63213408A (en) 1988-09-06

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