JPH0783214B2 - High frequency oscillator - Google Patents
High frequency oscillatorInfo
- Publication number
- JPH0783214B2 JPH0783214B2 JP61199442A JP19944286A JPH0783214B2 JP H0783214 B2 JPH0783214 B2 JP H0783214B2 JP 61199442 A JP61199442 A JP 61199442A JP 19944286 A JP19944286 A JP 19944286A JP H0783214 B2 JPH0783214 B2 JP H0783214B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- frequency
- voltage
- oscillation circuit
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000010355 oscillation Effects 0.000 claims description 32
- 238000010897 surface acoustic wave method Methods 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 3
- 239000013078 crystal Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000001360 synchronised effect Effects 0.000 description 2
- 238000004891 communication Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、通信装置などの同期回路に使用される電圧制
御発振回路に関する。特に、出力周波数が数百MHz帯で
高安定な電圧制御圧電発振回路に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voltage controlled oscillator circuit used in a synchronous circuit such as a communication device. In particular, the present invention relates to a voltage controlled piezoelectric oscillator circuit having an output frequency of several hundred MHz and being highly stable.
本発明は、高安定の高周波信号を発生する発振器におい
て、 高周波を発振する電圧制御発振回路を位相同期技術によ
り低周波側の安定な発振回路の周波数に同期させること
により、 発振器を小型化しかつ消費電力を低減することができる
ようにしたものである。The present invention, in an oscillator that generates a high-stable high-frequency signal, synchronizes a voltage-controlled oscillation circuit that oscillates a high frequency with the frequency of a stable oscillation circuit on the low-frequency side by phase synchronization technology, thereby making the oscillator compact and The electric power can be reduced.
従来高周波高安定の電圧制御発振器は、第２図に示すよ
うに、水晶共振子を含む高安定の電圧制御発振器１の出
力を逓倍回路７に入力し、その高調波成分を出力する構
成になっていた。As shown in FIG. 2, a conventional high frequency and highly stable voltage controlled oscillator has a configuration in which the output of a highly stable voltage controlled oscillator 1 including a crystal resonator is input to a multiplication circuit 7 and its harmonic component is output. Was there.
このような従来の電圧制御圧電発振回路は、逓倍回路が
必要であり、この逓倍回路は消費電力が大きく、また、
広い実装スペースが必要になり、小型化および低価格化
を困難にする欠点があり、さらに、基本周波数成分を除
去する狭帯域のフィルタが必要であった。Such a conventional voltage controlled piezoelectric oscillator circuit requires a multiplication circuit, and this multiplication circuit consumes a large amount of power.
A wide mounting space is required, there is a drawback that miniaturization and cost reduction are difficult, and a narrow band filter for removing the fundamental frequency component is required.
本発明はこのような欠点を除去するもので、小型で価格
の低廉な高周波発振回路を提供することを目的とする。The present invention eliminates such drawbacks, and an object of the present invention is to provide a high-frequency oscillator circuit that is small and inexpensive.
本発明は、到来する制御電圧が与えられ制御電圧値に応
じて静電容量の変化する可変容量素子および圧電共振素
子を有する第一の電圧制御発振回路と、この発振回路の
発振周波数の整数倍の周波数の信号を出力端子に与える
弾性表面波共振子を有する第二の電圧制御発振回路と、
この発振回路の出力信号の整数分の１の周波数の信号を
生成する分周回路と、この分周回路の出力信号の位相と
上記第一の電圧制御発振回路の出力信号の位相との位相
差に相応する電圧を生成する位相比較器と、この位相比
較器の出力を上記第二の電圧制御発振回路の制御電圧と
して与える接続手段とを備えたことを特徴とする。The present invention is directed to a first voltage controlled oscillation circuit having a variable capacitance element and a piezoelectric resonance element whose electrostatic capacitance changes in response to an incoming control voltage, and an integral multiple of the oscillation frequency of this oscillation circuit. A second voltage controlled oscillation circuit having a surface acoustic wave resonator for applying a signal of the frequency to the output terminal,
A frequency divider circuit that generates a signal having a frequency that is an integer fraction of the output signal of the oscillator circuit, and a phase difference between the phase of the output signal of the frequency divider circuit and the phase of the output signal of the first voltage controlled oscillator circuit. And a connecting means for supplying the output of the phase comparator as the control voltage of the second voltage controlled oscillator circuit.
本発明の電圧制御圧電発振回路では、高周波で発振する
電圧制御圧電発振回路を位相同期技術により低周波側の
安定な圧電発振回路出力周波数に同期させて安定した高
周波発振を実現する。ここで、高周波側の発振回路が低
周波側の発振回路の安定度と同等であれば直接使用可能
であるが、通常数百MHz帯の発振回路の安定度は数十MHz
帯で水晶共振子などを使用する低周波側の発振回路の安
定度に比べて悪い。In the voltage controlled piezoelectric oscillation circuit of the present invention, the voltage controlled piezoelectric oscillation circuit that oscillates at a high frequency is synchronized with the stable piezoelectric oscillation circuit output frequency on the low frequency side by the phase synchronization technique to realize stable high frequency oscillation. Here, if the oscillation circuit on the high frequency side is equivalent to the stability of the oscillation circuit on the low frequency side, it can be used directly, but the stability of the oscillation circuit in the several hundred MHz band is usually several tens of MHz.
It is worse than the stability of the oscillation circuit on the low frequency side that uses a crystal resonator in the band.
以下、本発明実施例回路を図に基づいて説明する。 The circuit of the embodiment of the present invention will be described below with reference to the drawings.
第１図はこの実施例の構成を示すブロック構成図であ
る。FIG. 1 is a block diagram showing the configuration of this embodiment.
まず、この実施例回路の構成を第１図に基づいて説明す
る。この実施例装置は、制御入力端子10に入力が接続さ
れた電圧制御圧電発振回路１と、この電圧制御圧電発振
回路１の出力に一方の入力が接続され、分周回路４の出
力に他方の入力が接続された位相比較器２と、この位相
比較器２の出力に入力が接続され、出力が出力端子15お
よび分周回路４に接続された電圧制御圧電発振回路３
と、分周回路４とを備える。First, the configuration of the circuit of this embodiment will be described with reference to FIG. In the device of this embodiment, one input is connected to the output of the voltage control piezoelectric oscillation circuit 1 whose input is connected to the control input terminal 10, and one output is connected to the output of this voltage control piezoelectric oscillation circuit 1, and the other is connected to the output of the frequency dividing circuit 4. A phase comparator 2 having an input connected thereto, and a voltage controlled piezoelectric oscillator circuit 3 having an input connected to the output of the phase comparator 2 and an output connected to the output terminal 15 and the frequency dividing circuit 4.
And a frequency dividing circuit 4.
ここで、電圧制御圧電発振回路１は、印加する電圧値で
静電容量の変化する可変容量素子と圧電共振素子とを含
む電圧制御圧電発振回路であり、また、電圧制御圧電発
振回路３は、弾性表面波共振子を使用した電圧制御圧電
発振回路である。Here, the voltage-controlled piezoelectric oscillation circuit 1 is a voltage-controlled piezoelectric oscillation circuit including a variable capacitance element whose capacitance changes according to an applied voltage value and a piezoelectric resonance element, and the voltage-controlled piezoelectric oscillation circuit 3 is It is a voltage-controlled piezoelectric oscillation circuit using a surface acoustic wave resonator.
次に、この実施例装置の動作を第１図に基づいて説明す
る。制御入力端子10に印加される電圧値に応じて出力周
波数が変化する安定な電圧制御圧電発振回路１の出力は
位相比較器２に入力する。ここで、電圧制御圧電発振回
路１の出力周波数の整数倍の周波数を出力する電圧制御
圧電発振回路３の周波数可変範囲は、電圧制御圧電発振
回路１の周波数可変範囲と自回路の周波数安定度の和以
上である。電圧制御圧電発振回路３の出力は分周回路４
に入力し、ここで電圧制御圧電発振回路１に同じ周波数
まで分周されて出力し、位相比較器２に入力する。位相
比較器２の出力は電圧制御圧電発振回路１および３の位
相差に比例した電圧を出力し、これを電圧制御圧電発振
回路３の制御入力に接続して位相同期ループを構成し、
位相同期している状態では、電圧制御圧電発振回路３の
出力周波数は電圧制御圧電発振回路１の整数倍（分周回
路４の分周比）に等しい周波数を出力する。Next, the operation of the apparatus of this embodiment will be described with reference to FIG. The output of the stable voltage controlled piezoelectric oscillation circuit 1 whose output frequency changes according to the voltage value applied to the control input terminal 10 is input to the phase comparator 2. Here, the frequency variable range of the voltage controlled piezoelectric oscillator circuit 3 that outputs a frequency that is an integer multiple of the output frequency of the voltage controlled piezoelectric oscillator circuit 1 is the frequency variable range of the voltage controlled piezoelectric oscillator circuit 1 and the frequency stability of its own circuit. It is more than sum. The output of the voltage controlled piezoelectric oscillation circuit 3 is the frequency dividing circuit 4
Is input to the voltage controlled piezoelectric oscillation circuit 1 after being divided by the same frequency and output to the phase comparator 2. The output of the phase comparator 2 outputs a voltage proportional to the phase difference between the voltage controlled piezoelectric oscillator circuits 1 and 3, and this is connected to the control input of the voltage controlled piezoelectric oscillator circuit 3 to form a phase locked loop.
In the phase-locked state, the output frequency of the voltage controlled piezoelectric oscillator circuit 3 outputs a frequency equal to an integral multiple of the voltage controlled piezoelectric oscillator circuit 1 (the frequency division ratio of the frequency divider circuit 4).
本発明は、以上説明したように、従来の逓倍回路に比較
すると回路構成が簡単であり、低消費電力および小型化
を図ることができ、また、低周波の発振回路に従来の可
変容量素子と圧電共振素子とを用いる電圧制御発振器を
用い、高周波の発振回路に弾性表面波共振子を用いるこ
とにより、全体の温度特性を平坦にでき、また高周波の
発振回路の集積回路化を図ることができる効果がある。INDUSTRIAL APPLICABILITY As described above, the present invention has a simple circuit configuration as compared with a conventional multiplication circuit, and can achieve low power consumption and downsizing, and a low-frequency oscillator circuit with a conventional variable capacitance element. By using a voltage controlled oscillator that uses a piezoelectric resonance element and using a surface acoustic wave resonator in a high frequency oscillation circuit, it is possible to flatten the overall temperature characteristics and to realize an integrated circuit of the high frequency oscillation circuit. effective.
第１図は本発明実施例回路の構成を示すブロック構成
図。 第２図は従来例回路の構成を示すブロック構成図。 １、３……電圧制御圧電発振回路、２……位相比較器、
４……分周回路、５……高調波発生回路、６……同調回
路。７……逓倍回路、10……制御入力端子、15……出力
端子。FIG. 1 is a block configuration diagram showing the configuration of an embodiment circuit of the present invention. FIG. 2 is a block diagram showing the configuration of a conventional circuit. 1, 3 ... Voltage controlled piezoelectric oscillator circuit, 2 ... Phase comparator,
4 ... Dividing circuit, 5 ... Harmonic generation circuit, 6 ... Tuning circuit. 7: multiplication circuit, 10: control input terminal, 15: output terminal.
Claims (1)
応じて静電容量の変化する可変容量素子および圧電共振
素子を有する第一の電圧制御発振回路と、 この発振回路の発振周波数の整数倍の周波数の信号を出
力端子に与える弾性表面波共振子を有する第二の電圧制
御発振回路と、 この発振回路の出力信号の整数分の１の周波数の信号を
生成する分周回路と、 この分周回路の出力信号の位相と上記第一の電圧制御発
振回路の出力信号の位相との位相差に相応する電圧を生
成する位相比較器と、 この位相比較器の出力を上記第二の電圧制御発振回路の
制御電圧として与える接続手段と を備えたことを特徴とする高周波発振回路。1. A first voltage-controlled oscillation circuit having a variable capacitance element and a piezoelectric resonance element whose electrostatic capacitance changes in response to an incoming control voltage, and an integer of the oscillation frequency of this oscillation circuit. A second voltage controlled oscillation circuit having a surface acoustic wave resonator for giving a signal of a doubled frequency to an output terminal; a frequency dividing circuit for generating a signal having a frequency which is a fraction of an output signal of the oscillation circuit; A phase comparator that generates a voltage corresponding to the phase difference between the phase of the output signal of the frequency divider circuit and the phase of the output signal of the first voltage controlled oscillator circuit, and the output of this phase comparator as the second voltage A high-frequency oscillation circuit, comprising: a connection means for supplying a control voltage of the control oscillation circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61199442A JPH0783214B2 (en) | 1986-08-26 | 1986-08-26 | High frequency oscillator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61199442A JPH0783214B2 (en) | 1986-08-26 | 1986-08-26 | High frequency oscillator |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6356019A JPS6356019A (en) | 1988-03-10 |
| JPH0783214B2 true JPH0783214B2 (en) | 1995-09-06 |
Family
ID=16407882
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61199442A Expired - Lifetime JPH0783214B2 (en) | 1986-08-26 | 1986-08-26 | High frequency oscillator |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0783214B2 (en) |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5915401B2 (en) * | 1974-04-26 | 1984-04-09 | 日本電気株式会社 | Frequency variable microwave generator |
| JPS5398766A (en) * | 1977-02-08 | 1978-08-29 | Marukon Denshi Kk | Pll synthesizer |
| JPS58170229A (en) * | 1982-03-31 | 1983-10-06 | Toshiba Corp | Frequency multiplication circuit |
-
1986
- 1986-08-26 JP JP61199442A patent/JPH0783214B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6356019A (en) | 1988-03-10 |
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