JPH0785622B2 - Inverter protection device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a power factor adjustable pulse width modulation (PW) device.
The present invention relates to an inverter protection device in which an M) type inverter is arranged and boost control is performed to control a DC voltage at a constant level.

(Prior Art) Generally, in a motor control device such as a thyristor Leonard device or a cycloconverter device, in a system in which voltage adjustment is performed by phase control, a control current with respect to a power supply voltage is delayed by a phase control angle, and thus a power factor is reduced. Drop,
The power supply must provide reactive power to the controller. Therefore, in such a control device, since the power supply capacity must be set to a value obtained by adding the reactive power capacity, the power supply capacity becomes large, and there is a drawback that a large amount of power supply equipment is required.

Therefore, in recent years, in order to improve the above problems, various electric motor control devices having a good power factor have been proposed. FIG. 4 is a circuit diagram showing a configuration example of this type of control device. In FIG. 4, 1 is an AC power source bus bar, 2 is an inverter device in which an AC input terminal is connected to this AC power source bus line 1 via an electromagnetic contactor 3 and a reactor 4, and 5 is a DC output terminal of this inverter device 2. DC power bus 6
A variable voltage variable frequency control device connected via the variable voltage variable frequency control device 5 is provided as a power conversion device for controlling the three-phase induction motor 7. 8
Is a smoothing capacitor connected to the DC power bus 6,
It constitutes the main circuit of the voltage source inverter. 9 more
Is a DC voltage detector connected to the DC power bus 6. On the other hand, 10 is a voltage controller to which the detection signal 9a of the DC voltage detector 9 and the voltage reference signal 11a of the voltage reference setting device 11 are input, and 12 is the output signal 10a of this voltage controller 10 and the AC bus 1
The current reference command device to which the voltage signal 13a of the AC voltage detector 13 connected to is input, 14 is the current control reference signal 12a of the current reference command device 12 and the current detector 15 provided on the AC power bus 1. It is a current controller to which the current signal 15a is input. 16 is a PWM control device to which the voltage command value 14a output from the current controller 14 is input.
Reference numeral 6 is for switching control of the inverter device 2.

Now, referring to FIG. 4, the variable voltage variable frequency control device 5
Is a sinusoidal current control method that controls the current in a sinusoidal manner by pulse width modulation (PWM) control that uses a self-extinguishing switching element such as GTR or GTO, or the excitation current component and torque component of the induction motor 7. It is possible to perform excellent control by a vector control method or the like for controlling the. Further, the inverter device 2 is also an inverter device using a switching element capable of self-extinguishing such as GTR and GTO, as in the above, and the inverter device 2 is
The voltage of the DC power bus 6 and the current of the AC power bus 1 are controlled as follows.

For example, the voltage reference signal 11a of the voltage setting device 11 and the detection signal 9a of the voltage detector 9 provided on the DC power supply bus 6 in FIG.
Is input to the voltage controller 10, the voltage controller 10 outputs the deviation output 10a to the voltage detector 1 provided on the AC power supply bus 1.
It is input to the current reference command device 12 together with the voltage signal 13a of 3. In this current reference command device 12, based on the deviation output 10a, it is converted into a current control reference signal 12a of the inverter device 2 synchronized with the phase of the phase voltage of the AC power supply bus 1, and this current control reference signal 12a and the AC power supply bus 1 are converted. The current signal 15a from the current detector 15 provided in the above is input to the current controller 14. The current controller 14 outputs a voltage command value 14a to the PWM control device 16 when the current signal 15a is input, and the PWM control device 16 receives this signal and controls the switching of the inverter device 2.

In this way, by controlling the current of each phase using the current control reference signal 12a as a sine wave reference synchronized with the phase of the phase voltage of the AC power supply bus 1, it is possible to operate with a high power factor. In this case, the voltage signal 13a is used as a sinusoidal reference and the output 10a of the voltage controller 10 determines the amplitude of the current control reference signal 12a. Further, the detector, the controller and the like have different configurations depending on the number of phases of the AC power source bus 1. The inverter device 2 is
After charging the smoothing capacitor 8 of the DC power bus 6 by turning on the electromagnetic contactor 3 provided on the AC power bus 1,
The control is started, and the voltage is adjusted to the value of the voltage reference signal 11a of the voltage setter 11 by the boosting action of the reactor 4 and the inverter device 2, and then the voltage of the DC power supply bus bar 6 is changed to the voltage reference according to the operating state of the load. The current of the AC power supply bus bar 1 is controlled so as to follow the signal 11a.

(Problems to be Solved by the Invention) In a motor control device as shown in FIG. 4, while the inverter device 2 is operating, the voltage signal 13a is caused by the abnormality of the voltage detector 13 or the like to cause the phase of the AC power supply bus 1 to change. When the phase shift of the voltage occurs, the current control reference signal 12a also becomes out of synchronization with the phase of the phase voltage. If the control of the inverter device 2 is continued in this state, there is a risk that an overcurrent may flow in the switching element forming the inverter device 2 depending on its operation mode, and the device may be destroyed.
Therefore, continuing the control in this state is not preferable for the control of the entire system.

Therefore, an object of the present invention is to protect the inverter so that the entire control device can be protected even when the voltage signal synchronized with the phase of the phase voltage of the AC power supply bus is out of synchronization. To provide a device.

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, the present invention synchronizes with a power supply input from an AC power supply through an electromagnetic contactor, and the AC power is supplied based on the power supply synchronization signal. A pulse width modulation type inverter device capable of adjusting a power factor and a smoothing capacitor for smoothing the DC output of the inverter device, and an inverter device for controlling the DC output voltage to a set voltage, The voltage detector that detects the voltage of each phase of the AC power supply and the voltage of each phase of the AC power supply detected by this voltage detector are binarized, and the pattern is not synchronized with the phase difference of the phase voltage of the AC power supply bus. When a pattern is detected, a detection device that detects an abnormality in the voltage detector is operated to open the electromagnetic contactor by the abnormality detection output of the detection device, and the inverter device is exchanged. An operating device and disconnecting from the power supply.

(Operation) In such a configuration, the detection device detects each phase voltage of the AC power supply, binarizes the voltage with a predetermined level as a threshold value, and parallelizes the data of the binarized phase voltage. Watch for that pattern to watch. Then, if a synchronization shift or voltage abnormality occurs between the phases, the pattern exhibits an abnormality. Therefore, when the pattern exhibits an abnormality, an abnormality detection output is output. The operation device is activated by this abnormality detection output to shut off the AC power supply of the inverter device.

Therefore, even when the phase voltage of the AC power supply is out of synchronization, and also when the voltage level is abnormal, this can be detected and the inverter device in operation can be protected.

(Example) Hereinafter, the present invention will be described with reference to an example shown in the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention, which shows a configuration example of a drive control device when an induction machine is sometimes used as an electric motor. The basic structure of this device is the same as the conventional one described in FIG. Therefore, the first
In the figure, the same parts as those in FIG. 4 are designated by the same reference numerals, the description thereof will be omitted, and different parts will be described.

As shown in FIG. 1, the present apparatus is obtained by adding a power supply synchronization detection device 17 and an electromagnetic contactor excitation circuit 18 for opening the electromagnetic contactor 3 to the configuration of FIG. Among these, the power supply synchronization detection device 17 detects the synchronization deviation with respect to the phase of the phase voltage of the AC power supply bus based on the voltage signal 13a which is the output of the AC voltage detector 13, and when detecting the synchronization deviation, the AC electromagnetic contactor is used. An OFF command signal 17a for the contactor is applied to the excitation circuit 18 of No. 3.

FIG. 2 is a circuit configuration diagram showing details of the configuration of the power supply synchronization detection device 17. In the figure, 19A to 19C are 60 ° phase delay circuits that delay each phase voltage signal from the voltage detector 13 by 60 ° and output (here, it is assumed that the AC bus power supply has three phases), 20A to 20C is provided corresponding to each of the 60 ° phase delay circuits 19A to 19C, and the 60 ° phase delay voltage signal output from the corresponding circuit is converted into logic "H" or "L" depending on the level, and logic signal 20a Logic detection circuit that outputs as ~ 20c, 21 is a fuse ROM (read only memory),
The logic signals 20a to 20c are lower addresses (A0 to A).
2) and the frequency division signals 25a to 25 from the frequency division circuit 25 described later.
d is connected to the upper address (A3 to A6), and the voltage information and the sync deviation information stored in the address corresponding to the address signal are output as the voltage signals 21a to 21c and the sync deviation detection signal 17a, respectively. (Here, A0-A6
A0 is the lowest address and A6 is the highest address).
Further, the signal 21d is a division cycle clear output for keeping the electrical angle of 180 ° by 12 and is an output signal of the data output terminal D4 of the ROM 21. 22 is an adder for adding the voltage signals 21a to 21c,
23 is a voltage smoothing circuit for smoothing the added signal 22a, 24 is a voltage oscillating circuit (VCO circuit) for receiving the smoothed voltage signal 23a and converting it into a signal 24a having a pulse frequency corresponding to the voltage, 25 is the pulse signal Divide 24a to 1/16, 1/8, 1/4,
It is a frequency dividing circuit that generates 1/2 frequency dividing signals 25a to 25d.

Further, FIG. 3 is a timing chart showing an output state of each element of FIG. 2 when the voltage detection signal is synchronized with the phase of the power supply bus voltage.

The above ROM 21 is the data that binarizes the voltage level of each phase of U, V, W when there is no voltage abnormality or synchronization deviation with respect to the phase of the power bus and when the electrical angle of 180 ° is divided into 12 equal parts. The binary data of each phase of U, V, and W that can be taken at this time is made to correspond to the lower 3 bits of the address, and is generated under the input of a constant voltage when there is no voltage abnormality or synchronization deviation as described above. The pulse signal 24a of the VCO circuit 24 is frequency-divided by the frequency divider circuit 25, and for each address that can be specified when the upper 4-bit address A3 to A6 is specified, the U, V, and W phases Data corresponding to each of the above-described 12 equal sections of the binary data of the voltage level is stored. At this time
Each of the U, V, and W phases is stored in association with one of the lower 3 bits of data bit positions. Further, the fifth lowest data bit (D4) stores reset data “H” for giving a reset signal to the frequency dividing circuit 25 at the address corresponding to the last section divided into 12 equal parts. As long as there is no abnormality in the power supply bus or synchronization deviation (as long as it is normal), the reset operation is performed at frequency division of 12 so that further frequency division does not proceed.

In addition, in order to deal with abnormalities, at addresses other than the above-mentioned addresses that can be specified during normal times, the abnormality notification data “H” is stored in the 4th data bit (D3) from the lower order, and When the address is designated, the abnormality notification data “H” is output from D3.

Next, the operation of the present apparatus having the above configuration will be described.

In the device shown in FIG. 1, the operation of the power supply synchronization detection device 17 according to the present invention will be described with reference to FIGS. 2 and 3. It should be noted that, in FIG. 1, the description of the operation of the other elements has already been described in detail, and therefore will be omitted here.

Now, in FIG. 2, the voltage signals U, V, W of each phase of U, V, W detected by the AC voltage detector 13 are 60 ° phase delay circuits 19A-1
When it is input to 9C, the phase is delayed by 60 ° here, and the signal is given to the logic detection circuits 20A to 20C and converted into a logical "H" signal or "L" signal depending on the level, and the output signal 20a is output.
It will be ~ 20c. This state is shown in FIG.
It is a figure of (9). The output signals 20a to 20c of the logic detection circuits 20A to 20C are used to specify the lower address of the ROM 21,
Further, the upper address of the ROM 21 is designated by the output of the frequency divider circuit 25, and when the storage data of this designated address is read, the adder 22 outputs the output data (from the ROM 21 of the data output terminals D0 to D2 ( Voltage signals) 21a to 21c are added and the signal 22a is given to the voltage smoothing circuit 23. The voltage smoothing circuit 23 smoothes the signal 22a, and the voltage oscillating circuit (hereinafter,
The signal 23a is provided to the (referred to as VCO) 24. The VCO 24 outputs a square wave pulse having a frequency corresponding to the voltage 23a. Here, the VCO 24 generates a pulse having a frequency corresponding to the input voltage ((1) in FIG. 3) and outputs a pulse having a constant frequency if the input voltage is constant. That is, when the output from the voltage smoothing circuit 23 settles down to a constant level, VCO2
The output pulse signal 24a from 4 becomes a pulse having a constant frequency. The frequency divider circuit 25 receives the pulse signal 24a and divides it to generate frequency-divided signals 25a to 25d. That is, when the pulse signal 24a settles at a constant frequency, the pulse signal 24a is divided into 1/2, 1/4, 1/8, 1/16 as shown in (2) to (5) of FIG. Generate a divided signal. By the way, the logic signals 20a to 20c and the frequency-divided signals 25a to 25d are connected to the address lines of the ROM 21, and the voltage signals 21a to 21c are output by the address signals. That is, in the ROM, the data of 20a set in the lower address of the ROM 21 is "L" for the address modes "0" to "11" determined by the frequency dividing signals 25a to 25d and the frequency divider clear output 25d. The ROM is set so as to output a signal as shown in FIG. 3 (10) to the data line of D0, that is, the signal 21a by "H". In the diagram of FIG. 3 (10), the solid line in each of the above modes is when the signal 20a is "L" and the dotted line is the signal 20a is "H".
The output state at the time of is shown. Similarly, depending on the address mode, the data of 20b and 20c is "L" or "H".
The ROM is set to output the signal like 2).
Now, in the address modes "0" to "11", assuming that the voltage signals U, V, W are in the states as shown in FIG. 3 (6) (that is, the logic signals 20a to 20c are shown in FIG. ) ~
(If it is in a state like (9)), ROM2 as described above
Since 1 is set, the output signals 21a to 21c have output waveforms as shown in (14) to (16) of FIG. Also adder 22
The signal 22a added in step (17) is as shown in FIG. Then, the signal 22a is given to the VCO 24 as a constant voltage 23a through the voltage smoothing circuit 23, and an output signal 24a having a constant frequency is outputted from the VCO 24 and given to the frequency dividing circuit 25. 25a to 25d are output, and the address mode returns to "0" when proceeding from "0" to "11". This state means that the voltage detection signal is synchronized with the phase difference of the phase voltage of the AC power supply bus.
Therefore, the address area is not specified when an error occurs.
The data of D3 of ROM21 is "L", and this data is sent to signal 17a.
The electromagnetic contactor excitation circuit 18 received as is kept off and the electromagnetic contactor 3 is not opened.

Now, for example, in the device of FIG. 1, the voltage signals U, V, W of FIG. 2 become abnormal due to an abnormality of the voltage detector 13 or the like during the operation of the inverter device 2, or the signal is the phase of the AC power bus. When the synchronization pattern is shifted with respect to the voltage phase and the output of the voltage value of each phase after passing through the logic circuits 20A to 20C does not become the normal data pattern, for example, 20a to 20c are all "H". When all are "L", the address that can be specified in ROM21 corresponds to the area other than the normal time. Since the data of D3 is "H" in this area, the signal 17a which is the output of D3 of ROM is "H". "It becomes. That is, as described above, R
For each address mode, the OM21 is in what state the voltage signals U, V, W (which are used to specify the lower address A0-A2 of the ROM 21 through the logic detection circuits 20A-20C). In this case, it becomes possible to recognize whether the signal is synchronized with the bus power supply.
When the signals 20a to 20c deviate from (7) to (9) in FIG. 3,
The output signal 17a from the D3 data output line of the ROM 21 becomes "H". Then, this signal 17a is given to the electromagnetic contactor excitation circuit 18 of FIG. 1 to turn off the electromagnetic contactor 3,
The power supply side inverter device 2 is disconnected from the main circuit.

As a result of the above, when the synchronous state shifts with respect to the phase of each phase voltage of the AC bus, or when a voltage abnormality or the like occurs, the AC power supply of the inverter device can be cut off.
It becomes possible to protect the inverter device and thus the entire system.

[Effects of the Invention] As described above, according to the present invention, a power width adjustable pulse width modulation (PWM) type inverter is arranged to obtain a signal synchronized with the phase voltage of an AC power bus. Then, in an inverter device that controls the DC bus voltage to be constant regardless of the operating state, during control, if the power supply synchronization signal is out of synchronization with the phase of the power supply, it is considered as an abnormality of the voltage detector, By turning off the electromagnetic contactor on the AC power supply side, the inverter device on the power supply side can be separated from the main circuit, and an inverter protection device that can appropriately protect the inverter device on the power supply side and the control device for the entire system is provided. can get.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an inverter device to which a protection device according to an embodiment of the present invention is added, and FIG. 2 is a circuit configuration diagram showing details of a power supply synchronization detection device which is a main part of the present invention.
FIG. 4 is a timing diagram showing the details of the operation of the power supply synchronization detection device, and FIG. 4 is a diagram showing the configuration of a conventional inverter device. 1 ... AC power bus, 2 ... Inverter device, 3 ... Electromagnetic contactor, 4 ... Reactor, 5 ... Variable voltage variable frequency control device, 7 ... Electric motor, 8 ... Smoothing capacitor, 9
...... DC voltage detector, 10 ...... Voltage controller, 11 …… Reference setting device, 12 …… Current reference command device, 13 …… AC voltage detector, 14 …… Current controller, 15 …… Current detector , 16 …… PWM
Control device, 17 ... Power supply synchronization detection device, 18 ... Electromagnetic contactor excitation circuit, 19A-19C ... 60 ° phase delay circuit, 20A-20C ...
... Logic detection circuit, 21 ... ROM, 22 ... Adder, 23 ...
… Voltage smoothing circuit, 24 …… Voltage oscillator circuit, 25 …… Dividing circuit.

Claims (1)

[Claims] 1. A pulse width modulation type inverter device capable of adjusting a power factor, which synchronizes with a power source input from an AC power source through an electromagnetic contactor, and converts AC to DC based on the power source synchronizing signal, and An inverter device comprising a smoothing capacitor for smoothing the DC output of the inverter device, and controlling the DC output voltage to be a set voltage. In the inverter device, a voltage detector for detecting each phase voltage of the AC power supply and detection by this voltage detector Each of the AC power supply each phase voltage is binarized, when the pattern is a pattern that is not synchronized with the phase difference of the phase voltage of the AC power bus, a detection device for detecting an abnormality of the voltage detector, and this detection device An operation device for opening the electromagnetic contactor according to an abnormality detection output to disconnect the inverter device from an AC power source. Protection device.