JPH0786205A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

(57) [Summary] (Modified) [Purpose] A semiconductor device having a high degree of integration is obtained by burying a space between adjacent gate electrodes with a conductive layer and planarizing the upper surface of the gate electrodes. [Structure] A two-layer poly-Si stack gate of an EPROM consisting of a floating gate 11, a control 12 and an oxide film 20 is formed on a P-type Si substrate 10, and an N region is formed in a drain region.
Type impurities are introduced to form the active region 14, and then the thermal oxide film 1 is formed.
3 is formed. After etching a predetermined portion of the oxide film to open a contact hole for the drain region, N-type poly-Si is deposited on the entire surface by a CVD method, and poly-Si 15 is buried between adjacent gate electrodes. Next, the gate electrode and the buried poly-Si are flattened by anisotropic etching. B over the entire surface
After the PSG insulating film 16 is formed, the contact hole is opened and the drain electrode wiring 17 is laminated to connect the wiring to poly-Si. With the above configuration, the distance between the two adjacent gate electrode ends 18 and 19 can be set to about 1.8 μm, and the degree of integration can be greatly improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a contact in a drain region of the semiconductor device and a method for forming the contact.

[0002]

2. Description of the Related Art FIG. 2 shows an example of a conventional semiconductor device.
6A to 6D are cross-sectional views of a process of forming a contact in a drain region of an EPROM. In FIG. 2A, 1 is Si
Substrate 2, drain region 3, oxide film 4, floating gate 5, control gate 5, and floating gate 4 and control gate 5 form a two-layer polysilicon gate. Next, as shown in FIG. 2B, an insulating film 6 is further formed on the oxide film 3, and the oxide film 3 and the insulating film 6 are selectively removed to form a contact hole, and then, FIG. As described above, the conductive layer 7 to be the drain electrode wiring is formed.

Here, when forming a contact in the drain region of the bit line of the EPROM, it is necessary to open a contact hole in the flat portion of the insulating film in order to stabilize the process. However, in the above-described conventional method, since the insulating film is directly deposited on the EPROM having a large step, in consideration of the flatness of the insulating film, a certain allowance is provided from the gate electrode end portions 8 and 9. Must open. Therefore, adjacent Es
The PROM gate electrode interval (distance between the gate electrode end portions 8 and 9) needs to be about 2.8 μm, which hinders high integration.

[0004]

As described above, in order to form a contact in the drain region of the bit line of the semiconductor device, a contact hole is opened in the flat portion of the insulating film in order to stabilize the process. However, in the conventional technique, the insulating film is directly deposited on the gate electrode having a large step. It had to be opened with a margin interval. Therefore, the distance between adjacent gate electrodes becomes large, which hinders high integration.

Further, in Japanese Patent Application Laid-Open No. 60-140870, contact holes are opened in portions of the insulating film formed on the substrate and the gate electrode on the gate electrode and the source / drain regions, and the openings are buried. The invention of burying with a contact layer is disclosed. However,
In this invention, the insulating film is not flattened,
It is conceivable that the wiring layer formed thereon may be hindered.

Further, Japanese Patent Laid-Open No. 61-216478 discloses an invention in which a conductive layer on the source and drain electrodes is covered with a silicon nitride film and a silicon oxide film, and then polysilicon is embedded between them to form a gate electrode. It is disclosed. However, even in the present invention, the adjacent two
It is not disclosed to flatten the two gate electrodes and the insulating film on the polysilicon embedded between the gate electrodes, and it is considered that the wiring layer formed thereover may be hindered. In addition, there is a problem that the manufacturing process becomes complicated because it is necessary to form a silicon nitride film on the upper surface of the gate electrode in order to bury the polysilicon and remove the silicon nitride film after burying the polysilicon. It was

The present invention has been made in order to solve the above-mentioned problems in the prior art, and a gap between adjacent gate electrodes is filled with a conductive layer to planarize the upper surface of the gate electrode to achieve a degree of integration. It is an object to obtain a semiconductor device with high cost.

[0008]

A semiconductor device according to the present invention comprises at least two adjacent gate electrodes formed on a semiconductor substrate and a first conductive layer formed between the at least two adjacent gate electrodes. An insulating layer selectively formed on the at least two adjacent gate electrodes and the first conductive layer, and a second conductive layer formed on the insulating layer and the exposed first conductive layer. It is characterized by having.

The semiconductor device of the present invention is characterized in that the gate electrode is a two-layer polysilicon stack gate.

Further, in the method of manufacturing a semiconductor device according to the present invention, the step of forming at least two adjacent gate electrodes on the semiconductor substrate and thermally oxidizing them is the first conductivity between the at least two adjacent gate electrodes. Planarizing the at least two adjacent gate electrode surfaces and the first conductive layer surface by embedding with a layer and then etching back, on the at least two adjacent gate electrodes and the first conductive layer. Exposing the first conductive layer by selectively removing the insulating layer after depositing the insulating layer, and further forming a second conductive layer on the insulating layer and the exposed first conductive layer It is characterized by including a process.

[0011]

According to the present invention, the distance between the contact hole in the source region or the drain region and the gate electrode can be narrowed, so that the distance between adjacent gate electrodes can be narrowed and the integration degree can be improved. A high semiconductor device can be obtained. Further, unlike the conventional case, it is not necessary to make contacts in the valleys between the adjacent gate electrodes, and all contacts on the memory can be formed at the same height, so that the contact formation yield in the memory region is improved. Further, since the gate electrode and the portion between adjacent gate electrodes are flattened, there is no step breakage of the conductive layer (second conductive layer) formed on the gate electrode and the yield reliability of the wiring can be improved. it can.

Further, according to the present invention, a good thin film can be obtained without selecting a thin film forming material, a thin film forming apparatus, or a substrate (which can also be applied to, for example, a plastic substrate) to be used.

【Example】

Hereinafter, the present invention will be described in more detail with reference to an example using an EPROM. FIG. 1 shows a method of manufacturing a semiconductor device according to the present invention. First, as shown in FIG. 1A, an EPROM including a floating gate 11, a control gate 12, and an oxide film 20 on a substrate 10.
Then, a two-layer polysilicon stack gate is formed, an impurity having a conductivity type opposite to that of the substrate is introduced into a region to be a drain, an active region 14 is formed, and then thermal oxidation is performed to form a thermal oxide film 13. Here, a P-type silicon substrate is used as the substrate 10.
N-type impurities are used as impurities. In this embodiment, the implantation amount and the implantation energy of this N-type active region are 6E15 / cm ² and 50 KeV, respectively, and the subsequent thermal oxidation is performed at 950 ° C. for 10 minutes. Up to this point, it can be manufactured in the same manner as the conventional technique. Next, as shown in FIG. 1B, a predetermined portion of the oxide film 13 is etched to open a contact hole for the drain region. After that, by vapor-phase growth at 650 ° C., about 100 N-type polysilicon is deposited on the entire surface.
00Å is deposited, and polysilicon 15 is embedded between adjacent gate electrodes. Next, as shown in FIG.
The gate electrode and the buried polysilicon are planarized by etching back the polysilicon 15. Here, the etch back of the polysilicon 15 is CCl ₄ , H
This is performed by anisotropic etching with Br or the like. After that, unnecessary polysilicon 1 by photolithography
5 is etched to separate adjacent bit lines (in the depth direction of FIG. 1C). Next, FIG. 1 (d)
As shown in, the insulating film (BPSG
The film 16 is formed by about 8000Å. Finally, as shown in FIG. 1E, a contact hole is formed in the insulating film by photolithography, drain electrode wiring 17 is laminated, and a contact between the polysilicon 15 and the wiring is formed.

According to the above configuration, the gate electrode end portion 1
The spacing between 8 and 19 can be about 1.8 μm,
The degree of integration can be significantly increased as compared with the conventional technology.

In the present invention, the description has been made on at least two adjacent gate electrodes formed on the semiconductor substrate. This means that if at least two adjacent gate electrodes among a large number of gate electrodes formed on the semiconductor substrate have the above-mentioned configuration, they are within the scope of the present invention.

Further, although the case where the contact is formed on the drain region has been described in the present embodiment, it goes without saying that the present invention can be applied to the case where the contact is formed on the source region.

Further, in the present embodiment, the EPROM in which the height of the gate electrode is relatively high and the effect of the present invention is more remarkable is taken as an example. It can also be applied to semiconductor devices.

[0018]

As described above, according to the present invention, the distance between the contact hole and the gate electrode can be narrowed, so that the distance between the adjacent gate electrodes can be narrowed and the degree of integration is high. A semiconductor device can be obtained. Further, unlike the conventional case, it is not necessary to make contacts in the valleys between the adjacent gate electrodes, and all contacts on the memory can be formed at the same height, so that the contact formation yield in the memory region is improved. further,
Since the gate electrode and the portion between adjacent gate electrodes are flattened, there is no step breakage of the conductive layer (second conductive layer) formed thereon, and the yield reliability of the wiring can be improved.

[Brief description of drawings]

1 is a cross-sectional view of a step of forming a contact in a drain region of an EPROM according to the present invention.

FIG. 2 is a cross-sectional view of a process of forming a contact in a drain region of a conventional EPROM.

[Explanation of symbols]

 1,10 Substrate 2,11 Floating Gate 3,12 Control Gate 4,13,20 Oxide Film 5,14 Active Region (Drain Region) 15 Conductive Layer (Buried Polysilicon) 6,16 Insulating Film 7,17 Conductive Layer (Wiring) ) 8, 9, 18, 19 Gate electrode end

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location H01L 21/8247 29/788 29/792

Claims (3)

[Claims] 1. A at least two adjacent gate electrodes formed on a semiconductor substrate, a first conductive layer formed between the at least two adjacent gate electrodes, the at least two adjacent gate electrodes, and A semiconductor device comprising: an insulating layer selectively formed on a first conductive layer; and a second conductive layer formed on the insulating layer and the exposed first conductive layer. 2. The semiconductor device according to claim 1, wherein the gate electrode is a two-layer polysilicon stack gate. 3. A method of forming at least two adjacent gate electrodes on a semiconductor substrate and oxidizing them, the method comprising the steps of filling a space between the at least two adjacent gate electrodes with a first conductive layer and then etching back. At least 2
Planarizing two adjacent gate electrode surfaces and the first conductive layer surface, selectively depositing the insulating layer after depositing an insulating layer on the at least two adjacent gate electrodes and the first conductive layer. Removing the first conductive layer to expose the first conductive layer, and forming a second conductive layer on the insulating layer and the exposed first conductive layer. .