JPH0786567A - Semiconductor device - Google Patents

Abstract

(57) [Abstract] [PROBLEMS] To provide a reverse conduction switching device having a separating portion for completely separating a switching device and a diode. [Structure] In the cross section of the disk-shaped semiconductor substrate 10, this substrate is divided into a GTO thyristor portion B, a diode portion D, and a separation portion C that divides both portions. Thyristor P ⁺
The base region 1 is completely separated from the P ⁻ anode region 2 of the diode portion by the isolation region 3 of the isolation portion C which is a part of the N ⁻ base region 11. The leak current when a reverse bias is applied to the GTO thyristor generated in the case of the conventional reverse conducting thyristor in which the P ⁺ base region 1 and the P ⁻ anode region 2 are in contact is eliminated. It is also possible to form a resistance film of polysilicon on the P ⁺ base region 1 and the P ⁻ anode region 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to an isolation structure between a switching device section and a diode section of a reverse conduction switching device.

[0002]

Reverse conduction switching devices, for example,
The reverse conduction type gate turn-off thyristor is usually a GTO.
(Gate Turn Off) A thyristor and a free wheel diode connected in anti-parallel with this GTO thyristor are integrated on one semiconductor substrate. It is a semiconductor device effective for downsizing devices such as inverters using GTO thyristors. In the semiconductor substrate in which the reverse conducting GTO thyristor is formed, the thyristor portion in which the GTO thyristor is formed and the diode portion in which the free wheel diode is formed are separated by a resistor. FIG. 10 is a plan view showing a half of a main surface of a conventional anode short type reverse conducting GTO thyristor, and FIG.
0 is a cross-sectional view taken along line AA ′ of 0, showing half of a reverse conducting GTO thyristor. As shown in FIG. 11, a thyristor portion B is formed in the center of the semiconductor substrate 10 and a diode portion D is formed in the periphery thereof, and a separation portion C is arranged at the boundary thereof. An N ⁻ base region 31 is formed on the semiconductor substrate 10, and a P ⁺ base region 32 and an N ⁺ base region 33 are formed on the upper surface and the lower surface of the N ⁻ base region 31. In the N ⁺ base region 33 of the thyristor portion B, a plurality of P ⁺ emitter regions 34 are selectively formed,
A plurality of N ⁺ emitter regions 35 are selectively formed on the P ⁺ base region 32.

The thickness of the P ⁺ base region 32 is about 80 μm.
And the thickness of the N ⁻ base region 31 is about 650 μm. The thickness of the N ⁺ base region 33 is about 20 μm. In the isolation portion C, the surface of the P ⁺ base region 32 is selectively removed by etching to form a trench 36 having a depth of about 50 μm. The base region 32 below the trench 36 has a low impurity concentration up to the diode portion (concentration of about 10 × 10 ^15).
cm ⁻³ ) P ⁻ base region 321, and the portion below the trench 36 functions as the isolation resistance region RGK. The trench 36 surrounds the thyristor portion B and separates the thyristor portion B and the diode portion D. A is formed in the N ⁺ emitter region 35 and the P ⁻ base region 321 of the diode portion D.
a cathode electrode 38 made of a metal layer such as 1 is formed,
These are collected to form the cathode electrode K. A gate electrode 39 is formed on the P ⁺ base region 32 of the thyristor portion B, and these are collected to form a gate electrode G. By covering the gate electrode 39 with the insulating film 40, the cathode electrode 38 and the gate electrode 39 are insulated from each other. On the other hand, an anode electrode 41 made of a metal layer such as Al is formed on the N ⁺ base region 33 and the P ⁺ emitter region 34, and the anode electrode 41 is connected to the anode extraction electrode A. The anode electrode 41 short-circuits the N ⁺ base region 33 and the P ⁺ emitter region 34 to form a short emitter structure. This structure improves the turn-off ability.

FIG. 12 is an equivalent circuit diagram of a reverse conducting GTO thyristor. The GTO thyristor 42 constitutes the thyristor part B shown in FIG. 11, and includes the P ⁺ emitter region 34 and N ^−.
It comprises a base region 31, a P ⁺ base region 32 and an N ⁺ emitter region 35. Free wheel diode 43
Constitutes the diode portion D, and includes a P ⁻ base region 321,
It has an N ⁻ base region 31 and an N ⁺ base region 33, and is connected in antiparallel with the GTO thyristor 42.
The isolation portion C is configured by the isolation resistance RGK of the P ⁻ base region 321 below the trench 36. Separation resistance RGK
Is inserted between the gate and the cathode of the GTO thyristor 42 on the equivalent circuit. This reverse conducting GTO thyristor reverse biases the PN junction formed by the N emitter region 35 and the P base region 32 to suppress electron injection from the N ⁺ emitter region 35 to the P ⁺ base region 32 when the GTO thyristor is off. You need to keep it. Therefore,
When turned off, a reverse bias is applied to the cathode electrode 38 and the gate electrode 39. At this time, since a reactive current flows through the separation resistor RGK, the load on the gate drive circuit (not shown) becomes heavy. In order to reduce this burden, the resistance value of the separation resistor RGK should be as large as possible. In this example, the separation resistance RGK is about 70 to 100Ω.

[0005]

A reverse conduction type switching device, for example, a reverse conduction GTO thyristor is used by being connected in antiparallel with a free wheel diode. Then, during the OFF period of switching, it is necessary to continue to apply a negative bias of 2 to 18 V between the gate and cathode of the GTO thyristor. As described above, the P base region and the P anode region are electrically connected as the same region. Therefore, if a negative bias is applied between the gate and the cathode of the GTO thyristor, a reverse current will flow through the isolation resistance. Therefore, the power supply capacity of the gate circuit must be made larger than that of the GTO thyristor alone, and its loss is also large. The separation resistance value of the conventional reverse conducting GTO thyristor is about 70-
Although it is about 100Ω, its resistance value varies greatly depending on the mesa etching thickness of the trench portion and the diffusion specification of the P base region (P anode region of the diode).
The temperature dependency of this separation resistance is strong, and the resistance value decreases at low temperatures. Therefore, there is a problem that it is difficult to control the separation resistance during manufacturing, and it is difficult to design and set the gate circuit during use. The present invention has been made under such circumstances, and an object of the present invention is to provide a reverse conduction switching device provided with an isolation portion having an isolation structure capable of completely isolating a switching device and a diode. ing.

[0006]

According to the present invention, the first conductivity type base region of the switching device and the first conductivity type anode region of the free wheel diode are completely separated by the second conductivity type isolation region. It is characterized by That is, the semiconductor device of the present invention includes a semiconductor substrate having first and second main surfaces, a first conductive type first semiconductor region formed in the semiconductor substrate, and a first main surface of the semiconductor substrate. A second semiconductor region of a second conductivity type that is formed on a surface and is adjacent to the first semiconductor region, and a second main surface of the semiconductor substrate that corresponds to the second semiconductor region. The third of the second conductivity type adjacent to the first semiconductor region
Second semiconductor region formed on the first main surface of the semiconductor substrate and adjacent to the second semiconductor region.
And a second conductive type fifth region formed on the first main surface of the semiconductor substrate and adjacent to the first semiconductor region.
A semiconductor region, a first conductivity type isolation region formed on the first main surface of the semiconductor substrate, and formed between the second semiconductor region and the fifth semiconductor region; 1
Formed on the first semiconductor region and the third semiconductor region
Electrode, a second electrode formed on the fourth semiconductor region and the fifth semiconductor region, and a third electrode formed on the second semiconductor region. I am trying. An insulating film is formed on the first main surface of the semiconductor substrate so as to cover the junction between the second semiconductor region and the isolation region and the junction between the fifth semiconductor region and the isolation region. May be. The second semiconductor region and the fifth
Of the semiconductor substrate so as to connect to the semiconductor region of
A resistance layer may be formed on the main surface of the.

[0007]

The second semiconductor region and the fifth semiconductor region, for example, the first conductivity type base region of the switching device and the first conductivity type anode region of the free wheel diode are separated by the second conductivity type separation region. Since it has been
The two regions are completely separated, the leakage current is eliminated when the negative bias of the switching device is applied, and the same gate circuit as that of a normal switching device can be used. Further, when the resistance layer is provided on the surface of the isolation region, the potential on the surface of the semiconductor substrate is stabilized, and thus the breakdown voltage reliability is improved.

[0008]

Embodiments of the present invention will be described below with reference to the drawings. First, a first embodiment will be described with reference to FIGS. In this embodiment, a reverse conducting GTO thyristor will be described as an example of the reverse conducting type switching device. FIG. 1 shows a half of a disk-shaped semiconductor substrate having a diameter of about 91 mm. 2 is an enlarged cross-sectional view of the R region of FIG.
FIG. 3 is an equivalent circuit diagram of FIGS. 1 and 2. A thyristor portion B is formed in the center of the semiconductor substrate 10 having a bevel structure, and a diode portion D is formed in the periphery thereof, and the two portions B and D are separated by an intermediate separating portion C. On the silicon semiconductor substrate 10, the N ⁻ base region 11 of the first semiconductor region is formed, and on the upper surface and the lower surface of the N ⁻ base region 11, the thyristor portion B has the second semiconductor region P ^+. N in the base region 1, the thyristor part B and the diode part D
^{A +} base region 15 is formed. A P ⁺ emitter region 16 which is a third semiconductor region is selectively formed in the base region of the thyristor portion B, and P ^{+ of the} thyristor portion B is formed.
A plurality of mesa-shaped N ⁺ emitter regions 14, which are fourth semiconductor regions, are selectively formed on the base region 1.

In addition, the N ^- base region 1 of the diode portion D
The upper surface of 1 is a fifth semiconductor region having a thickness of about 80 μm.
P ⁻ anode region 2 is formed. The thickness of the P ⁺ base region 1 from the substrate surface is about 80 μm, and N ⁻
The thickness of the base region 11 is about 650 μm. The thickness of the N ⁺ base region 15 is about 20 μm. The separating portion will be described with reference to FIG. 2 which is an enlarged cross-sectional view of the separating portion of FIG. 1 and a region R showing the periphery thereof. The thyristor section B and the diode section D are separated by the separation section C.
The P ⁺ base region 1 of the thyristor portion B and the P ⁻ anode region 2 of the diode portion D are connected to each other in the past, but the isolation region 3 is interposed in the present invention. The isolation region 3 is a part of the N ⁻ base region 11,
It has an impurity concentration of about 2.1 × 10 ¹³ cm ⁻³ .
The P ⁺ base region 1 has a high impurity concentration and its surface is about 1 × 10 ¹⁷ to 1 × 10 ¹⁸ cm ⁻³ . On the other hand, the P ⁻ anode region 2 has a low impurity concentration,
The surface concentration is about 1 × 10 ¹⁷ cm ⁻³ . The base region 1 and the anode region 2 are separated by the separation region 3 by about 20 to 500 μm.

On the first main surface of the semiconductor substrate 10, a first insulating film 4 made of SiO ₂ and BPSG (Boron-doped Phospho-Sili) so as to cover each junction of the isolation region 3.
A second insulating film 5 made of cateGlass) and a third insulating film 6 made of polyimide are sequentially laminated. In this way, since the junction is protected by the high resistance insulating film, the separation performance is improved. The insulating material is not limited to those mentioned above, and any existing high resistance material can be used. The thickness of the cathode electrode 8 (anode electrode of the diode part) is adjusted so that these insulating films do not contact the cathode electrode plate 7 when an external electrode (not shown) is pressed against the cathode electrode 8 via the electrode plate 7 (K). Is greater than these total thicknesses,
For example, it should be about 14 μm. On the N ⁺ base region 15 and the P ⁺ emitter region 16, an anode electrode 12 made of a metal layer having a thickness of about 14 μm, such as Al, which is a first electrode, is formed.
It is connected to an anode extraction electrode A (not shown). The anode electrode 12 short-circuits the N ⁺ base region 15 and the P ⁺ emitter region 16 to form a short emitter structure. This structure improves the turn-off ability. N ⁺
On the surfaces of the emitter region 14 and the P ⁻ anode region 2 of the diode portion D, a cathode electrode 8 made of a metal layer such as Al, which is a second electrode, is formed.

The cathode electrode plate 7, which is a collector electrode made of Mo or the like, is pressed against the cathode electrode 8. A gate electrode 9 which is a third electrode is formed on the P ⁺ base region 1 of the thyristor portion B, and a gate lead electrode G (not shown) is electrically connected to this. By covering the gate electrode 9 with the insulating film 6, the cathode electrode 8 and the gate electrode 9 are insulated from each other. Figure 3
It is an equivalent circuit diagram of the reverse conduction type GTO thyristor of this embodiment. The GTO thyristor 18 constitutes the thyristor part B shown in FIG. 1, and further includes a P ⁺ emitter region 16, an N ⁻ base region 11, a P ⁺ base region 1 and an N ⁺ emitter region 14. The free wheel diode 19 constitutes the diode part D, includes the P ⁻ anode region 2, the N ⁻ base region 11 and the N ⁺ base region 15, and includes the GTO.
The thyristor 18 is connected in antiparallel. Separation part C
Does not have a separation resistance RGK. On the side surface of the semiconductor substrate 10, an insulating protector 17 having a high insulating property such as a silicone resin is provided for insulating protection.

Next, a second embodiment will be described with reference to FIG. The figure is a cross-sectional view showing the right half of the central cross section of a disk-shaped semiconductor substrate. The reverse conducting GTO thyristor of this embodiment comprises a thyristor section, a diode section and a separating section for separating the thyristor section and the diode section. The GTO thyristor of the thyristor portion includes a P ⁺ emitter region 16, an N ⁻ base region 11, a P ⁺ base region 1 and a mesa-shaped N ⁺ emitter region 14. Free-wheeling diode of the diode unit, P ^-
It is provided with an anode region 2, an N ⁻ base region 11 and an N ⁺ base region 15, and is connected in antiparallel with the GTO thyristor. An isolation region 3 that forms a part of the N ⁻ base region 11 is formed in the isolation portion that separates the thyristor portion and the diode portion. N ⁺ base region 15 and P ⁺
On the emitter region 16, the anode electrode 12 made of a metal layer such as Al that is the first electrode is formed. N ⁺ emitter region 14 and P ⁻ anode region 2 of the diode portion
A cathode electrode 8 made of a metal layer such as Al, which is a second electrode, is formed on the surface of the. The cathode electrode plate 7 which is a collector electrode made of Mo or the like is pressed against the cathode electrode 8. A gate electrode 9, which is a third electrode, is formed on the P ⁺ base region 1 of the thyristor portion.

By covering the gate electrode 9 with the insulating film 6, the cathode electrode 8 and the gate electrode 9 are insulated from each other. On the side surface of the semiconductor substrate 10, an insulating protector 17 having a high insulating property such as a silicone resin is provided for insulating protection. The above configuration is the same as that of the first embodiment. Similar to the first embodiment, the first insulating film 4 made of SiO ₂ and the _second insulating film made of BPSG are formed on the first main surface of the semiconductor substrate 10 so as to cover the junctions of the isolation regions 3. The insulating film 5 and the third insulating film 6 made of polyimide are sequentially laminated. In the above-described first embodiment, when the external electrode (not shown) is pressed against the cathode electrode 8 via the electrode plate 7, the cathode electrode 8 (diode part) is prevented so that these insulating films do not contact the cathode electrode plate 7. The anode electrode) had to be thicker than these total thicknesses. In this embodiment as well, it is necessary to prevent the laminated insulating films from coming into contact with the cathode electrode plate 7. However, in this embodiment, the surface of the semiconductor substrate 10 in the isolation region 3 and its vicinity is lower than the surface of other portions. By doing so, the uppermost surface of the laminated insulating films is made lower than the surface of the cathode electrode 8. As a result, contact between these insulating films and the electrode plate 7 is prevented. In FIG. 4, the N ⁺ emitter region 14 is formed in a mesa shape.

In this embodiment, the surface of the semiconductor substrate is mesa-etched to form a mesa-shaped region. At this time, the isolation region 3 of the semiconductor substrate and the surface in the vicinity thereof are also mesa-etched at the same time to lower the surface. To do. Therefore,
It is possible to lower the surface of the separation region without increasing the number of steps. Therefore, the stacked insulating films 4 and 5 are
Are formed on the same low surface as the mesa-etched substrate surface on which the gate electrode 9 is formed. Then, the gate electrode 9 is protectively covered with the uppermost insulating film 6 of the stacked insulating films.

Next, a third embodiment will be described with reference to FIG. The figure is a cross-sectional view showing the right half of the central cross section of a disk-shaped semiconductor substrate. The reverse conducting GTO thyristor of this embodiment comprises a thyristor section, a diode section and a separating section for separating the thyristor section and the diode section. The GTO thyristor of the thyristor portion includes a P ⁺ emitter region 16, an N ⁻ base region 11, a P ⁺ base region 1 and a mesa-shaped N ⁺ emitter region 14. Free-wheeling diode of the diode unit, P ^-
It is provided with an anode region 2, an N ⁻ base region 11 and an N ⁺ base region 15, and is connected in antiparallel with the GTO thyristor. An isolation region 3 that forms a part of the N ⁻ base region 11 is formed in the isolation portion that separates the thyristor portion and the diode portion. N ⁺ base region 15 and P ⁺
The anode electrode 12, which is the first electrode, is formed on the emitter region 16. A cathode electrode 8 serving as a second electrode is formed on the surfaces of the N ⁺ emitter region 14 and the P ⁻ anode region 2 of the diode portion. This cathode electrode 8
Then, the cathode electrode plate 7 such as Mo is pressed. A gate electrode 9, which is a third electrode, is formed on the P ⁺ base region 1 of the thyristor portion. By covering the gate electrode 9 with the insulating film 6, the cathode electrode 8 and the gate electrode 9 are insulated from each other. On the side surface of the semiconductor substrate 10, an insulating protector 17 having a high insulating property such as a silicone resin is provided for insulating protection. The above configuration is the same as that of the first embodiment.

Similar to the first embodiment, a first insulating film 4 made of SiO ₂ and BPSG are formed on the first main surface of the semiconductor substrate 10 so as to cover the junctions of the isolation region 3. Second insulating film 5 and third insulating film 6 made of polyimide
Are sequentially laminated. In the above-described first embodiment, when the external electrode (not shown) is pressed against the cathode electrode 8 via the electrode plate 7, the cathode electrode 8 (diode part) is prevented so that these insulating films do not contact the cathode electrode plate 7. The anode electrode) had to be thicker than these total thicknesses. In this embodiment as well, it is necessary to prevent the laminated insulating films from contacting the cathode electrode plate 7. However, in this embodiment, the height of the surface of the semiconductor substrate 10 in the separation region 3 and its vicinity is not changed, and It is characterized in that a recess is formed in a part of the surface of the electrode plate 7 that contacts the cathode electrode 8. That is, the isolation region 3 in which the insulating film 6 and the like are laminated
And the concave portion 7 in the cathode electrode plate 7 arranged on the vicinity thereof.
1 is formed. As a result, contact between these insulating films and the electrode plate 7 is prevented. Only by partially deforming the electrode plate 7, it is possible to prevent contact between the two without considering the thickness of the metal layer such as Al that constitutes the cathode electrode or the like.

Next, a fourth embodiment will be described with reference to FIG. The figure is a partial cross-sectional view showing a separation part in the central cross section of a disk-shaped semiconductor substrate and the vicinity thereof. The reverse conducting GTO thyristor of this embodiment comprises a thyristor section, a diode section and a separating section for separating the thyristor section and the diode section. In the above-described embodiment, the separating unit is N
^- the separation region 3, P of the P ⁺ base region 1 and the diode portion of the thyristor portion ^{- -} N is a part of the base region 11 and anode region 2 is separated, it is separated. This embodiment is characterized in that the P ⁺ guard ring 20 is formed in this isolation region 3, and the other structure is the same as that of the first embodiment. The depth of the P ⁺ base region 1 and the P ⁻ anode region 2 from the substrate surface is about 80 μm, and the depth of the guard ring 20 from the substrate surface is also about 8 μm.
It is about 0 μm. Although the size of the guard ring varies depending on the rating of the element, a plurality of guard rings 20 are formed substantially in the center of the isolation region 3, and the widths W1 and W2 of the guard rings near the substrate surface need to be 20 μm or more. is there. Further, the distance D1 between the P ⁺ base region 1 and the guard ring 20, the distance D2 between the guard rings 20 and the distance D3 between the guard ring 20 and the P ⁻ anode region 2 are
Both have a size of about 20 to 500 μm. The surface concentration of the P ⁺ base region 1 is about 10 ¹⁸ cm ⁻³ ,
^- the surface concentration of the anode region 2 is approximately 10 ¹⁷ cm ^-3. On the other hand, the surface concentration of the guard ring 20 is 10 ¹⁸ cm.
^{-It is} about ^-3 .

Next, a fifth embodiment will be described with reference to FIG. The figure is a partial cross-sectional view showing a separation part in the central part cross section of a disk-shaped semiconductor substrate and the vicinity thereof. The reverse conducting GTO thyristor of this embodiment comprises a thyristor section, a diode section and a separating section for separating the thyristor section and the diode section. In the above-described embodiment, the separating unit is N
^- the separation region 3, P of the P ⁺ base region 1 and the diode portion of the thyristor portion ^{- -} N is a part of the base region 11 and anode region 2 is separated, it is separated. Then, on the surface of the substrate in the isolation region 3 and in the vicinity thereof, a laminated insulating film, that is, a first insulating film 4 made of SiO ₂ , a second insulating film 5 made of BPSG, and a third insulating film made of polyimide. The film 6 is formed. In particular, the polyimide film 6 also covers and protects the gate electrode 9. This embodiment is characterized in that a resistance film is formed on the surface of the isolation region 3 and the substrate in the vicinity thereof, and the other structure is the first.
Is the same as the embodiment described above. The resistance film 21 is between the cathode electrode 8 on the diode portion and the P ⁺ base region 1 and the gate electrode 9 on the substrate surface which is mesa-etched and is lower than the other portions, and is formed in the thyristor portion. It is formed so as to straddle the first insulating film 4 and the second insulating film 5 between the P ⁺ base region 1 and the P ⁻ anode region 2 of the diode portion. Both ends of the resistance film 21 are in contact with the semiconductor substrate 10.

As the resistance film 21, a polysilicon film formed by patterning polysilicon deposited by CVD or the like is used. The polysilicon film 21 is the polyimide film 6
Protected by. By forming the resistance layer on the surface, the surface state is stabilized and the surface potential is stabilized. Therefore, the breakdown voltage reliability is improved. The circuit diagram of the semiconductor device of this embodiment is the same as the circuit diagram of the conventional semiconductor device shown in FIG. However, its resistance RGK is sufficiently larger than 70Ω.

Next, a sixth embodiment will be described with reference to FIG. The figure is a partial cross-sectional view showing a separation part in the central part cross section of a disk-shaped semiconductor substrate and the vicinity thereof. The reverse conducting GTO thyristor of this embodiment comprises a thyristor section, a diode section and a separating section for separating the thyristor section and the diode section. In the above-described embodiment, the separating unit is N
^- the separation region 3, P of the P ⁺ base region 1 and the diode portion of the thyristor portion ^{- -} N is a part of the base region 11 and anode region 2 is separated, it is separated. This embodiment is characterized in that the P ^-- region 22 is formed in this isolation region 3, and the other structure is the same as that of the first embodiment. In the first embodiment, the P ⁺ base region 1 of the thyristor portion and the P ⁻ anode region 2 of the diode portion are provided.
The isolation portion interposed between the isolation portions is composed of the N ⁻ isolation region 3. In this embodiment, the isolation portion is occupied by the P ^{− −} region 22 at a predetermined depth from the surface of the semiconductor substrate of the isolation portion. . The predetermined depth from the surface of the semiconductor substrate is about 30 to 70 μm, which is deeper than the N ⁺ emitter region of the thyristor portion. At this time, the depths of the P ⁺ base region 1 and the P ⁻ anode region 2 from the semiconductor substrate surface are both about 8
It is 0 μm. The surface concentration of the P ⁺ base region 1 is 10 ¹⁸
cm ⁻³ , and the surface concentration of the P ⁻ anode region 2 is
It is approximately 10 ¹⁷ cm ^-3 .

On the other hand, the surface concentration of the P ^-- region 22 is 10
It is about ¹⁵ cm ^-3 . The circuit diagram of the semiconductor device of this embodiment is the same as the circuit diagram of the conventional semiconductor device shown in FIG. 12, and its resistance RGK is about 70Ω. This embodiment is the same as the next embodiment, but is also characterized by its manufacturing method. Conventionally, when forming the P ⁺ base region 1 of the thyristor portion and the P ⁻ anode region 2 of the diode portion, impurities are ion-implanted into each region separately, and then the ion-implanted impurities in each region are, for example, Thermal diffusion is performed simultaneously under the conditions of 1200 to 1300 ° C. and about 100 hours. Among the embodiments of the present invention, the embodiment having the P ^{− −} region in the separation portion uses the method different from the conventional method. First, a P-type impurity for forming a P ^{− −} region is ion-implanted into the entire surface region of the semiconductor substrate 10, and then the ion-implanted impurity is subjected to, for example, 1200 to 1300 ° C. for about 20 hours. Heat is diffused to form a P ⁻ region on the entire surface region. Then, impurities for forming the P ⁺ base region 1 and the P ⁻ anode region 2 are separately ion-implanted into predetermined regions of the surface region of the semiconductor substrate on which the P ^{− −} region is formed. Then, the impurities ion-implanted into the respective regions are simultaneously subjected to thermal diffusion under the conditions of 1200 to 1300 ° C. and about 100 hours, and the P ⁺ base region 1 is formed.
And P ⁻ anode region 2 and a P ⁻ region 22 between the two regions are formed. Since ion implantation is used, masking can be performed and each region is formed with high precision.

Next, a seventh embodiment will be described with reference to FIG. The figure is a partial cross-sectional view showing a separation part in the central part cross section of a disk-shaped semiconductor substrate and the vicinity thereof. The reverse conducting GTO thyristor of this embodiment comprises a thyristor section, a diode section and a separating section for separating the thyristor section and the diode section. In the sixth embodiment, the separation unit is N
^- which is part of the base region 11 N ^- isolation region 3 and P
^The region 22 separates the P ⁺ base region 1 of the thyristor part from the P ⁻ anode region 2 of the diode part,
It is separated. This embodiment is characterized in that the P ^{− −} region 22 and the N ⁺ region 23 are formed in the isolation region 3, and the other structures are the same as those in the first and sixth embodiments. In the first embodiment, the isolation portion interposed between the P ⁺ base region 1 of the thyristor portion and the P ⁻ anode region 2 of the diode portion is composed of the N ⁻ isolation region 3.
In this embodiment, the N ⁻ separation region 3 is formed in the lower part of the separation part, the N ⁺ region 23 is formed in the upper part, and the P ^{− −} region 22 is formed in the center part thereof. In the separation portion, N formed on the uppermost portion and exposed to the semiconductor substrate
^{The +} region 23 has a depth of about 20 μm from the substrate surface, the same depth as the N ⁺ emitter region 14, and the same concentration. The P ^{− −} region 22 formed in the center is formed so that the distance from the bottom of the N ⁺ region 23 above it to the surface of the N ⁻ separation region 3 below it is about 20 to 50 μm. .

At this time, the depths of the P ⁺ base region 1 and the P ⁻ anode region 2 from the surface of the semiconductor substrate are both about 8
It is 0 μm. The surface concentration of the P ⁺ base region 1 is 10 ¹⁸
cm ⁻³ , and the surface concentration of the P ⁻ anode region 2 is
It is approximately 10 ¹⁷ cm ^-3 . On the other hand, the surface concentration of the P ^{− −} region 22 is about 10 ¹⁵ cm ⁻³ . The circuit diagram of the semiconductor device of this embodiment is the same as the circuit diagram of the conventional semiconductor device shown in FIG. 12, and its resistance RGK is about 70Ω. This embodiment uses the same ion implantation method as in the sixth embodiment, but the N ⁺ region 23 can be formed at the same time when the N ⁺ emitter region 14 is formed. It can be easily formed without increasing the number of steps.

Although the reverse conduction type switching device has been described using the GTO thyristor as the switching device in the embodiments, the present invention is not limited to this thyristor, and other switching devices such as IGBT and SCR may be used. You can Further, in the GTO thyristor used in the embodiment, the diode portion is formed in the peripheral portion of the disk-shaped semiconductor substrate, but the present invention does not need to dispose the diode portion only around the semiconductor substrate, It can also be applied to a thyristor having a diode formed in the center of a semiconductor substrate.

[0025]

As described above, since the P base region of the switching device and the P anode region of the free wheel diode are completely separated from each other, the leakage current when the switching device is negatively biased is eliminated. It can be used in the same gate circuit as the GTO thyristor. Further, since it is not necessary to control the separation resistance, the manufacturing becomes easy. Also in terms of device characteristics, the switching device and the free wheel diode are formed in independent diffusion regions, which facilitates optimization. Furthermore, when the resistance layer is formed on the surface of the semiconductor substrate, the surface potential is stabilized and the breakdown voltage reliability is improved.

[Brief description of drawings]

FIG. 1 is a sectional view showing a right side section of a semiconductor substrate according to a first embodiment of the present invention.

FIG. 2 is an enlarged sectional view of a region R of FIG.

FIG. 3 is a circuit diagram of the semiconductor device of FIG.

FIG. 4 is a partial sectional view of a semiconductor device according to a second embodiment.

FIG. 5 is a partial sectional view of a semiconductor device according to a third embodiment.

FIG. 6 is a partial sectional view of a semiconductor device according to a fourth embodiment.

FIG. 7 is a partial sectional view of a semiconductor device according to a fifth embodiment.

FIG. 8 is a partial sectional view of a semiconductor device according to a sixth embodiment.

FIG. 9 is a partial sectional view of a semiconductor device according to a seventh embodiment.

FIG. 10 is a partial plan view showing an upper half of a conventional semiconductor device.

11 is a cross-sectional view of the semiconductor device taken along the line AA ′ of FIG.

12 is a circuit diagram of the semiconductor device of FIG.

[Explanation of symbols]

1 P ⁺ base region 2 P ⁻ anode region 3 separation region 4 first insulating film 5 second insulating film 6 third insulating film 7 cathode electrode plate 8 cathode electrode 9 gate electrode 10 semiconductor substrate 11 N ⁻ base Region 12 Anode electrode 14 N ⁺ Emitter region 15 N ⁺ Base region 16 P ⁺ Emitter region 17 Insulation protector 18 GTO thyristor 19 Free wheel diode 20 Guard ring 21 Polysilicon resistance layer 22 P ^{− −} Region 23 N ⁺ region

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Takashi Fujiwara, No. 1 Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Inside the Tamagawa Factory, Toshiba Corporation (72) Inventor Akira Yanagisawa Komukai-shiba, Kawasaki-shi, Kanagawa No. 1 Incorporation company Toshiba Tamagawa factory

Claims (3)

[Claims] 1. A semiconductor substrate having first and second main surfaces, a first conductivity type first semiconductor region formed in the semiconductor substrate, and a first main surface of the semiconductor substrate. A second semiconductor region of a second conductivity type adjacent to the first semiconductor region, and a second semiconductor region of the semiconductor substrate corresponding to the second semiconductor region.
A third semiconductor region of the second conductivity type formed on the main surface of the semiconductor substrate and adjacent to the first semiconductor region, and formed on the first main surface of the semiconductor substrate and adjacent to the second semiconductor region. A fourth semiconductor region of a first conductivity type; a fifth semiconductor region of a second conductivity type formed on the first main surface of the semiconductor substrate and adjacent to the first semiconductor region; A first-conductivity-type isolation region formed on a first main surface and formed between the second semiconductor region and the fifth semiconductor region; the first semiconductor region and the third semiconductor; A first electrode formed on the region, a second electrode formed on the fourth semiconductor region and the fifth semiconductor region, and a third electrode formed on the second semiconductor region A semiconductor device comprising: 2. The first main surface of the semiconductor substrate is formed so as to cover the junction between the second semiconductor region and the isolation region and the junction between the fifth semiconductor region and the isolation region. The semiconductor device according to claim 1, wherein an insulating film is formed. 3. The resistance layer is formed on the first main surface of the semiconductor substrate so as to connect the second semiconductor region and the fifth semiconductor region. Item 2. The semiconductor device according to item 2.