JPH0787207B2 - Integrated circuit test equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention uses an electron beam or a laser beam as a means of observation and utilizes design data in a CAD system to obtain a device under test (DUT: Device). Under Tes
The present invention relates to an integrated circuit test method for automatically finding the location of a failure in step t).

[Conventional technology]

With the large scale and complexity of integrated circuits, the gate / pin ratio has reached a level of several thousand today, and conventional large scale integrated circuits that perform tests by exchanging signals only from external pins ( It has become impossible to detect faults inside the LSI by using the test equipment for LSI) and the fault simulation method based on this.

In response to this, non-contact test equipment such as electron beam test equipment and laser beam test equipment has appeared. By combining the electron beam test equipment with the CAD system of the integrated circuit and using the design data of the integrated circuit under test for comparison and judgment of the measurement results, a device that can detect the existence of a failure point on a gate-by-gate basis It has already been devised by the inventors of the present invention (Japanese Patent Application No. 60-39897).

This electron beam tester includes a scanning electron microscope, a test signal supply circuit, an image binarization circuit, an electronic computer,
A semiconductor integrated circuit design support CAD system, design data of a measurement target integrated circuit DUT created by the CAD system, and a two-dimensional analog image signal measured by the scanning electron microscope are fixed through the image binarization circuit. Create a "measurement logic map" that shows the two-dimensional distribution of the measurement logic values, which is obtained by capturing the image signals at each grid point or higher into a logic value of "1" or "0" at the timing of A measurement logic map creating program for the wiring pattern information of the DUT correspondingly read from the design data, and a logic expected value of the case wiring obtained by starting a logic simulator in the CAD system, A design map creation program for creating a "design logic map" that shows the one-dimensional distribution of the logic expected value that each grid point in the measurement logic map should take. And a logical map collation program for matching, which sequentially applies a test signal series of a certain length from the test signal supply circuit to the DUT installed in the electron microscope, and starts the measurement logical map creation program. The "measurement logic map" measured each time via the image binarization circuit and the corresponding "design logic map" obtained by starting the design logic map creation program are used by the logic map collation program. The measured logical value and the designed logical value for each wiring obtained by comparing and collating with each other can be output as a logical time chart with the theoretical value on one coordinate axis and the test signal application time on the other coordinate axis. In addition, after applying a test signal sequence of a certain length from the test signal supply circuit to the DUT including the sequential circuit, the test signal sequence is set to the final application state. Of the logical map of the “measurement logic map” obtained by activating the measurement logic map creation program with the fixed measurement signal and the corresponding “setting logic map” obtained by activating the design logic map creation program. By using a collation program to compare and collate, it is possible to detect whether or not a failure has occurred during the application of the test signal based on the difference between the two.

[Problems to be solved by the invention]

However, the above electron beam test apparatus has the following drawbacks. That is, since the above-mentioned device adopts the sequential operation method, the node name to be checked is determined while looking at the circuit diagram, the XY stage is moved so that the wiring having the node name is observed, and the test pattern is applied. , It was necessary to manually perform all operations such as stopping at the timing of measurement and measuring the logical value. In addition, since there is no clear guideline as to which node should be checked in what order among many nodes in the DUT, the failure location in the DUT could not be found efficiently.

[Means for solving problems]

In order to solve the above-mentioned problems, an integrated circuit test apparatus of the present invention comprises: (a) an electron beam or laser beam test apparatus having at least an XY stage, a detector and a beam irradiator; and (b) a test signal supply apparatus. , (C) Wiring logic value reading circuit, (D) XY stage control circuit, (V) Control computer, (F) At least circuit element identification data, circuit element connection data, circuit connection data and mask pattern Add at least circuit node identification data, wiring coordinate data, test pattern data to be added to the input terminals of the DUT chip, and test signals and test signals to the input terminals of the DUT chip created by the test data generation program based on the design data file containing the data. A design data file having the logic expected value of each node and the route information of the circuit when At least and a program, under the control of the control computer and the test program, the
The XY stage is moved by the XY stage control circuit based on the node identification data, the wiring coordinate data and the route information in the design data file, and the test pattern data to be added to the input terminal of the DUT chip is supplied with the test signal. It is supplied to the DUT to be tested through the device, and the electron beam or the laser beam is applied to the defined position of the node to be tested of the circuit on the DUT, and the signal of the node to be tested is detected by the detector and detected. The signal thus read is read by the wiring logical value reading circuit to obtain the wiring theoretical value of the node, and the defective portion is detected by comparing the logical expected value with the wiring logical value.

[Work]

The configuration of this device described in (a) to (g) above makes it possible to automatically and efficiently detect a failure location in the DUT.

〔Example〕

FIG. 1 is a diagram showing an embodiment of the test apparatus of the present invention. Through the test signal supply device 11, the wiring logical value reading circuit 12, and the XY stage control circuit 14, an electron beam test device (EBT: E-Bea
m Tester) 20 is connected to the control computer 1.
The XY stage control circuit 14 controls a motor 25 that controls the movement of the XY stage 22. The wiring logical value reading circuit 12 is connected to the secondary electron detector 24 and the scanning circuit 13 of the electron beam 21,
Based on a command from the control computer 1, the scanning of the electron beam 21 is started, and the EBT2 is set at a preset timing.
The image signal of 0 is sampled and the value is transferred to the control computer 1. The test signal supply device 11 sends a test signal to the IC socket 23 based on a command from the control computer 1.
Supply to DUT10 via. The test signal supply device 11 may be an ordinary IC tester as long as it can be controlled by the control computer 1. The control computer 1 has a terminal 2, an internal storage device 3, an external storage device 4, and is connected to an integrated circuit design support (CAD) system 8 having a design database 9. A test program 6 describing a test procedure is stored in the internal storage device 3, and a design data file 7 is stored in the external storage device 4. The design data file 7 consists of wiring coordinates on the DUT 10, expected logic values of each wiring at each timing of the test pattern, route information from each input terminal to each output terminal, etc., and is generated from the data in the design database 9. It

The route information file is composed of the following data.

(I) All signal propagation paths from each input to each output of the circuit under test (71, 72, etc. in FIG. 2) ... This is a path number for distinguishing the paths and a series of nodes indicating the paths. Each chain consists of 51-52-53-54 ... 60 in the case of FIG.

(Ii) Node names on each path (54, 57, 58, etc. in FIG. 2) The test program 6 of this device uses the following procedure for the entire circuit under test or a branch node in the circuit block in question. The logical check is performed to identify the location of the failure. That is, in the circuit under test, the signal propagation path connected to the output terminal where a defect is detected and the branch node on that path are sequentially called from the path information file, and the XY stage is moved based on the wiring coordinates corresponding to each branch node. Move and supply the test signal to the circuit under test in order from the test signal supply circuit, measure the logical value with the logical value reading circuit at the specified timing, and compare this with the expected logical value in the expected logical value file. Normal / defective is determined by the above, and the result is output.

Next, the branch node closest to the input side is selected from the defective branch nodes on all paths (nodes in which the measured logic value and the expected logic value do not match and there is a possibility of a failure). In the case of FIG. 2, node 57 is selected. Therefore, next, a logical check is performed between the branch nodes adjacent to the node 57, in this case, between (node 54, node 57) and between (node 63, node 57) in the same procedure. The resulting logic-mismatch node closest to the input side, in this case node 55, is the location of the failure. The procedure of the above processing performed by the test program 6 is shown in the flow chart of FIG.

Next, a specific procedure for measuring and comparing logical values will be described. The scanning circuit 13 operates for each test pattern and raster-scans the electron beam 21 over the entire observation area. The wiring logical value reading circuit 12 binarizes the potential contrast signal detected by the secondary electron detector 24 in synchronization with it under a certain threshold value and determines the logical value (0 or 1) of each sample point. Ask. These measured logic values are transferred to the control computer 1 and form a "measured logic map". The measurement logic map is a map showing the distribution of wiring figures having a logic value of 0. Depending on the number of sample points, an A / D converter is placed instead of the binarization circuit, the analog potential contrast signal is digitized and transferred to the control computer 1, where the "binarization program" is used. It may be valued. However, it is faster and more efficient to use the binarization circuit.

When using a high-precision XY stage with submicron positioning accuracy, if the coordinate system of the design wiring data and the coordinate system of the DUT chip are matched in advance using the coordinates of several locations around the DUT chip, the wiring logic The value is easy to measure. That is, if the coordinates of the wiring to be measured are read from the design data and the logical value of the corresponding position on the measurement logical map is read, that becomes the logical value of the desired wiring.

When the XY stage has a positioning error of ± several μm or more, it is necessary to perform image matching between the measurement logic map and the design wiring map of the corresponding area. This is a method already devised by the inventors (Japanese Patent Application No. 60-39897), and is a method of calculating the shift amount of both from the parallel movement amount required for superposition. If the shift amount between the measurement logic map and the design wiring map is known, the logic value of the wiring can be obtained by the same method as above also in this case.

Even if a laser beam tester (LBT: Laser Beam Tester) is used instead of the electron beam tester, the operating state inside the LSI can be measured without contact. For LBT, (a)
Type that scans the laser beam two-dimensionally (b)
There are two types: a type that moves the XY stage while the laser beam is fixed. When using LBT instead of EBT,
The configuration may be almost the same as that shown in the figure. In the case of LBT, the XY stage is placed in the atmosphere, so unlike the case of EBT, a highly accurate XY stage can be manufactured at a lower cost. Therefore, an XY stage with μm accuracy may be premised.

The method of detecting a logical value is the same in both types (a) and (b). That is, when a reverse-biased pn junction is irradiated with a laser beam, the photo-induced current changes according to the logic state, and the change appears in the power supply current supplied to the DUT. There is. Therefore, from the design data file, the pn junction of the transistor connected to the node under measurement (in the case of a COMS device, the drain junction of the p-ch or n-ch portion or the well boundary for forming the p-channel transistor) end The coordinates of the part are read out, and the XY stage is moved so that it becomes the irradiation point of the laser beam. If the laser beam is chopped in synchronization with the test pattern, the logic value corresponding to each test pattern can be taken into the control computer 1 through the signal detection circuit 16. Test program is third
It can be exactly the same as the one shown.

Next, a method of detecting a failure point will be described. Since it is inefficient to detect a failure point only with a non-contact test apparatus such as the test apparatus of the present invention, a normal IC tester is used to determine which test pattern and which output terminal has a failure. Make sure. Based on this information, the failure location is specified using a non-contact test device. Since LSI is generally a sequential circuit,
The simplest method to find the failure point is to test all the nodes in order from the output terminal to the input terminal, but this is inefficient, so the method of testing the nodes in a scattered manner is efficient. Target. For example, in a circuit having the number of logic stages D as shown in FIG. 2 (an average value of the number of gates passing through when considering various paths from the input pin 1 to the output pin 0), at the time t = T, the output terminal 0 Suppose that a fail has been detected. In this case, the logical state of a node per logical stage number D / 2 (one guideline that does not have to be exact), for example, the node 54, is checked from t = 1 to T. If it is a path at node 54, then n = 3D / 4
A node 57 around the node 57, and a node 63 around n = D / 2 if this is a failure are sequentially checked by a dichotomy. Finally, if the node 65 is a path and the node 56 and the node 55 are fail, the failure point is identified as the node 55. In this way, without measuring the logical values of all nodes,
The failure location can be found efficiently. Not only can the spatial dichotomy be used, but the dichotomy can also be taken temporally. When checking the logical value of a node, first check at t = T / 2, and if there is a failure, then t = T /
If not 4, t = 3T / 4 and so on.

If this device is combined with a "route extraction program", further automation can be promoted. This program extracts all the paths from the input terminal 1 to the output terminal 0 from the circuit description data in the design database 9, and the external storage device 4
It is a program stored in the above design data file.

One path connected to the output terminal 0 extracted by the program is shown by 71 in FIG. When a fail is detected at the output terminal 0, the logical value is checked at the node 54 at the center of the path. If node 54 is a path, then node
The node 57 in the middle of 54 and 0, and if this is a failure, next the node in the middle of the nodes 54 and 57, and so on. In this way, if you trace the failure on a path-by-path basis,
The location of the failure can be found extremely efficiently.

〔The invention's effect〕

As described above, the present invention provides a failure diagnosis technique capable of automatically detecting a failure location in the field of failure diagnosis of an integrated circuit, which has been almost impossible with the increase of the scale of the integrated circuit. However, the impact on the semiconductor industry is extremely large.

[Brief description of drawings]

FIG. 1 shows an embodiment of an integrated circuit test apparatus of the present invention, FIG. 2 shows a circuit under test of a device under test and its path, and FIG. 3 shows a test procedure of a test program. It is a figure. 1 ... Control computer, 2 ... Terminal, 3 ... Internal storage device, 4 ... External storage device, 5 ... Output device, 6 ... Test program, 7 ... Design data file, 8 ... Integrated circuit design Support (CAD) system, 9 ... Design database, 10 ... Device under test (DUT), 11 ... Test signal supply device, 12 ... Wiring logic value reading circuit, 13 ... Scanning circuit, 14 ... XY stage Control circuit, 15 ... Interface path, 16 ... Signal detection circuit, 20 ... Electron beam tester, 21 ... Electron beam, 22 ... XY stage, 23 ... IC socket, 24 ... Secondary electron detector , 25 …… Motor, 51 to 69
...... Node number

Claims (1)

[Claims] 1. An electron beam or laser beam testing device having at least an XY stage, a detector and a beam irradiator, (b) a test signal supplying device, (c) a wiring logical value reading circuit, D) XY stage control circuit, (e) Control computer, (f) Test data generation based on design data file containing at least circuit element identification data, circuit element connection data, circuit connection data and mask pattern data At least the circuit node identification data created by the program, the wiring coordinate data, the device under test (DU
T) Design data file having test pattern data applied to the input terminal of the chip, logical expected value of each node when the test signal is applied to the input terminal of the DUT chip, and circuit route information, and (g) test program And at least under the control of the control computer and the test program,
The XY stage is moved by the XY stage control circuit based on the node identification data, the wiring coordinate data and the route information in the design data file, and the test pattern data to be added to the input terminal of the DUT chip is supplied with the test signal. It is supplied to the DUT to be tested through the device, and the electron beam or the laser beam is applied to the defined position of the node to be tested of the circuit on the DUT, and the signal of the node to be tested is detected by the detector and detected. An integrated circuit test characterized in that a defective portion is detected by reading the generated signal by the wiring logical value reading circuit to obtain a wiring logical value of the node and comparing the logical expected value with the wiring logical value. apparatus.