JPH0789621B2 - Encoder - Google Patents

Description

The present invention relates to an encoding device that encodes image data of a plurality of color components.

[Prior Art] In a redundancy suppression coding method for a binary signal represented by a binary image signal, a signal sequence having a statistical bias larger than that of the original binary signal sequence is obtained. A major problem is to obtain a high compression ratio by simply encoding the signal sequence obtained in step (1). This is because, in a signal sequence having a large bias of statistical properties, a continuous length having the same logical value becomes longer, so that, for example, run-length encoding reduces so-called entropy and an extremely high compression ratio can be obtained.

However, image signals, especially encoding methods in the field of facsimile communication, for example, MH (Modified Eyed Huffman) encoding recommended by CCITT, MR (Modified Eyed READ) encoding, MMR (Modified Eyed, Modified Eyed READ) encoding, etc. It is well known that it is used not only for facsimiles but also for electronic files, etc., but these encoding methods focus on the fact that document information such as characters often has many "white" runs. Therefore, the transmission of such image signals is assumed. On the other hand, in addition to general document images, binary images of halftone images such as photographs are
A binarized pseudo-halftone image can be considered. However, since the pseudo halftone image produces gradation by the area gradation method, the printing dots (“black”) are dispersed due to its nature. That is, in the pseudo intermediate length image, the "run length", which is shorter than the original halftone image, increases, which is inconvenient for encoding.

This situation is shown in FIGS. 2 (a), (b) and FIG. 3 (a),
An explanation will be given using (b). The matrix in FIGS. 2 (a) and 2 (b) shows a threshold matrix, in particular, a dot concentration type dither matrix. The solid line in FIG. 3 (a) represents the threshold change in the first column in FIG. 2 (b). When a halftone image like the dotted line in the figure is input to such a threshold value, a pseudo halftone image signal having a discrete distribution as shown in FIG. 3B is obtained. When the “white” and “black” are thus separated, the compression ratio is lowered in the run-length coding, and it will not be necessary to explain. When MH coding or the like is performed on such a pseudo-halftone image, not only efficient suppression can not be expected but, on the contrary, the data amount may increase.

Conventionally, a bit interleave method has been known as a means for solving the above problem. In the bit interleaving method, pixels corresponding to threshold values that are close to each other are grouped and converted into multiple series bit patterns, or groups of pixels with the same threshold value are grouped and converted into multiple series bit patterns, and each bit pattern is converted. However, MH encoding was performed, but it was not possible to expect significant efficiency improvement.

On the other hand, the information amount of the color image is as large as 3 to 4 times that of the white / black image. Therefore, it is not the ratio of white / black images that requires a highly efficient redundancy suppression coding scheme to transmit or store this information. However, there is currently no effective redundancy suppression coding method for color image information, and a combination of the above-mentioned conventional methods for white / black images, that is, bit interleaving, MH coding, etc. are performed for each color image signal. The actual situation is that it was not possible to expect high efficiency.

[Object of the Invention] The present invention has been made in view of the above circumstances, and provides an encoding device capable of performing efficient encoding by appropriately extracting the characteristics of image data of a plurality of color components. The purpose is to provide.

[Means and Actions for Solving Problems] An encoding device of the present invention for solving the above problems includes an input unit for inputting image data of a plurality of color components, and an input unit for inputting the image data. A conversion unit that performs an array conversion process on the image data for each color component in block units of a predetermined number of pixels, and extracts change point information of the image data of the plurality of color components that are array-converted by the conversion unit. And an encoding unit that encodes the change point information of the plurality of color components respectively extracted by the extracting unit in parallel in line units, and the encoding unit is extracted by the extracting unit. It is characterized in that a "0" run block in which a plurality of color components are all "0" is encoded by a variable length encoding method from the change point information of each color component.

[Embodiment] In order to solve the above problems, as an example, the configuration of the embodiment shown in FIG. 1 in which the present invention is applied to suppress the redundancy of color binary image data C, M signals is as follows. For example, from among four color binary image signal sequences (7 _C , 7 _M , 7 _Y , 7 _K ) (C is cyan, M is magenta, Y is yellow and K is black), 0 → 1 detection unit 9 _CM that detects the change of each signal from “0” to “1”, etc., and “0” of signal sequence 7 _C , 7 _M
And run-length encoding for reduction "0" run coded portion 11 _CM collectively run, for the signal sequence 7 _C, and the determination unit 17 _C to determine that there is a predetermined pattern in the signal sequence 7 in _C, predetermined a flag generator 14 _C for generating a flag indicating the existence of a pattern,
A block encoding unit 15 _C to convert the blocks of one column in a predetermined code having a pattern other than the predetermined pattern,
Similarly for the signal sequence 7 _M , the determination unit 17 _C and the flag generation unit 1
4 _C , a block coding unit 15 _C, and a synthesizing unit 12 _CM that synthesizes the run-length code, the flag, and the code code. The same applies to the other colors (Y, K).

In addition, in the configuration of still another embodiment of the present invention, in addition to the above configuration, the signal sequence 7 _C is preprocessed by a preprocessing unit 1 _C including a bit interleave reconstruction unit 3 _C and a change point extraction unit 6 _C. Has a configuration. The same applies to the other signals (7 _M , 7 _Y , 7 _K ).

Under the above configuration, the 0 → 1 detection unit 9 _CM changes the binary signal sequence from 0 → 1
By capturing 1 change, the "0" run coding unit 11 _CM becomes 2
A "0" run block 16 _CM containing only a "0" signal is cut out across the column, and run length coding is performed on this "0" run block 16 _CM . On the other hand, when the 0 → 1 detection unit 9 _CM detects “1” in either the signal sequence 7 _C or 7 _M following the “0” run block 16 _CM , a predetermined length (for example, 4 bit length) is obtained. The possessed block is detected for each signal sequence 7 _C , 7 _M. Further, for the signal train 7 _C , when the discriminator 17 _C detects the presence of a predetermined pattern in the signal train 7 _C , the block of that one train is determined as the first
12 view (a), the flag generating unit flags # 1F as shown in (b) is set to "1", the discriminator 17 _C the presence of a pattern other than the predetermined pattern is detected, the flag generating part 14 _C the flags # 1F to "0", the block coding unit 15 _C is converts the pattern to a predetermined code code. Signal train 7 _M
For, a flag # 2F is provided and in the same manner as in the signal sequence 7 _C. Run length code and flag # thus obtained
1F, # 2F and the code are combined by a combiner 12 _CM to obtain a compressed signal string 13 _CM .

Further, according to another configuration shown in FIG. 1, if the color binary image data input to the encoding unit is, for example, the halftone image as shown in FIG. 3B, which is area-modulated by the dither method. , Such a color binary image signal (4 _C , 4 _M , 4 _Y , 4 _K ) is first subjected to a bit interleave reconstruction unit (3 _C , 1 _C , 1 _M , 1 _Y , 1 _K ) 3 _M, 3 _Y, 3 _K) to through, the white or black bias large binary signal sequence _{(5 C, 5 M, 5} Y, 5 K) is obtained. The reason is that the dither matrix is 4 as shown in FIG. 2 (b).
If it is × 4, the image data after dither processing includes the periodicity as shown in FIG. 3 (b), so that the binary signal sequence (5 _C , 5 _M , 5 _Y , 5 _K ) is unevenly distributed in white or black, and the white run length and the black run length become long.

Further, the change point extraction unit (6 _C , 6 _M , 6 _Y , 6 _K ) performs binarization by change point extraction, for example, the logical value change point of the signal sequence (5 _C , 5 _M , 5 _Y , 5 _K ). Is set to “1” and other unchanged points are set to “0” 2
When the value is converted, the logical value "1" becomes only the above change point. Then, the new binary signal sequence (7 _C , 7 _M , 7 _Y , 7 _K ) has “0”.
The run length of the run becomes longer, and the "0" run coding unit 11 _CM , 1
1 _YK encoding becomes efficient. In addition, the signal train (7 _C , 7 _M , 7
_Y , 7 _K ) has a specific bit pattern, such as "0000", "10
Many "00", "1100", etc. are generated. For example, if a 1-bit flag # 1F or # 2F is provided and the most frequent specific pattern is detected, the flag is detected. Is set to 1. If the number of bits of the flag is increased, even if there are many specific patterns, it can be compressed efficiently by flagging.

Hereinafter, embodiments according to the present invention will be described in more detail with reference to the accompanying drawings. In the embodiment, as described above, the pretreatment unit (1 _C , 1
_M , 1 _Y , 1 _K ) and an encoding unit (2 _CM , 2 _YK ) and processes a binary color signal C, M, Y, K to obtain a compressed image signal sequence 13 You get _CM , 13 _YK . First, the pre-processing unit (1 _C , 1 _M ) applies pre-processing to the color image signal (4 _C , 4 _M ), and the coding unit 2 _CM specifies the pre-processed signal sequence (7 _C , 7 _M ). Encoding is performed, and the synthesizing unit 12 _CM further causes one signal sequence 13
Convert to _CM . Similar processing is applied to Y and K of color signals. As will be described below sequentially with reference to the drawings, as shown in FIG. 1, the combination of the C signal and the M signal is equivalent to the combination of the Y signal and the K signal.
Therefore, a description will be given using a combination of the C signal and the M signal. or,
Since each constituent element of the embodiment shown in FIG. 1 has many common parts, in order to prevent the description from being duplicated, the accompanying drawings described below show a circuit example or the like for each one or two colors.

Preprocessing section, looking at the signal C, a bit interleaving reconstruction unit 3 _C, consisting change point extraction unit 6 _C. Also encoding unit
2 _CM has a different internal structure due to the difference in encoding method described later (Fig. 10 (a) and Fig. 11). First, let us explain the preprocessing unit 1 _C.

<Bit Interleave Reconstruction Unit> A bit interleave method will be described with reference to FIGS. 4A and 4B, and FIGS. 5A to 5C and 6.
Figure 4 (a) is, for example, FIG. 2 (a) or (b) of the dither Matrigel try the binarized C signal 4 _C der connexion, 40 pixels in the main scanning direction, 4 pixels in the sub-scanning direction Shows the size of minutes. The numbers given in the drawing are numbers of pixels in the main scanning direction and line numbers in the sub-scanning direction for convenience. This C signal 4 _C has a periodicity of about 4 bit periods. As described above, such a taser image is excellent for expressing a halftone, but it is clear from the figure that the run length is shortened. When 4-bit interleaving is performed on this C signal 4 _C , 1 in FIG.
The pixel array of 2,3,4, ... is 1,5,9,13,17, as shown in FIG.
It can be seen that the array becomes, and the "white" and "black" run lengths are increasing. 4 bits are used because the dither matrix used for the threshold processing is 4 bits, but the bit interleaving was performed with the same length as the dither matrix. In addition to such determination of the bit interleave length, it can be set to an integer multiple of the size of the matrix or a size of an integer, or at a cycle corresponding to the threshold value having an approximate value in the threshold matrix. There is also a method of grouping.

A circuit for performing such bit interleaving is shown in FIG. The bit interleave reconstruction unit 3 _C of FIG.
Two line memories 40, 41 are used for the rearrangement of the signal 4 _C. Two of them are used in order to simultaneously perform the input of the C signal 4 _C , the rearrangement operation, and the operation of reading out the rearranged signal train 5 _C. That is, when inputting (writing) to one line memory, the other line memory is used for output (reading). To prevent one line memory from being used for writing and reading at the same time, a write address counter 25, a read address counter 26, and a selector that distributes the outputs of these counters 25, 26 to each line memory 40, 41. 27, 28, 29, 30, 31, 32 and a line memory control unit 42 for performing exclusive control. Line memory controller 42
Is the second line memory write signal 36 or the first line memory write signal 37 in synchronization with the BD signal 38 generated for each line.
Are alternately set to "1". Further, the selectors 27, 28 and 31 are arranged to output the second line memory write signal 36 or the first line memory write signal.
A selector that selects an output according to the logical value of 37, while selectors 29, 30, and 32 similarly select an input according to the logical value of the second line memory write signal 36 or the first line memory write signal 37. To do. This way,
When the first line memory write signal 37 is “1”, the second line memory write signal 36 is “0”, the selector 27 outputs “0”, the selector 29 inputs “0”, and the selector 31 outputs The C signal 4 _C is written to the first line memory 40 to select the output “0”, while the output of the read address counter 26 is input to the second line memory 41 by the selector 28 and the selector 30, and the selector 32 is set to the second line memory 41. Select the line memory 41. Thus, simultaneous writing and reading can be performed, which contributes to speeding up.

FIG. 5 shows an address generation method of each address counter 25, 26. The capacity of the line memory is, for example, 000 to FFF as shown in FIG. The write address counter 25 may be sequentially incremented from 000 to FFF in ascending order as shown in FIG. 5 (b). Also, read address Taunta 26
Is as shown in FIG. 5 (c). Such an address generation circuit of the read counter 26 includes, for example, the same counter as the write address counter 25 and "1" to
It can be easily configured by using a counter having an output of "4" and an adder. The BD signal 38 of this embodiment uses a beam detect signal when the redundancy suppression coding method is applied to, for example, a laser beam printer or the like, and a horizontal synchronization signal when applied to a facsimile or the like.

The driving clocks of the address counters 25 and 26 and the line memories 40 and 41 are the synchronous clocks 35 _CM . The synchronous clock 35 _CM is intended to be generated by the encoding unit 2 _CM, the encoding unit 2 _CM
At the time of encoding in, when a signal string has a certain pattern, it is necessary to forcibly insert a predetermined code, and in that case, the bit interleaved reconstruction is performed until the composing unit 10 finishes sending the forced insertion code. It is used to stop the operation of part 3 _C (details will be described later).

The bit interleave reconstructing unit as described above performs bit interleaving for each color of the color signal. By the way, as you can see in Figure 1, C signal 4 _C and M signal 4 _M
And are simultaneously encoded by the encoding unit 2 _CM . Also, as will be described later, the "0" run coding unit 11 _CM collectively performs the run length coding on the C signal and the M signal. Further, the coding of the block including "1" is performed for each predetermined length. That is, the bit interleaving preprocessing of the C signal and the Y signal is synchronized, and therefore, of the constituent elements shown in FIG. 6, all but the first line memory 40 and the second line memory 41 can be shared. Contributes to miniaturization of the circuit. The same applies to the combination of the signal Y and the signal K.

<Extraction of Change Point> FIG. 7B shows an example of a circuit for extracting the change point, and FIG. 7A shows the result. Change point extraction unit in FIG. 7 (b)
An example of 6 _C is a case where a change point between pixels adjacent to one pixel in the main scanning direction of the signal C is extracted. A flip-flop 20 is used to detect one adjacent pixel, and an EX-OR gate (exclusive OR gate) 21 is used to detect a change point. Binary signal sequence with 4-bit interleaving
For 5 _C , EX-OR is performed with the pixel immediately before that on the same scan line as the pixel of interest. That is, if each pixel of the binary signal sequence 5 _C is made to correspond to the threshold value D _ij in FIG. 2A, the output D of the EX-OR gate 21
_xij 7 _C is D _xij = D _ij D _{i-1, j} . As can be seen by comparing FIG. 4 (b) and FIG. 7 (a), the “0” run (such a “0” run is also called a “white” run) is longer, and the run length is longer. It is obvious that it is suitable for encoding. Further, the bit-interleaved signal train 5 _C has long run lengths of “white” runs and “black” runs.
The characteristics appearing in the signal train 7 _C obtained by extracting the change points from the signal train 5 _C are as follows.

: There is a high probability that the logical value “1” is unevenly distributed surrounded by “0” before and after (ie, “1000” occurs after “0” run). This is because if the “white” run and the “black” run are long, the change point “1” occurs only at both ends thereof.

: On the other hand, the isolated “black” in a long “white” run and the isolated “white” in a long “black” run have a change point of “1100”.

From the above and above, it can be seen that "1000" and "1100" are frequently generated in the signal train 13. This is obvious by looking at FIG. 7 (a). The above facts have a lot to do with the encoding described below.

The preprocessing for redundancy suppression coding has been described above. Therefore, two embodiments of the encoding unit will be described next. In a sense, the pre-processing unit described above independently processes the signals of the respective colors. The encoding embodiment described below has two color signals (for example, the signal C and the signal M).
It is processed as one signal.

<First encoding embodiment of> FIG. 9 (a), in the signal sequence 7 _C extracted change point in FIG. 7 (a), shows a cut-out how block. In the figure,
(C1, M1) represents cyan on the first line and magenta on the first line, and (C2, M2) represents cyan on the second line and magenta on the second line. Also, "0" is changed to "white" and "1" according to the convention in the figure.
Is referred to as “black”. This is because it is easy to display the number of digits. First, for cyan (signal C) and magenta (signal M) on the first line, two series signals that include only “0” at the same time are cut out as white (“0”) runs. For example, "white 34" on the first line means that 34 white runs continue. For such a white (“0”) run, for example
Performs compression by MH encoding.

On the other hand, if even one "1" appears in any column, a block of 4 rows and 2 columns having a length of 4 bits is cut out from that. Such a block always contains one or more "1" s somewhere, but it is possible that one column contains "0" s. When the pre-processing as described above is performed, the number of "0" runs increases for each color as a whole. However, when cutting out a block that collects all the colors as described above, one column has "0000". Despite that, many items are included in non-blocks. this is,
This is because, in the same pixel, the stochastic processes of the C signal and the M signal are independent, so that the occurrence of "0" and "1" between the colors is random. The fact that there are many "0000" patterns suggests the possibility of further compression. This will be described in another embodiment.

The patterns that can be generated in the block thus obtained are combinations of 16 types of patterns shown in FIG.
For convenience sake, symbol names B _{0 to} B ₁₅ are given to such 16 types of patterns and shown in FIG. 9 (a). For example, the first block of the second line, and (B _8, B ₉₎ expressed. By the way, the second line in FIG. 9 (a) starts from a block that is not a "0" run. In such a case, one "white 0" (MH code "00" is forced before the non-zero block.
110101 ") is inserted, and the same applies when non-zero blocks are consecutive, so that" 0 "runs and blocks are always generated alternately.

By the way, as described above, a lot of "1000" and "1100" are generated in the block due to the preprocessing. Further, when "1" occurs in one of the colors, it becomes a part of the block, and therefore "0000" is also large. Therefore, if attention is paid to such a large number of generated patterns and predetermined coding is performed to make the bit length shorter than the pattern length, the compression rate by coding is improved. Now, in the above example, "0000", "1000" and "1"
Three types of patterns of 100 "occur frequently. Fig. 8 (a)
In the embodiment, the 2-bit code “00” is set to B ₀ = “0000”,
"01" is that the B ₃ = assigned to "1100". In this way compression is achieved. Further, all the codes in FIG. 8 (a) are unique to each other, and are a combination that does not cause confusion. Compressed code “10” is B ₀ , B ₃
Not adopted because it cannot be distinguished from other patterns. In this way, the patterns "0000" and "1"
100 "is compressed to 2 bits, while" 0000 "and" 110 "
For an image in which many patterns other than 0 "and" 1000 "occur with the same probability, the compression code is set to 3 bits. Then," 000 "," 001 "," 010 "," 011 " Of 4
Different types of compressed code are possible. The compression ratio is worse in the individual compression than in the 2-bit example, but the overall compression ratio is further improved. FIG. 9B is a diagram showing a compression pattern of each signal in accordance with the above rules. MH in Fig. 9 (b)
Represents MH encoding. It can be seen from FIG. 9 (b) that the compression ratio is much higher than that of simple MH coding.

FIG. 10 (a) is an example of a circuit for such encoding. In the figure, RL (run length) counter 51, selector 52,
The "white" MH encoding ROM 53 or the like encodes the "0"("white") run and latches the code code in the latch 54. Also detection circuit 50
As shown in the detailed diagram in Fig. 10 (b),
Change of 5 _C , 5 _M (“0” → “0”, “0” → “1”, “1” → “0”,
"1" → "1") is detected. The RL counter 51 is a counter that uses CLK as a driving clock. When "1" is input to its EN (energization) terminal, counting is enabled, and it is cleared when "1" is input to the CL (clear) terminal. Therefore, the RL counter 51
Keeps counting while both signal sequences 5 _C and 5 _M are “0”, and inputs the MH code code corresponding to the count value to the latch 54. If either the signal sequence 5 _C or 5 _M changes from “0” to “1”, the sign code of the count value at that time is signal 70.
Is latched by the latch 54 via the, and the counter 51 is cleared at the same time.

On the other hand, the 4-bit shift register 61 holds the signal train 5 _C and the 4-bit shift register 62 holds the signal 5 _M for a 4-bit length. The block coding ROMs 63 and 64 respectively code the outputs of the 4-bit shift registers 61 and 62 according to the rules shown in FIG. On the other hand, in the 4-bit counter 55, the detection circuit 50 detects the change of the signal train 5 _C , 5 _M from “0” to “1”, and activates the signal 71 4 bit time after the change. At this timing, the outputs of the block coding ROMs 63 and 64 are latched in the latches 65 and 66, respectively. The synthesizer 67 is for synthesizing the encoded codes and storing them in the shift register 63. Since the MH code has a variable length, such a combiner is required. The shift register 63 performs parallel-serial conversion.

The AND gate 60 is for inserting the MH code corresponding to the white "0" as described above when the block starts from the beginning of the line. The AND gate 59 is connected to one block, and when a "1" signal is immediately input without inputting a "0" run (either the signal sequence 5 _C or 5 _M is "1", and the signal is 72 is for inserting the MH code corresponding to white “0” in “1”). The white "0" insertion part 56 is for inserting this one "white". When either AND gate 59, 60 is opened,
Output “0” to the selector 52. Thus, white MH encoded RO
M53 outputs the MH code corresponding to “0” = “00110101”,
White “0” is inserted forcibly. The clock control 57 is a 35 _CM synchronous clock of the bit interleave section described above.
However, the generation of the synchronous clock 35 _CM is stopped until "00110101" is output from the shift register 68 at the timing of the forced insertion. This is for synchronizing the input to the line memory 40 or 41 and the output from the shift register 68. In this way, compressed data 12 _CM having a high compression rate can be obtained from the C signal 4 _C and the M signal 4 _{M of} FIG. 4 (a).

Although the MH coding method is used in the circuit of FIG. 10 (a), for example, Wyle code or the like may be used as the one-dimensional coding.
Further, it is obvious that the present invention can be easily applied to not only one-dimensional encoding but also two-dimensional encoding processing such as MR symbol and MMR symbol. Basically, the coding method is not chosen. Furthermore,
It is also applicable to R, G, B for color images.

Next, another embodiment of the encoding process will be described.

<Second Encoding Example> In the above-described example, "0000" generated in large numbers in a block is compressed into a code "00". In this embodiment, this "0000" is compressed more efficiently. For that purpose, the cutting out of the block is performed as shown in FIG. 9 (a) as in the above-mentioned embodiment. And
Consider a block of 4 rows and 2 columns containing "1" as two blocks of 4 rows and 1 column, and if there is a 4-bit "0000" (this is called a zero pattern for convenience), execute it as described above. As in the example, instead of encoding as "00", a flag indicating that "0000" is compressed is provided and the value of that flag is set to "0".
To If even one "1" exists in one column, the flag corresponding to the block of 4 rows and 1 column (such a block of 1 column is called a non-zero pattern for convenience) is set to "1". Such a flag is provided for each column. The code corresponding to the non-zero pattern is provided as shown in FIG. 8 (b). First
Figure 12 (a) shows the format. The code code for the C signal is # 1 code, the code code for the M signal is # 2 code, and the flags corresponding to these code codes are # 1F and # 2F, respectively.

Any combination of blocks of 4 rows and 2 columns is always a combination of a zero pattern and a non-zero pattern, so that any one of the patterns shown in FIG. 12 (b) is obtained. When the data compression is performed in this way, the zero pattern does not appear as a code, so that there is a possibility that a synchronization shift may occur during decoding. However, there is always a flag in the data to be reconstituted, the length of which is always 4 bits, and the length of the # 1 code to # 2 code following the flag depends on the logical value of the flag (that is, how many bits are in a block). You can see if there was a zero pattern). Also as can be seen from FIG. 8 (b), reference numeral code corresponding to the B ₁ .about.B ₁₅ are all unique. Therefore, even if the zero pattern is converted to have no code, the synchronization will not be lost during decoding.

When the block cutouts shown in FIGS. 9 (a) and 9 (b) are compressed according to the compression of this embodiment, the result is as shown in FIG. 14 (c). For example, B ₀ / B ₁ in the figure has a flag portion of “01”, # 1
There is no code, and the # 2 code is "00".

Now, FIG. 11 shows an example of a circuit for performing such encoding. That is, the block coding ROM 6 has the same basic configuration as that of the first embodiment (FIGS. 10A and 10B).
The flag output is added to a part of the output of 3,64 as shown in FIG. Then, for example, if a zero pattern is input to this block coding ROM, the length is "1".
(Because there is only 1 bit of the flag), the flag is "0",
The code is "0". The ROM length output is input to the combiner 67 and becomes information when combining. That is, the synthesizer 67
Will only output "0000" as "1". Thus
More effective compression is possible for an image signal containing many “0000”.

In the above embodiment, the block length is set to 4 bits, but there is no limitation to this and it is determined according to the circuit scale and the type of original image data. By the way, if it is set to a length of 8 bits, the efficiency will be slightly improved. Furthermore, MH for “0” run
The coding efficiency is further improved by changing the coding ROM table to some extent. Also, the coding method is not limited to the MH coding method, and can be applied to other one-dimensional coding methods.

As for the binary color signals C, M, Y, K, as is well known, the one stored in a memory (not shown) is read out, or the image is read in real time and binarized. Good.

<Effects of the Embodiment> The effects of the various embodiments described above can be summarized as follows.

: Since bit interleave processing is applied to binary color image data, the run length is restored and lengthened even if the white run and the black run are scattered. This is particularly effective for color image data that has undergone halftone processing using a threshold matrix.

: Since the change point extraction processing is further performed on the signal sequence that has been subjected to bit interleaving processing, the run tone of "1" is short,
The run length of "0" becomes long, so that high compression of the encoding process can be expected. As a result, the pseudo halftone image can be compressed with high efficiency while using the encoding algorithm for the document image as it is.

In particular, if existing coding such as MH coding is performed, a redundancy suppression method with a high compression rate can be obtained with a slight modification to the conventional circuit.

: A large number of signal trains (blocks) having a predetermined pattern are generated by the change point extraction. Therefore, the pattern in this block is encoded into a code having a short bit length for each color and then combined. Also, for "0" runs, it is the same as before.
Encoding is performed by applying one-dimensional encoding such as MH encoding. That is, depending on the type of original image data, "0000", "1000" or "1100" occurs frequently in the signal sequence from which the change points are extracted, so that the compression rate is increased by encoding such blocks with short bits. In addition to being able to do so, it is possible to unify signals from two or more columns.

: Furthermore, by replacing the zero pattern of "0000" with a 1-bit flag, a higher degree of compression becomes possible.

[Effects of the Invention] As described above, according to the present invention, it is possible to appropriately perform the array conversion and the change point extraction for each color component, and the extracted change point information is paralleled in line units. By encoding the "0" run block in which all of the color components are "0" when encoding with the variable length encoding method,
It is possible to efficiently encode image data of a plurality of color components.

[Brief description of drawings]

FIG. 1 is a principle configuration diagram of an embodiment according to the present invention, and FIGS. 2 (a) and 2 (b) are Diesama matrix diagrams used in the embodiment according to the present invention and a conventional example, and FIG. ) And (b) are diagrams for explaining how the degree of bit dispersion is increased by the halftone process in the conventional example, FIGS. 4 (a) and 4 (b) are diagrams for explaining the operation of the bit interleaving process, and FIG. a) to (c) are diagrams for explaining the principle of bit interleave address generation, FIG. 6 is a circuit diagram of the bit interleave reconstruction unit, and FIGS. 7 (a) and 7 (b) are the operation of the change point extraction unit and 8A and 8B are views for explaining a circuit configuration, FIGS. 8A and 8B are views for explaining an example of a code code of an embodiment of the present invention, and FIGS. 9A and 9B are respectively implementations. FIGS. 10 (a) and 10 (b) for explaining the block cutout method and the code array after encoding in the example. And a circuit diagram of an embodiment for realizing the operation shown in FIGS. 9A and 9B, FIG. 11 is a configuration diagram of a ROM used for encoding in another embodiment, and FIG. ) To (c) are diagrams for explaining the principle of the encoding method of another embodiment, in which 1 _C , 1 _M , 1 _Y , 1 _K ... preprocessing unit, 2 _CM , 2 _YK ... encoding Part, 3 _C , 3
_M , 3 _Y , 3 _K ... Bit interleaved reconstruction unit, 4 _C , 4 _M , 4 _Y , 4 _K
...... Color binary image data, 5 _C , 5 _M , 5 _Y , 5 _K ...... Bit-interleaved signal sequence, 6 _C , 6 _M , 6 _Y , 6 _K ...... Change point extractor, 7 _C , 7 _M , 7 _Y , 7 _K ...... Change point extracted signal, 14 _C , 14 _M , 1
4 _Y , 14 _K …… Flag generator, 15 _C , 15 _Y , 15 _M , 15 _K …… Block encoder, 9 _CM , 9 _YK …… 0 → 1 detector, 11 _CM , 11 _YK ……
"0" Run coding unit, 12 _CM , 12 _YK …… Synthesis unit, 13 _CM , 13 _YK …
--- Redundancy suppressed binary signal, 16 _CM --- "0" run block, 17 _C , 17 _M , 17 _Y , 17 _K --- Discrimination unit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP 59-58972 (JP, A) JP 60-77576 (JP, A) JP 60-85856 (JP, A) JP 53- 108217 (JP, A) JP 62-82723 (JP, A) JP 62-118642 (JP, A) JP 62-98921 (JP, A) Actual development Sho 59-17669 (JP, U) JP-B-49-28762 (JP, B1) JP-B-54-13332 (JP, B2) JP-B-54-33886 (JP, B2) JP-B 57-31703 (JP, B2) JP-B 5-8621 (JP, B2)

Claims (1)

[Claims] 1. Input means for inputting image data of a plurality of color components, and conversion for performing array conversion processing on the image data input by the input means in block units of a predetermined number of pixels for each color component. Means, extraction means for extracting change point information of image data of a plurality of color components respectively array-converted by the converting means, and change point information of a plurality of color components respectively extracted by the extracting means in line units Coding means for coding in parallel, wherein the coding means is configured such that all the plurality of color components are “0” from the change point information of each color component extracted by the extraction means. An encoding device characterized in that a run block is encoded by a variable length encoding method.