JPH0792933A - Flat panel display - Google Patents

Abstract

(57) [Summary] [Object] To provide a flat panel display device capable of directly inputting CRT display data and a synchronization signal. [Composition] An interface section for generating a timing signal suitable for a flat panel used internally is provided, and a display for a CRT is displayed based on horizontal display start position setting information and vertical display position start information supplied from an external terminal. The timing signal is converted into a display timing signal for a flat panel. [Effect] According to the setting information, the CRT display data can be displayed so as to fit the flat panel.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flat panel display device, and more particularly to a technique effectively used for an interface portion of a display device using a liquid crystal display panel having a large display screen.

[0002]

2. Description of the Related Art A display control signal for a flat panel such as a liquid crystal display device is generated by a horizontal synchronizing signal for CRT, a vertical synchronizing signal and display data. However, since there is a blanking period between the CRT display data and the horizontal and vertical synchronizing signals, even if each signal is directly input to the flat panel, the display cannot be performed at the expected position. A circuit that inputs the horizontal display start signal that indicates where to start in the horizontal direction and the vertical display start signal that indicates where to start in the vertical direction in order to display at the expected position on the flat panel. is necessary.

Conventionally, from the time of designing a display system, it has been necessary to prepare a circuit in accordance with a flat panel so as to satisfy the relationship between data and a synchronizing signal. In addition, it is not possible to display the position on the flat panel as expected by only generating the vertical synchronization signal, and a circuit for generating the horizontal display start signal that indicates where to start in the horizontal direction is required. is there. When considering display on a flat panel, it is necessary to specify the horizontal data start position especially for generation of the drive clock, and it is necessary to create a circuit for specifying the horizontal data start position each time. was there. As a circuit that generates a timing signal for LC using a vertical counter,
There is No. 0.

[0004]

As described above, in order to display at an arbitrary position on the flat panel by the display data and the synchronization signal for the CRT, the synchronization signal is adjusted according to the flat panel used from the time of designing the display system. It is necessary to form a circuit that satisfies the relationship with. Therefore, the number of man-hours for designing and manufacturing the flat panel display device increases, and only a uniform display operation can be performed.
Therefore, the inventor of the present application has considered a timing generation circuit that can be displayed at an arbitrary position on the flat panel by the display data and the synchronization signal for the CRT by software.

An object of the present invention is to provide a flat panel display device capable of directly inputting CRT display data and sync signal. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0006]

The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows. That is, an interface unit for generating a timing signal suitable for a flat panel used internally is provided, and display timing for CRT is displayed based on horizontal display start position setting information and vertical display position start information supplied from an external terminal. Convert the signal to a display timing signal for a flat panel.

[0007]

According to the above-mentioned means, the CRT display data can be displayed so as to fit the flat panel according to the setting information.

[0008]

1 is a block diagram of an embodiment of a horizontal display timing generation circuit as an interface portion provided in a flat panel display device according to the present invention. Although not particularly limited, each circuit block in the figure is built in a semiconductor integrated circuit device forming a controller for a flat panel. This embodiment is directed to the case where the number of lines of the flat panel and the number of lines of the CRT match, and this timing generation circuit (circuit A) performs a conversion operation so that the horizontal display position is adapted to the flat panel. To do.

Dot clock DOT corresponding to display pixels
CK is supplied to the horizontal counter circuit 1 to perform counting operation. Reset terminal R of this horizontal counter circuit 1
Is supplied with a horizontal synchronizing signal HSYNC for CRT display. As a result, the horizontal counter circuit 1 performs the counting operation of the dot clock DOTCK with the generation timing of the horizontal synchronization signal HYNC as a base point.

The display start position information inputted from the external terminal is fetched into the register circuit 2. Register circuit 2
Is compared with the count output of the horizontal counter circuit 1 by the comparison circuit 3. The latch circuit 4 is set by the comparison match signal of the comparison circuit 3. The latch circuit 4 is reset by the horizontal synchronizing signal HSYNC for CRT display. That is, the latch circuit 4 outputs the horizontal synchronizing signal HS after the coincidence output of the comparison circuit 3 is formed.
Until YNC arrives, the horizontal display timing signal DTMG supplied to the flat panel is set to a high level which is effective.

If the number of dots in the register circuit 2 is N, the horizontal display timing signal DTMG of the flat panel is validated after the arrival of N dot clocks DOTCK after the horizontal synchronizing signal HSYNC is generated. . Therefore, on the flat panel, when the set value of the register circuit 2 is matched with the number of dot clocks in the horizontal blanking period, the display operation is started from the pixel at the left end. If the number of display data of the CRT is the same as the number of pixels in the horizontal direction of the flat panel, the above display setting is desirable.

Even if the number of display data of the CRT and the number of pixels in the horizontal direction of the flat panel are equal, if it is necessary to intentionally shift the display start position to the right by M pixels, the register circuit 2 has N + M. You can enter. If the number of pixels in the horizontal direction of the flat panel is larger than the number of CRT display data by K, and if the CRT display data is to be displayed in the left and right center portions of the screen, the above M
May be set as K / 2. As a result, in the flat panel, the display data of the CRT is written from the pixels on the left end and from the pixels of K / 2 and displayed on the left and right center portions.

FIG. 2 is a block diagram showing an embodiment of horizontal and vertical display timing generation circuits as an interface section provided in the flat panel display device according to the present invention. Although not particularly limited, each circuit block in the figure is built in a semiconductor integrated circuit device forming a controller for a flat panel. In this example,
By providing the circuit B in addition to the circuit A of FIG. 1, the conversion operation is performed so that the display position in the vertical direction also fits the flat panel.

Horizontal sync signal HSYNC for CRT display
Are supplied to the vertical counter circuit 5 to perform the counting operation. The vertical synchronizing signal VSYNC for CRT display is supplied to the reset terminal R of the vertical counter circuit 5. As a result, the vertical counter circuit 5 performs the counting operation of the horizontal synchronizing signal HSYNC, with the generation timing of the vertical synchronizing signal VSYNC as a base point.

The display start position information input from the external terminal is fetched into the register circuit 6. Register circuit 6
Of the vertical counter circuit 5 and the count output of the vertical counter circuit 5 are compared by the comparison circuit 7. The latch circuit 8 is set by the comparison match signal of the comparison circuit 7. The latch circuit 8 is reset by the vertical synchronization signal VSYNC for CRT display. That is, the latch circuit 8 outputs the vertical synchronizing signal VS after the coincidence output of the comparison circuit 7 is formed.
Until YNC arrives, the vertical display timing signal supplied to the flat panel is set to a high level which is valid.

The horizontal display timing signal generated by the same circuit A as in FIG. 1 and the vertical display timing signal are input to the logical product 9. This logical product 9 forms and outputs the display timing signal DTMG which is set to the effective level when both the input are the effective levels.

FIG. 3 is a block diagram of an embodiment of a timing generation circuit for forming a vertical sync signal for a flat panel. Horizontal sync signal HSYN for CRT display
C is supplied to the vertical counter circuit 10 and the counting operation is performed. The vertical synchronizing signal VSYNC for CRT display is supplied to the reset terminal R of the vertical counter circuit 10. As a result, the vertical counter circuit 10 performs the counting operation of the horizontal synchronizing signal HSYNC based on the generation timing of the vertical synchronizing signal VSYNC as in the vertical counter circuit 5 for the display timing signal.

The register circuit 11 fetches position information corresponding to a vertical sync signal for a flat panel, which is input from an external terminal. The output signal of the register circuit 11 and the count output of the vertical counter circuit 10 are compared by the comparison circuit 12. The comparison match signal of the comparison circuit 12 is output as the flat panel vertical synchronization signal VSFLAT.

FIG. 4 is a display screen diagram of a flat panel for explaining the operation of the timing generation circuit according to the present invention. 480 flat panels vertically
For a large flat panel with lines, there are 440 vertical periods of display data for CRT, of which vertical retrace periods of 20 lines each are allocated above and below,
It is assumed that the valid display data has 400 lines. In order to facilitate understanding, the number of data in the horizontal direction is the same as the number of CRT data and the number of pixels of a flat panel.

When the display data of the CRT having the above-described structure is directly supplied to the flat panel to perform the display operation, nothing is displayed as the vertical blanking period from line 1 to line 20, and line 21 to line 420 is displayed. Up to 4
The display data of the CRT is displayed in the shaded portion such as the 00 line. Then, the 20 lines from 421 to 440 are not displayed as the vertical blanking period. As a result, the CRT display data repeats the same display operation from one line again. On the contrary,
In the flat panel, since the vertical selection circuit is not reset, the 1st line and the 441th line are simultaneously selected. As a result, pixel data corresponding to 21 lines is input from the 461 lines of the flat panel. That is, the display data is displayed in a biased manner on the upper portion of the flat panel, and there is a problem that the upper 20 lines of the display screen are displayed on the lower side of the screen.

On the other hand, when the timing generation circuit of this embodiment is used, the timing generation circuit (circuit D) of FIG. 3 causes the vertical synchronization signal VS on line 421.
Move FLAT. Then, by the circuit C of FIG.
The display timing signal DTMG may be sequentially output to the effective data lines from the 421st line to the 440th line, the 1st line to the 20th line, and the 21st line to the 420th line. That is, in this embodiment, the display timing signal is generated in all the vertical periods (440 lines) assigned to the CRT.

When viewed from the flat panel side, the data (vertical retrace line period) of the 421st line inputted after the generation of the vertical synchronizing signal VFLAT is displayed as the first line. In other words, in the 40th line from the 1st line to the 40th line on the flat panel, CR
A vertical blanking period consisting of 421 to 420 lines of T display data and a total of 40 lines from the first line to 20 lines is allocated. During this period, since there is no valid data, the black level is displayed. And 41
The display data is displayed over 400 lines from line 440 to line 440.

After the display operation of the 440th line is completed, the vertical synchronizing signal VF is added to the next 441th line as described above.
Since the LAT is generated, the flat panel starts the display operation from one line. As described above, the vertical selection circuit
Since there is no reset function, the selecting operation for the 441th line is performed in parallel with the selecting operation for the first line. However, 441
The 40 lines from 480 to 480 correspond to the 40 lines of the vertical blanking period, so that nothing is displayed. That is, the display operation can be performed in the central portion like the display screen of (B), and a part of the display screen is not displayed on the lower side of the screen.

FIG. 5 is a block diagram of an embodiment of a liquid crystal display device to which the present invention is applied. The liquid crystal display panel is as large as 1024 × 796 and has a color of 51.
Multicolor display of two colors is enabled. Since one pixel requires three signal lines corresponding to RGB, the total number of signal lines is 3072.

The signal lines for the above 1024 pixels are vertically divided into odd-numbered ones and even-numbered ones, the signal line driving circuits DDV1 to DDV10 are provided on the upper side, and the signal line driving circuit DDV11 is provided on the lower side. ~ DDV20 is provided. One signal line drive circuit has the same structure as in the above embodiment.
The one having 60 output terminals is used. 30 up and down
Since 72/2 = 1536 signal lines are provided and the number of outputs of one signal line drive circuit is 160, 9440 signal lines drive circuits can handle 1440 lines, and the remaining 96 lines are 1 line. One signal line drive circuit will be in charge.
The signal line drive circuit that handles these 96 lines is DDV1 and DD
It is arranged in the first-stage circuit like V11 and the mode setting is performed as follows.

By the above mode setting, the data corresponding to the first 96 lines are the signal line drive circuits DDV1 and DDV1.
2 of serial input clock pulse CL2
The capture is completed in 4 clocks and the low power consumption mode is immediately entered. Then, since the output signal EIO2 is set to the low level, the signal line drive circuits DDV2 and DDV12 of the next stage are set.
Each starts its operation and thereafter fetches 160 lines of data at 40 clocks. Similarly, when the input data is completely fetched by the signal line drive circuits DDV10 and DDV20 at the final stage, the clock pulse CL1
Occurs, the data in the latch (1) that has been captured is transferred to the latch (2), and the capture of the serial data corresponding to the next line is started.

The scanning line electrodes are the scanning line driving circuits CDV1 to CDV1.
It is driven by CDV4. This scanning line drive circuit CDV
1 to CDV4 each have 192 output terminals,
Upon receiving the line synchronization signal, the scanning lines to be selected are sequentially switched. Since there are 768 scanning lines as described above, the scanning line driving circuits CDV1 to CDV4 make one
Scan line signals for the screen can be formed.

The controller has an image memory for storing display data for at least one screen, and the host computer (microcomputer) CPU inputs the display data to the image memory. The controller is CR
The data in the image memory is sequentially read in synchronization with the scanning timing of T to generate serial data and control signals.
The display data and the synchronizing signal for the CRT display formed in this manner are processed by the timing generation circuit provided in the interface unit IF to form the flat panel TF.
It is converted into a timing signal corresponding to the screen configuration of the T color liquid crystal panel and input together with the display data.

In the above structure, if the controller is connected to the CRT display device, the display operation by the CRT can be performed. The liquid crystal display device provided with the timing generation circuit as the interface unit IF according to this embodiment can also input the display data and the synchronization signal formed by the same controller. That is,
According to this embodiment, a flat panel display device can be used in place of the CRT display device in the microcomputer designed on the assumption that the CRT display device is used. In that case, since the CRT display data can be displayed at a desired position on the flat panel by setting the display position from the external terminal, the flat panel display device can be made highly versatile.

The effects obtained from the above embodiment are as follows. That is, (1) An interface section for generating a timing signal suitable for a flat panel used inside is provided, and for a CRT based on horizontal display start position setting information and vertical display position start information supplied from an external terminal. By converting the display timing signal of 1 to the display timing signal for the flat panel, it is possible to obtain the effect that the flat panel display device that displays the CRT display data can be obtained.

(2) According to the above (1), in a microcomputer designed on the assumption that a CRT display device is used, it is possible to use a flat panel display device instead of the CRT display device. An effect that a flat panel display device having high property can be obtained is obtained.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention of the present application is not limited to the embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, the timing generation circuit may be configured by only the one that generates the horizontal display timing signal or only the one that generates the vertical display timing signal and the vertical synchronization signal according to the screen configuration of the flat panel display device. The display timing signal may be formed by a magnitude comparison circuit without the latch circuit. The register may have a serial input configuration to reduce the number of input terminals. The register may be configured such that information written using a non-volatile memory element or the like in which writing or writing and erasing operations are electrically performed is not lost by power shutdown. The flat panel display device can adopt various embodiments such as an STN liquid crystal display device or a plasma display device in addition to the TFT liquid crystal panel as described above. The present invention can be widely used as a flat display device.

[0033]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, an interface unit for generating a timing signal suitable for a flat panel used internally is provided, and display timing for CRT is displayed based on horizontal display start position setting information and vertical display position start information supplied from an external terminal. A flat panel display device that displays CRT display data can be obtained by converting the signal into a display timing signal for a flat panel.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a horizontal display timing generation circuit as an interface section provided in a flat panel display device according to the present invention.

FIG. 2 is a block diagram showing an embodiment of horizontal and vertical display timing generation circuits as an interface section provided in the flat panel display device according to the present invention.

FIG. 3 is a block diagram showing an embodiment of a timing generation circuit that forms a vertical synchronization signal for a flat panel.

FIG. 4 is a display screen diagram of a flat panel for explaining the operation of the timing generation circuit according to the present invention.

FIG. 5 is a block diagram showing an embodiment of a liquid crystal display device to which the present invention is applied.

[Explanation of symbols]

1 ... Horizontal counter circuit, 2 ... Register circuit, 3 ... Comparison circuit, 4 ... Latch circuit, 5 ... Vertical counter circuit, 6 ...
Register circuit, 7 ... Comparison circuit, 8 ... Latch circuit, 9 ... Logical product, 10 ... Vertical counter circuit, 11 ... Register circuit, 12 ... Comparison circuit, DDV1 to DDV20 ... Signal line drive circuit, CDV1 to CDV4 ... Scan line drive Circuit, CPU
… Host computer (microcomputer), IF
… Interface part.

Claims (5)

[Claims] 1. A horizontal counter that is reset by a horizontal sync signal for CRT display and counts a dot clock pulse, and horizontal display position information used for actual display of a flat panel is set by an input signal supplied from an external terminal. A horizontal register, a horizontal comparing circuit for comparing the output signals of the horizontal register and the horizontal counter, and a horizontal timing generating circuit for forming a horizontal display timing signal of the flat panel by the output signal of the comparing circuit and the horizontal synchronizing signal. A flat panel display device characterized by having an interface section comprising: 2. A first vertical counter reset by a vertical synchronizing signal for CRT display and counting a horizontal synchronizing signal, and a vertical display position used for actual display of a flat panel by an input signal supplied from an external terminal. A first vertical register in which information is set, a first vertical comparison circuit that compares the output signals of the first vertical register and the first vertical counter, an output signal of the vertical comparison circuit, and the vertical synchronization signal. And a vertical timing generating circuit for forming a vertical display timing signal of a flat panel, a display timing signal generating circuit for forming a display timing signal by the horizontal and vertical timing signals, and a horizontal synchronizing signal for resetting by a vertical synchronizing signal for CRT display. The second vertical counter that counts the synchronization signal and the input signal supplied from the external terminal The vertical synchronizing signal for the flat panel by comparing the output signals of the second vertical register and the second vertical counter with the second vertical register in which the position information designating the generation timing of the vertical synchronizing signal of the panel is set. A flat panel display device having an interface section including a second vertical comparison circuit to be formed. 3. A horizontal counter that is reset by a horizontal synchronizing signal for CRT display and counts a dot clock pulse, and horizontal display position information used for actual display of a flat panel is set by an input signal supplied from an external terminal. A horizontal register, a horizontal comparing circuit for comparing the output signals of the horizontal register and the horizontal counter, and a horizontal timing generating circuit for forming a horizontal display timing signal of the flat panel by the output signal of the comparing circuit and the horizontal synchronizing signal. And the first vertical counter that is reset by the vertical sync signal for CRT display and counts the horizontal sync signal, and the vertical display position information used for the actual display of the flat panel is set by the input signal supplied from the external terminal. A first vertical register, the first vertical register and the first vertical counter, A first vertical comparison circuit for comparing output signals of a flat panel, a vertical timing generation circuit for forming a vertical display timing signal of a flat panel by the output signal of the vertical comparison circuit and the vertical synchronization signal, and the horizontal and vertical timings. A flat panel by a display timing signal generating circuit which forms a display timing signal by a signal, a second vertical counter which is reset by a vertical synchronizing signal for CRT display and counts a horizontal synchronizing signal, and an input signal supplied from an external terminal A vertical synchronization signal for a flat panel is formed by comparing the output signals of the second vertical register and the second vertical counter with the second vertical register in which the storage information designating the generation timing of the vertical synchronization signal of And a second vertical comparison circuit that has an interface section. Topaneru display device. 4. The flat display position information according to claim 1 or 3, wherein the horizontal display position information is set based on a display position of the flat panel corresponding to a timing when the horizontal synchronizing signal is generated. Panel display device. 5. The interface according to claim 1, wherein the interface section is built in a semiconductor integrated circuit device which constitutes a display controller.
Alternatively, the flat panel display device according to claim 4.