JPH0793043A - Overcurrent limiting circuit - Google Patents

Abstract

PURPOSE:To clamp the voltage of an output FET, to stably limit an output overcurrent and hold the voltage by connecting a switching element which operates in response to the voltage between an output terminal and a power source and a temperature-independent constant voltage part in series and interposing them between the source and gate of an output field effect transistor. CONSTITUTION:The temperature-independent constant voltage part A is used as a substitute for a conventional temperature dependent diode group to clamp an output voltage, and then it is connected to a 2nd FET TB as a switching element in series and interposed between the gate and source of a 1st FET Ta to form an overcurrent limiting part. The 2nd FET Tb has its gate Gb connected to a power source terminal Vcc, its drain Db connected to the gate Ga of the 1st FET Ta for output through the temperature-independent constant voltage part A, and its source Sb connected to an output terminal Vo. Therefore, the temperature-independent constant voltage part A clamps the gate voltage of the output FET Ta, so an output current is limited and held at a constant value irrespectively of temperature.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an overcurrent limiting circuit for limiting an output overcurrent to protect an output field effect transistor.

[0002]

2. Description of the Related Art A MOSIC output circuit has a built-in overcurrent limiting circuit for limiting an output overcurrent to protect an output field effect transistor. An example thereof will be described below with reference to FIG. In the figure, (Vcc) is a power supply terminal, (Vo) is an output terminal, (Ta) is an output MOS type first field effect transistor (hereinafter referred to as a first FET), (Tb) is an overcurrent limiting switching element, For example, a MOS type second field effect transistor (hereinafter referred to as a second FET), (J
a) to (Jd) are a group of diodes for limiting overcurrent. The first FET (Ta) has a drain (Da) and a source (S).
a) is inserted between the power supply and output terminals (Vcc) (Vo), and the load (B) is connected to the output terminal (Vo). The second FET (Tb) has a gate (Gb) connected to a power supply terminal (Vc
c) connected to the drain (Db) of the first FET (Ta)
, And the source (Sb) is connected to the output terminal (Vo) through the diode groups (Ja) to (Jd). The diode group (Ja) to (Jd) is the second FET
(Tb) and the output terminal (Vo) are connected in series in the forward direction to form an overcurrent limiting section with the second FET (Tb).

In the above structure, when the gate voltage of the first FET (Ta) is raised above the power supply potential and applied, the first
The FET (Ta) becomes conductive and a current flows between the drain and the source. Therefore, when an excessive current flows through the first FET (Ta), an excessive voltage drop occurs at the output terminal (Vo) according to the conduction resistance of the first FET (Ta), and the first FET (T)
The source voltage (output voltage) of a) decreases. Then, the source voltage of the second FET (Tb) is also lowered and the gate-source voltage is increased, so that the second FET (Tb)
Conducts. Therefore, the diode groups (Ja) to (Jd)
The gate voltage of the first FET (Ta) is clamped and lowered by the forward voltage (Vf) of 1 to limit the output overcurrent of the first FET (Ta).

[0004]

The problem to be solved is the forward voltage (V) of the diode groups (Ja) to (Jd).
Since f) has temperature dependency, the limit value of the output overcurrent fluctuates due to the temperature change, especially when the temperature decreases,
Since the forward voltage (Vf) becomes large and the limit value of the output current becomes large, there arises a problem that the first FET (Ta) is destroyed at a low temperature.

[0005]

According to the present invention, an output field effect transistor having a drain and a source connected between a power supply and an output terminal, a switching element which operates in response to a voltage between the output terminal and the power supply, and a temperature non-transistor. And an overcurrent limiting section which is connected in series with a dependent constant voltage section and is inserted between the gate and the source of the output field effect transistor.

[0006]

According to the above technical means, the gate voltage of the output FET is clamped by the temperature-independent constant voltage section, and the output overcurrent is stably limited and held regardless of the temperature change.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an embodiment of an overcurrent limiting circuit according to the present invention.
And FIG. 2 will be described below. The same parts as those shown in FIG. 3 are designated by the same reference numerals and the description thereof will be omitted. The difference is that instead of the conventional temperature-dependent diode groups (Ja) to (Jd) for output voltage clamping, a temperature-independent constant voltage unit (A) is used, which is used as a switching element. Two FETs (Tb) are connected in series and are inserted between the gate and the source of the first FET (Ta).
The overcurrent limiting portion (1) shown in (a) is formed. Second above
The FET (Tb) connects the gate (Gb) to the power supply terminal (Vcc), and the drain (Db) through the temperature independent constant voltage section (A) to the gate (Ga) of the output first FET (Ta). And the source (Sb) is connected to the output terminal (Vo). The constant voltage section (A) is the first FE
Upper and lower voltage terminals (Vp) (Vq) connected to the gate (Ga) of T (Ta) and the drain (Db) of the second FET (Tb), respectively, and an NPN having a large emitter area.
-Type first transistor (Qa) and second transistor (Qb) having a small emitter area are mirror-connected, and each collector is commonly connected to the gate (Ga) via the first and second resistors (Ra) and (Rb). And a current mirror circuit (CM) in which the emitter of the first transistor (Qa) is directly connected to the lower voltage terminal (Vq) and the emitter of the second transistor (Qb) is connected through the third resistor (Rc). , A collector and an emitter are respectively connected to the base through fourth and fifth resistors (Rd) (Re), and a collector is connected to the collector of the second transistor (Qb), and a third transistor diode (Qc) and a higher voltage A fourth transistor in which the collector is connected to the terminal (Vp), the base is connected to the emitter of the third transistor diode (Qc), and the emitter is connected to the lower voltage terminal (Vq). ; And a static (Qd).

In the constant voltage section (A), the first and second
For the transistors (Qa) and (Qb), the collector currents are (Ia) and (Ib), and the emitter area ratio is (Wa: Wb =
1: 5), the base-emitter voltage is (Va) (V
b), assuming that the saturation current is (Isa) (Isb) and the base current can be ignored with respect to the collector current: Va = (kT / q) ln (Ia / Isa) Vb = (kT / q) ln (Ib / Isb) Isa: Isb = 1: 5 Ia≈Ib Ib = (1 / Rc) (Va−Vb). Next, assuming that the voltage drop of the resistor (Rb) is (Vr), Vr = Ib · Rb = (1 / Rc) (Va−Vb) · Rb = (kT / q) · ln {(Ia / Ib) ( Isb / Is
a)}. (Rb / Rc) = (kT / q) .ln5. (R
b / Rc).

Therefore, assuming that the gate-source clamp voltage of the first FET (Ta) is (Vcp) and the base-emitter voltages of the third and fourth transistors (Qc) (Qd) are (Vbc) (Vbd), respectively. , Vcp = Vr + (1 / Re) (Rd + Re) · Vbc +
Vbd (however, both Vbc and Vbd are set equal to about 0.6V).

Therefore, when Vcp is differentiated with respect to temperature, (∂Vcp / ∂T) = (k / q) ln5 (Rb / R
c)-{(1 / Re) (Rd + Re) +1} · (∂Vb
d / ∂T). Here, since (∂Vbd / ∂T) is known, if resistances (Rb) and (Rc) are selectively set after selecting resistances (Rd) and (Re), the temperature gradient of Vcp is eliminated. It can be kept constant regardless of temperature.
Alternatively, a temperature gradient can be intentionally provided.

The operation of the present invention based on the configuration of the above embodiment is the same as the conventional one, and when an overcurrent flows through the first FET (Ta),
The source voltage of the second FET (Tb) decreases and becomes conductive, and the constant voltage unit (A) clamps the output voltage to hold the output current at a constant limit value.

Next, as shown in FIG. 1B, the lower voltage terminal (Vq) of the constant voltage section (A) is connected to the first FET (T).
Directly connected to the source (Sa) of a) and the gate (Ga)
The upper voltage terminal (Vp) may be connected to the second FET (Tb) via the second FET (Tb) to form the overcurrent limiting unit (2). In this case, since the second FET (b) becomes conductive when the source voltage of the first FET (Ta) drops including the constant voltage, the second FET (b) operates slightly later than the embodiment shown in FIG. 1 (a). .

Further, as shown in FIGS. 2 (a) and 2 (b), a temperature-independent constant voltage element composed of a Zener diode (Za) (Zb) having a Zener voltage of 5 V or less is used as the constant voltage section (A). However, the operation is the same for each.

[0014]

According to the present invention, in the circuit for limiting and protecting the overcurrent of the output field effect transistor in the MOSIC output circuit, the output gate voltage is clamped by the temperature-independent constant voltage section. Can be maintained at a constant value regardless of temperature by preventing the damage of the element, especially at low temperature.

[Brief description of drawings]

FIG. 1A is a circuit diagram showing an embodiment of an overcurrent limiting circuit according to the present invention. (B) is a circuit diagram showing another embodiment of the overcurrent limiting circuit according to the present invention.

FIG. 2A is a circuit diagram showing another embodiment of the overcurrent limiting circuit according to the present invention. (B) is a circuit diagram showing another embodiment of the overcurrent limiting circuit according to the present invention.

FIG. 3 is a circuit diagram showing an example of a conventional overcurrent limiting circuit.

[Explanation of symbols]

 1 Overcurrent limiter Vcc Power supply terminal Vo Output terminal Ta Output field effect transistor Tb Switching element A Constant voltage part

Claims (4)

[Claims] 1. A series of an output field effect transistor in which a drain and a source are connected between a power supply and an output terminal, a switching element which operates in response to a voltage between the output terminal and the power supply, and a temperature-independent constant voltage section. An overcurrent limiting circuit comprising: an overcurrent limiting unit connected to and inserted between the gate and the source of the output field effect transistor. 2. The overcurrent limiting circuit according to claim 1, wherein the switching element is a field effect transistor. 3. The temperature-independent constant-voltage section includes a first transistor having a smaller emitter area, and upper and lower voltage terminals connected to the gate or source of the output field effect transistor directly or via a switching element, respectively. And a second transistor having a larger emitter area are mirror-connected, and their collectors are commonly connected to the upper voltage terminal via the first and second resistors, and the emitter of the first transistor is directly connected to the lower voltage terminal. And a current mirror circuit in which the emitter of the second transistor is connected via a third resistor, and the collector and emitter of the current mirror circuit are fourth and fifth.
Connect to the base via a resistor and connect the collector to the second
A third transistor diode connected to the collector of the transistor; and a fourth transistor having a collector connected to the upper voltage terminal, a base connected to the emitter of the third transistor, and an emitter connected to the lower voltage terminal. The overcurrent limiting circuit according to claim 1 or 2. 4. The overcurrent limiting circuit according to claim 1, wherein the temperature-independent constant voltage section is composed of a temperature-independent constant voltage element.