JPH079470Y2 - Asynchronous / synchronous code converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention relates to a code conversion device, and more particularly to a asynchronous conversion code that is converted into a synchronous code and sent out, and this is received and inversely converted to the original asynchronous mode. The present invention relates to an asynchronous / synchronous code conversion device for returning to an asynchronous code.

[Conventional technology]

Conventionally, this type of code conversion device converts an asynchronous code into a synchronous code at a speed ratio of 1: 1. An example of the configuration is shown in FIGS. 3 (a) and 3 (b). FIG. 3 (a) is a block diagram of the encoding unit that constitutes the transmission unit, and its outline will be described. Here, the input asynchronous code (also referred to as an asynchronous code) 1 causes a sampling pulse generation circuit 101 to generate a sampling pulse, and a pulse 7 for sampling the center of the code is shifted register 103 and code monitoring circuit 102.
Output to. The code monitoring circuit 102 is a shift register 103.
The start, stop, and break signals of the start / stop code input to (3) are output, and a shift pulse 8 is generated and sent to the buffer memory 104 when the start bit is placed on the shift register 103 to the stop bit. The buffer memory 104 is a register for performing a buffer operation between the shift register 103 and the shift register 105. The buffer memory 104 reads the data of the shift register 103 with the shift pulse 8 from the code monitoring circuit 102 and shifts it with the transfer pulse 12 from the transmission controller 106. The data is output to the register 105. Then, the data in the shift register 105 is sequentially read by the transmission shift pulse 15 accompanying the transmission timing pulse 3 supplied from the outside, and is output through the flip-flop (FF) 108, the AND circuit 109, and the flip-flop 110. The synchronous encoding output 2 from the encoding unit 100 is sent to the receiving-side decoding unit 120 shown in FIG. 3 (b).

FIG. 3B is a block diagram of the decoding unit which performs the inverse transformation of the coding unit shown in FIG.
The synchronous coded output 2 transmitted from the receiver, that is, the received synchronous code 5 is received by the shift register 122, the code on the shift register 122 is monitored by the monitoring circuit 121, and when 1 byte is aligned, the monitoring circuit 121 shifts the code. Outputs pulse 19,
The data in the shift register 122 is transferred to the buffer memory 123. Then, the transfer pulse 2 from the reception controller 125
2 to transfer the data in the buffer memory 123 to the shift register 12
After the data is transferred to 4, the data is read by the reception shift pulse 25 from the reception shift pulse generating rotation 126, and the flip-flop 128, the AND circuit 129 and the flip-flop 130 are read.
Output through the flip-flop 130
The original asynchronous Asynchronous code 6 inversely converted by the above is obtained.

[Problems to be solved by the device]

However, the above-described conventional code conversion device performs conversion with a speed ratio of 1: 1 as shown in FIG.
There is a drawback in that a 1200 baud start / stop code cannot be transmitted / received using a transmission path for transmitting a 2400 bit / sec synchronous code. Generally, when transmitting and receiving using a start-and-stop type code, many of which use communication lines and the like are less than 1200 baud, but recent digitalized synchronous transmission lines are
2400bit / sec or more is common. Therefore, it is necessary to convert the speed ratio to 1: N instead of 1: 1.

[Means for Solving the Problems]

The asynchronous / synchronous code converter according to the present invention includes an encoding unit that converts an asynchronous asynchronous code into a synchronous code at a code rate ratio of 1: 1 and an asynchronous code that is synchronously encoded by the encoding unit. A decoding unit for returning to a code, a transmission timing frequency dividing circuit for dividing an externally supplied synchronous coded transmission timing signal by a frequency division ratio N, and a frequency division ratio N for an externally supplied synchronous code reception timing signal. A reception timing frequency dividing circuit for dividing the output of the transmission timing frequency dividing circuit as a transmission timing signal of the encoding unit, and an output of the reception timing frequency dividing circuit of the receiving unit of the decoding unit. The input is made as a timing signal.

[Action]

In the present invention, by switching the frequency division ratio N of the transmission and reception timing frequency dividing circuit, it is possible to convert any speed ratio.

〔Example〕

 Hereinafter, the present invention will be described with reference to the drawings.

FIG. 1 shows an embodiment of an asynchronous / synchronous code conversion device according to the present invention. FIG. 1 (a) is a block diagram of an encoding unit forming the transmitting unit, and FIG. 1 (b) is a receiving unit. It is a block diagram of a decoding unit. In FIG. 1A, a sampling pulse generating circuit 101, a code monitoring circuit 102, a shift register 103, a buffer memory 104, and a shift register.
105, the transmission controller 106, the OR circuit 107, the flip-flops 108 and 110, and the AND circuit 109 constitute a coding unit 100 on the transmission side. The asynchronous asynchronous code 1 is converted into a synchronous code, that is, a synchronous coded output 2 at a code rate ratio of 1: 1. The encoding unit 100 is provided with a transmission timing divider circuit 111 that divides the transmission timing pulse 3 supplied from the outside with an arbitrary division ratio N.
The frequency-divided output of the frequency dividing circuit 111 is sent to the shift register 105, the transmission controller 106, and the flip-flops 108 and 110 as the transmission shift pulse 15.

Further, in FIG. 1B, the monitoring circuit 121, the shift register 122, the buffer memory 123, and the shift register
124, a reception controller 125, a reception shift pulse generation circuit 126, an OR circuit 127, and flip-flops 128 and 1
30 and an AND circuit 129 constitute a decoding unit 120 on the receiving side, which decodes the asynchronous code synchronously coded by the coding unit 100 on the transmitting side as in the conventional case. 5, and reversely returns it to the asynchronous asynchronous code 6. The decoding unit 120 is provided with a reception timing frequency dividing circuit 131 for frequency-dividing the reception timing pulse 4 supplied from the outside by an arbitrary frequency division ratio N. The frequency division output of the frequency dividing circuit 131 is The read pulse 18 is sent to the monitoring circuit 121 and the shift register 122. In addition,
This embodiment uses the conversion method defined in CCITT Recommendation V22 and the like.

Next, the operation of the configuration of the above embodiment will be described. First, in FIG. 1A, the input asynchronous code 1 causes the sampling pulse generation circuit 101 to generate a sampling pulse, and the pulse 7 for sampling the center of the code is sent to the shift register 103 and the code monitoring circuit 102. Output. This monitoring circuit 102 outputs the start, stop and break signals of the code input to the shift register 103, and generates a shift pulse 8 when the start bit on the shift register 103 is 1 byte up to the stop bit. To do. When the 1-byte length is all the start code polarity (break signal detection), the detection signal 9 is generated.
The buffer memory 104 is a register for performing a buffer operation between the shift register 103 and the shift register 105, reads the data in the shift register 103 with the shift pulse 8 generated from the code monitoring circuit 102, and transfers it from the transmission controller 106. After outputting the data to the shift register 105 with the pulse 12, the contents are reset. Further, when there is a read operation to the buffer memory 104, the transfer request signal 11 is output to the transmission controller 106.

Then, when the transmission timing pulse 3 is supplied from the outside after the data is transferred to the shift register 105, the timing pulse 3 is frequency-divided by the frequency dividing circuit 111, and then its output is shifted as the transmission shift pulse 15. It is sent to the register 105, transmission controller 106, flip-flops 108 and 110. As a result, the shift register 105 sequentially reads the code data based on the transmission shift pulse 15, and the flip-flop 108, the AND circuit 109, and the flip-flop 110.
The synchronous coded output 2 is transmitted as a transmission code to the receiving section described later.

However, the shift register 105 outputs the notification signals 13 and 14 to the transmission controller 106 after the shift is completed, and the transmission controller 106 receives the shift completion notification signals 13 and 14 and outputs the signal 10 to the OR circuit 107. Through the AND circuit 109. This signal 10 is a signal indicating that the shift is completed, and the code immediately before the break signal is the monitoring circuit.
This prevents the detection signal 9 from 102, that is, the break signal from being not transmitted. The flip-flops 108 and 110 are for adjusting the timing of the transmission code.

Next, in FIG. 1 (b), the reception timing pulse 4 is supplied from the outside, and the encoding unit 100 on the transmission side is provided.
When the reception synchronization code (same as the synchronization encoding output 2) 5 is supplied from the reception timing pulse 4, the reception timing pulse 4 is divided by the frequency divider 131
After being divided by, the output pulse is sent to the monitor circuit 121 and the shift register 122 as the read pulse 18. Then, the monitoring circuit 121 monitors the code on the shift register 122, and when the data has 1 byte, the shift pulse is shifted.
It outputs 19 and transfers the data in the shift register 122 to the buffer memory 123. Then, after the data in the buffer memory 123 is transferred to the shift register 124 by the transfer pulse 22 from the reception controller 125, the data is sequentially read by the reception shift pulse 24 from the reception shift pulse generation circuit 126, and the flip-flop 128 and the AND circuit 129 are read. And the output from the flip-flop 130, so that the flip-flop 130 reversely converts the reception synchronization code 5 transmitted from the encoding unit 100 on the transmission side and returns it, that is, the original start-stop asynchronous The code can be retrieved. In FIG. 1B, 16 is a break detection signal generated from the monitoring circuit 121, 17 is a stop code deletion detection signal sent from the monitoring circuit 121 to the reception controller 125, and 20 is from the reception controller 125. A generated reception code output completion signal, 21 is a signal indicating that data has been written in the buffer memory 123, and 23 is the shift register 12
4 shift completion signal, 25 receive shift pulse generation circuit 126
Is a control signal for changing the pulse speed of.

Thus, according to the present embodiment, the transmission timing divider circuit
When the division ratio N of 111 is, for example, 1: 2 (N = 2,1200: 240
0 (bit / sec)), the relationship between the synchronous encoded output 2 of the encoding unit 100 and the transmission timing pulse 3 is as shown in FIG. As a result, the read pulse 18 to the decoding unit 120 on the receiving side is divided by the reception timing dividing circuit 131, so that only 1 bit is input to the shift register 122. Therefore, by setting the frequency division ratio N to match between the transmitting side frequency dividing circuit 111 and the receiving side frequency dividing circuit 131, it is possible to restore the original start / stop code.

[Effect of device]

As described above, according to the present invention, the transmission timing signal input to the encoding unit for converting the asynchronous code into the synchronous code and the reception timing signal input to the decoding unit on the receiving side are respectively separated at the code rate ratio of 1: 1. It is possible to provide a code conversion device having a conversion speed ratio of 1: N by performing frequency division with a frequency circuit. Therefore, by adding a frequency dividing circuit to the conventional device and switching the frequency dividing ratio, the same circuit can deal with various speed ratios, and the practical effect is great.

[Brief description of drawings]

FIGS. 1 (a) and 1 (b) are block diagrams of an encoding unit and a decoding unit showing an embodiment of a code conversion device according to the present invention, and FIG. 2 is a block diagram of a frequency dividing circuit in the embodiment of FIG. The ratio N is 2
FIG. 3 (a) and FIG. 3 (b) are block diagrams of an encoding unit and a decoding unit showing an example of a conventional device, and FIG. 4 shows a converted output signal according to a conventional example. It is a figure. DESCRIPTION OF SYMBOLS 1 ... Asynchronous asynchronous code (start / stop code), 2 ... Synchronous coding output, 3 ... Transmission timing pulse, 4 ... Reception timing pulse, 5 ... Reception synchronous code, 100 ... Encoding unit, 111 ... Transmission timing frequency divider circuit, 120 ... Decoding unit, 131 ... Reception timing divider circuit.

Claims (1)

[Scope of utility model registration request] 1. A code conversion device for converting an asynchronous asynchronous code into a synchronous code, and an encoding unit for converting the asynchronous code into a synchronous code at a code rate ratio of 1: 1 and a synchronous code in the encoding unit. A decoding unit for converting the converted asynchronous code back to an asynchronous code; and a transmission timing frequency dividing circuit for frequency-dividing an externally supplied synchronous code transmission timing signal by a frequency division ratio N,
A reception timing frequency dividing circuit for dividing a synchronization code reception timing signal supplied from the outside by a frequency division ratio N, and inputting an output of the transmission timing frequency dividing circuit as a transmission timing signal of the encoding unit, An asynchronous / synchronous code conversion device, wherein an output of the reception timing frequency dividing circuit is input as a reception timing signal of the decoding unit.