JPH0795413A - Pseudo halftone binarization device - Google Patents

Abstract

(57) [Abstract] [PROBLEMS] To provide a pseudo halftone binarization device capable of binarizing a multi-valued image while reducing the influence of block distortion due to compression encoding. A pseudo halftone 2 having image decompression / decoding means, address generation means, and binarization means having variable means for changing the value of an error signal based on the address of the address generation means.
The digitizer was constructed. [Effect] The circuit scale can be reduced without performing post-filter processing to reduce block distortion.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention converts a grayscale image having multi-value gradation into a pseudo-halftone image which expresses the light and shade of the image by the areal density of dots in binary or limited multi-valued gradation. It relates to a pseudo halftone binary device.

In particular, the present invention relates to a pseudo halftone binarization device for an image compressed by dividing the image into coding blocks of a small area.

[0003]

2. Description of the Related Art A still image used for printing such as a printer or a facsimile requires an information amount of, for example, several megabytes or several tens of megabytes per A4 sheet.

Generally, various image information compression encoding methods have been proposed in order to reduce the time and cost required for transmitting / accumulating such a large amount of information. Above all, a method of dividing an image into blocks of a small area and performing compression coding for each block is currently widely used.

Further, in the still image used for the above-mentioned printing, many printing methods such as the electrophotographic method and the ink jet method can essentially express the gradation of one pixel only by the presence or absence of a dot (1 bit). In the case of expressing a multi-valued image, pseudo halftone expression is used in which the density of an image is perceived by changing the areal density of a set of a plurality of dots (Japanese Patent Laid-Open No. 3-253175).

The error diffusion method is widely used as a pseudo halftone expression method. The error diffusion method introduces the error generated when binarizing into the original image,
This is a method of minimizing the density error between the original image and the result.
The error diffusion method also has an advantage that the generated pseudo-halftone image has excellent gradation and resolution.

[0007]

2. Description of the Related Art In the compression coding method based on the above-described block division, pattern-like deterioration called block distortion occurs at the area boundaries of the divided blocks.

When the block distortion is usually a problem, post-filter processing for smoothing the block distortion at the block boundary is performed on the decompressed image after the decoding processing. (JP-A-3-17489
1) That is, as shown in FIG. 7, in a conventional image processing apparatus for generating a pseudo-halftone image for printout, in order to process the above-described decompressed image, an image decoding unit 701 is used. After the output decompressed image is smoothed by the filter processing unit 702, the binarization processing unit 703 executes error diffusion processing to obtain a desired pseudo halftone image.

Here, the purpose of the smoothing process by the post filter 702 is to diffuse the pattern-like distortion caused by the block division to peripheral pixels to make it visually inconspicuous. On the other hand, the purpose of the error diffusion method in the pseudo intermediateization of the image is to diffuse the error due to the binarization, and thus overlaps with the function of the post filter. That is, there is waste in the configuration of the conventional pseudo halftone binarization device.

[0010]

In order to solve the above problems, the present invention encodes a range of error data to be referred to when performing error diffusion processing on a decompressed image output by an image encoding means. An error diffusion range setting means is provided which is variable according to the relative position with the boundary of the digitized block. Further, according to the present invention, a weighting factor setting means is provided for varying the weighting factor for each error data when the error data is renormalized into the expanded image, according to the relative position with the boundary of the coding block. .

[0011]

By providing the error diffusion range setting means or the weight coefficient setting means as described above, in the vicinity of the boundary of the coding block, the error is diffused to pixels far from the point far from the boundary. As a result, it is possible to effectively reduce the pattern distortion generated on the block boundary.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be illustratively described in detail below with reference to the drawings. However, unless otherwise specified, the dimensions, materials, shapes, other relative arrangements, etc. of the components described in this embodiment are not intended to limit the scope of the present invention thereto, but merely illustrative examples. It is nothing more than a thing. In the following embodiments, the block size in encoding is 8 pixels in the horizontal direction and 8 pixels in the vertical direction, and the gradation per pixel is from level 0 to 255.
256 levels up to the level.

The configuration of the first embodiment of the present invention is shown in FIG.

The pseudo halftone binarization apparatus of this embodiment is shown in FIG.
Although not shown in the figure, a decoder 101 which decodes a compressed image coded based on block division by a corresponding encoder and reproduces it as a decompressed image signal, and pseudo-halftone conversion by error diffusion processing It is composed of a binarization processing unit 102 for generating a binary image and an address generation circuit 103 for designating the horizontal and vertical positions of the pixel of interest in the image.

The decompressed image signal decoded by the decoder 101 is input to the binarization processing unit 102 as a raster signal. The signal input to the binarization processing unit 102 is added to an error signal described later by the adder 104, and becomes a corrected image signal in which an error is incorporated in the expanded image signal. The corrected image signal is compared with a predetermined threshold level such as 128 level by the comparator 105, and if the value is equal to or higher than the threshold value, a 255 level signal is output.
If the value is less than the threshold value, a 0 level signal is output, and this binary image signal is output as a pseudo halftone image. Here, the corrected image signal and the binary image signal are used to derive an error signal. The corrected image signal and the binary image signal are input to the subtractor 106, the difference between the corrected image signal and the binary image signal is calculated, and the difference signal is output. The difference signal is
It is input to the error diffusion range setting unit 107. The error diffusion range setting unit 107 sets the range of the difference signal used for the error diffusion processing based on the relative position of the pixel of interest with respect to the boundary of the coding block.

The differential signal input to the error diffusion range setting unit 107 is a buffer memory 1 composed of delay elements.
08, the differential signal of a region having a relatively constant range is extracted from the pixel of interest and output. In this embodiment, as one embodiment of the above-mentioned area, an area constituted by the differential signals A0 to A8 as shown in FIG. 2A is set. Of the differential signals A0 to A8 output from the buffer memory 108, the differential signals A0 to A3 are input signals to the direct arithmetic operation circuit 113. Is selected and input to the arithmetic circuit 113.

The selectors 109 and 110 select the difference signal according to the relative position of the pixel of interest with respect to the boundary of the coding block. The difference signal is selected so that the difference signal outside the coding block to which the pixel of interest belongs is selected as much as possible. In the present embodiment, as the selection described above, the selector 109 selects the target pixel from A4 and A5 in the vicinity of the upper boundary of the block (a in FIG. 3A,
If it is in the range (b, c), A5 is selected, and if it is in the other range (range of d, e, f in FIG. 3), A4 is selected. If the pixel of interest is in the vicinity of the left boundary of the block (range of a and d in FIG. 3) among A6, A7 and A8, A6 is selected and the pixel of interest is in the vicinity of the right boundary of the block (c of FIG. 3). , F range), A8 is selected, and otherwise (range b and e in FIG. 3) A7 is selected.

The operation of controlling the selectors 109 and 110 by the counters 111 and 112 and the selection of the difference signal will be described in detail below.

The horizontal and vertical position addresses in the image of the pixel of interest generated by the address generation circuit 103 are given to the vertical counter 111 and the horizontal counter 112 of the error diffusion range setting unit 107.

Vertical counter 111 and horizontal counter 11
2 is a modulo 8 counter, which has vertical address 0 and horizontal address 0 at the upper left corner and vertical address 7 and horizontal address 7 at the lower right corner in the coding block shown in FIG. The output values of the counter 111 and the counter 112 serve as control signals to the selector 109 and the selector 110. When the output value of the vertical counter 111 is from 2 to 7 and the output value of the horizontal counter 112 is from 2 to 5, the pixel of interest is within the area marked with a in FIG. At this time, it is considered that the pixel of interest is near the center of the coding block, the selector 109 selects the difference signal A4, and the selector 110 selects the difference signal A7, whereby the city block distance 2 shown in FIG. The differential signal in the area of is set as the error diffusion range. Here, pay attention to the output value of the vertical counter 111. When the output value of the vertical counter 111 is 0 or 1, the pixel of interest is within the area labeled d in FIG. At this time, since the target pixel is near the upper boundary of the coding block, the difference signal in the coding block adjacent to the upper side of the coding block to which the target pixel belongs is used to reduce the effect of block distortion. It is considered that the influence of block distortion can be reduced by diffusing the error. Therefore, the selector 109 selects the difference signal A5 to refer to the difference signal of the coding block adjacent to the upper side. Similarly, the selector 110
When the output value of the horizontal counter 112 is 0 or 1, the pixel of interest is near the left boundary of the coding block, so the difference signal A6 is selected to refer to the difference signal of the coding block adjacent to the left side, When the output value of the horizontal counter 112 is 6 or 7, the pixel of interest is near the right boundary of the coding block, so the difference signal A8 is selected to refer to the difference signal of the coding block adjacent to the right side.

By selectively varying the difference signal error diffusion range as described above, when the pixel of interest is near the boundary of the coding block, the difference signal outside the coding block contributes to the error diffusion processing to a greater extent. Therefore, the influence of block distortion can be reduced. The differential signals A0 to A3 output from the buffer memory 108 and the differential signals selected by the selector 109 and the selector 110 are input to the arithmetic circuit 113. In the arithmetic circuit 113, the above 6
The individual difference signals are subjected to a product-sum operation in accordance with a weighting coefficient that is determined in advance for each difference signal, and the result is output as an error signal. This error signal is again added to the next expanded image signal by the adder 104, and the binary processing is sequentially performed.

Next, a second embodiment of the pseudo halftone binarization apparatus according to the present invention will be described in detail.

The structure of the second embodiment is shown in FIG. In addition,
In FIG. 4, the parts having the same numbers as those in FIG. 1 have the same functions, and the duplicate description will be omitted.

The difference signal output from the adder 106 is
It is input to the buffer memory 401, and as in the first embodiment, a difference signal of a region having a relatively constant range is extracted and output from the pixel of interest. In this embodiment, as one embodiment of the above-mentioned area, an area constituted by the differential signals A0 to A11 as shown in FIG. 5 is set. The difference signal from A0 to A11 output from the buffer memory 401 is calculated by the arithmetic circuit 402.
Is input to. The arithmetic circuit 402 performs the sum-of-products operation on the above-mentioned twelve difference signals in accordance with the weighting coefficient determined in advance for each difference signal, and outputs the result as an error signal. At this time, the weighting factor setting unit 403 controls the weighting factor to be variable according to the position of the pixel of interest relative to the boundary of the coding block. less than,
The weighting factor setting operation by the weighting factor setting unit 403 will be described. When the horizontal and vertical position addresses in the image of the pixel of interest generated by the address generation circuit 103 are given to the vertical counter 111 and the horizontal counter 112 of the weighting coefficient setting unit 403, the vertical counter 111 and The horizontal counter 112 outputs the position address of the pixel of interest in the encoded block. ROM405
In order to perform the sum of products operation of the difference signals A0 to A11,
A plurality of sets of weighting factors corresponding to each of the differential signals A0 to A11 are stored, and one set of weighting factors is selected according to the position address in the coding block of the pixel of interest. That is, the position address output from the counter 111 and the counter 112 is converted by the address conversion circuit 404 into the address of the ROM 405 in which the set of weighting factors corresponding to the position address is stored, and the address specified by the address conversion circuit 404. The above set of weighting factors are output from the ROM 405 and set in the multipliers 406a to 406l inside the arithmetic circuit 402, respectively.

Here, the relationship between the position address in the coding block of the pixel of interest and the weighting factor will be described.

The object of the present invention is to effectively incorporate the difference signal of the pixels outside the coding block into the error signal when the pixel of interest is near the boundary of the coding block. When the pixel is in the vicinity of the center of the encoding block, the weighting coefficient of the difference signal in the vicinity of the pixel of interest is set to a large value so that the difference signal in the vicinity of the pixel of interest is greatly affected, and the pixel of interest is in the vicinity of the coding block boundary At this time, the weighting coefficient of the differential signal located far from the pixel of interest is set to a large value so that the influence of the differential signal outside the coding block remains relatively large. For example, if the pixel of interest exists in the range of e in FIG. 3 (when the horizontal address is 2 or more and 5 or less and the vertical address is 2 or more), it is determined that the pixel of interest is near the center of the encoded block, and the difference signal A0 To A11, the value of the weighting coefficient corresponding to the position of A11 is increased in the vicinity of the pixel of interest as shown in FIG.
If the pixel far from the pixel of interest is small (for example, 1/16), and if the pixel of interest exists in another part of FIG. 3, the value of the weighting coefficient is set for all areas as shown in FIG. 6B. By making it uniform (1/12), the influence of the differential signal outside the coding block is increased.

The weight signal and the difference signal set in this way are multiplied by the multipliers 406a to 406l, and the sum of the difference signals weighted by the multiplication is calculated by the adder 407 to obtain the error signal. And output from the arithmetic circuit 402.

Similar to the first embodiment, this error signal is again added to the next expanded image signal by the adder 104, and the binarization process is sequentially performed.

[0029]

As described above, according to the configuration of the present invention, the error signal is sent to the target pixel according to the relative position of the target pixel to the coding block boundary by the error diffusion range setting means or the weighting coefficient setting means. Since the influence of the image signal outside the coding block can be made relatively large in the vicinity of the coding block boundary, it is possible to reduce the block distortion during compression coding as in the conventional case. It is not necessary to perform post-filter processing, and the circuit scale of the pseudo halftone binarization device can be reduced.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a first embodiment of the present invention.

FIG. 2 is a diagram showing a region of a differential signal used in the first embodiment.

FIG. 3 is a diagram for explaining a relationship between a position of a pixel of interest in an encoding block and an error diffusion range in the first embodiment.

FIG. 4 is a configuration diagram of a second embodiment of the present invention.

FIG. 5 is a diagram showing a region of a differential signal used in the second embodiment.

FIG. 6 is a diagram for explaining a relationship between a position of a pixel of interest in an encoding block and an error diffusion range in the second embodiment.

FIG. 7 is a block diagram of a conventional pseudo-halftone binarization device for compressed images.

[Description of Codes] 101 Decoder 102 Binarization Processing Unit 103 Address Generation Circuit 113 Operation Circuit

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Claims (3)

[Claims] 1. An image decoding means for dividing a multi-valued image signal into coding blocks of a small area and decoding a compressed image signal coded for each coding block to obtain a decompressed image signal, Binarization processing means for converting the decompressed image signal from a multi-valued image to a binary image, and address generation means for giving horizontal and vertical addresses in the image of the pixel of interest when performing the binarization processing. In the pseudo-halftone binarizing device provided, the binarization processing unit outputs the binarized image signal based on the magnitude of the density difference of the multivalued image, and the error signal generated by the binarization. Calculating means for calculating, adding means for incorporating the error signal into the expanded image signal, and varying means for varying the value of the error signal based on the address of the pixel of interest given by the address generating means. Pseudo halftone characterized by the provision of Binary system. 2. The variable means has an error diffusion range setting means for changing the area of the image signal referred to by the arithmetic means according to the relative position of the pixel of interest to the coding block boundary. Item 1. The pseudo halftone binarization device according to Item 1. 3. The variable means comprises weighting coefficient setting means for changing the weighting coefficient for the image signal referred to by the computing means in accordance with the position of the pixel of interest relative to the coding blocking boundary. Claim 1
The pseudo halftone binarization apparatus described.