JPH0795443A - External sync signal addition circuit - Google Patents

Abstract

(57) [Summary] [Object] To provide an external synchronization signal addition circuit capable of adding an external synchronization signal to a video signal with an inexpensive configuration. A clamp circuit 14 for clamping a sync signal in a video signal to a potential higher than the sync signal and outputting the clamped video signal, and an external sync signal having a potential lower than the sync signal synchronized with the external sync signal. An analog switch 16 for outputting a video signal with an external synchronizing signal to be superimposed on the clamped video signal, and a reference voltage generating circuit 15 for setting the potential of the external synchronizing signal and the clamp potential of the synchronizing signal. Prepared

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an external synchronizing signal adding circuit for adding an external synchronizing signal to a video signal.

[0002]

2. Description of the Related Art In a video display device, a video is normally displayed in synchronization with a sync signal added to the video signal. However, depending on the application, it may be desirable to synchronize with an external synchronization signal that is different from the synchronization signal in the video signal. Therefore, when designing a video display device for a wide range of applications, consider compatibility with external synchronization signals. There is a need.

FIG. 5 is a block diagram of a video display device compatible with an external synchronizing signal according to a conventional example. In the figure, 1 is a video display device, which is a video signal input terminal 2, an external sync signal input terminal 3, a sync separation circuit 4 for separating the sync signal from the video signal, and a changeover switch for switching the separated sync signal and the external sync signal. The circuit 5 and the signal processing unit 6 superimposes the sync signal or the external sync signal output from the changeover switch circuit 5 on the video signal from which the sync signal is separated. That is, the changeover switch circuit 5 is required to obtain the synchronization even with the external synchronization signal.

By the way, in recent years, the circuits constituting the image display apparatus are also becoming ICs, but there are cases where it is desired to use a device that does not support an external synchronization signal due to cost reasons.

[0005]

FIG. 6 is a block diagram of a video display device IC which is not compatible with an external synchronization signal. As shown in this figure, if the main part of the video display device 1 including the sync separation circuit 4 is integrated into an IC by the video display IC 7, unless the video display IC 7 is compatible with an external sync signal,
It becomes impossible to switch between the sync signal in the video signal and the external sync signal.

In this case, in order to realize the function of synchronizing the video signal with the external synchronizing signal, there is a method of cutting the synchronizing signal in the video signal and newly adding the external synchronizing signal as a synchronizing signal. The circuit scale becomes large in order to completely eliminate the synchronizing signal in the video signal, so that there are drawbacks that the cost increases and the board area required for forming the circuit also increases.

The present invention has been made based on such a background, solves the above-mentioned drawbacks of the prior art, and does not support external synchronization (especially a video display IC).
It is also an object of the present invention to provide an external synchronization signal adding circuit capable of adding an external synchronization signal to a video signal with an inexpensive configuration even for a video display device using the.

[0008]

In order to achieve the above object, the present invention provides a clamp circuit for clamping a sync signal in a video signal to a potential higher than the sync signal and outputting the clamped video signal. And a superimposing unit that synchronizes an external synchronizing signal having a lower potential than the synchronizing signal with the external synchronizing signal to superimpose it on the clamped video signal and outputs a video signal with the external synchronizing signal.

The present invention further comprises potential setting means for setting the potential of the external synchronizing signal. Furthermore, in the present invention, the clamp potential of the synchronization signal is set by the potential setting means.

[0010]

According to the present invention, the amplitude of the sync signal is expanded from the original amplitude by clamping the sync signal in the video signal to a potential higher than that and then superimposing the external sync signal having a potential lower than the sync signal. A video signal with the external synchronization signal is obtained.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of an external synchronization signal adding circuit according to an embodiment, and FIG. 2 is a waveform diagram of each part of FIG. In FIG. 1, 11 is an external sync signal input terminal to which external sync signals of various amplitudes are input, 12 is a video signal input terminal, 13 is a sync signal component from the external sync signal input to the external sync signal input terminal 11. Is a sync separation circuit for separating the sync signal, and 14 is a sync tip clamp circuit for clamping the sync signal in the video signal input to the video signal input terminal 12.

Numeral 15 is a sync tip clamp circuit 1
A reference voltage generation circuit for generating a potential according to the clamp potential of the synchronization signal by 4 and the amplitude of the external synchronization signal superimposed on the clamped video signal clamped by the sync tip clamp circuit 14, and 16 is a voltage after the clamp. It is an analog switch that superimposes an external synchronizing signal whose amplitude is set according to the potential generated by the reference voltage generating circuit 15 on the video signal.

Next, the operation will be described. The potential of the synchronizing signal H is Va at the video signal input terminal 12 shown in FIG.
The video signal V of (a) is input, and the video signal V enters the sync tip clamp circuit 14. The sync signal H of the video signal V in the sync tip clamp circuit 14 is the clamp potential Vc (Vc> V) generated in the reference voltage generation circuit 15.
The image signal V1 after being clamped in (a) and shown in FIG. 2 (b) is obtained.

External sync signals (not shown) of various amplitudes are input to the external sync signal input terminal 11, and the sync signal component of them is separated by the sync separation circuit 13 so that one of the analog switches 16 is connected. It is output to the terminal. Further, in the reference voltage generation circuit 15, a potential Ve (Vc> Ve) according to the amplitude of the external synchronizing signal H1 of FIG. 2C and FIG. 2E superimposed on the clamped video signal V1 is set. , The voltage of the potential Ve is the analog switch 16
Applied to the other terminal of the. Therefore, the analog switch 16 superimposes the external synchronization signal H1 on the clamped video signal V1 in synchronization with the external synchronization signal (not shown) input to the external synchronization signal input terminal 11. The video signals V2 and V3 with the external synchronization signal shown in FIGS. 2D and 2F are obtained.

The sync separation circuit 13 described above corresponds to the set potential Ve of the reference voltage generation circuit 15 regardless of the amplitude of the external sync signal input to the external sync signal input terminal 11. It is possible to superimpose the external synchronization signal H1 having a constant amplitude on the clamped video signal V1.

FIG. 3 is a block diagram of an entire video display system to which the present invention is applied, and an external synchronizing signal adding circuit 17 including a sync separation circuit 13, a sync tip clamp circuit 14, a reference voltage generating circuit 15, and an analog switch 16.
Is provided in front of the video display IC 18. That is, the video signal V2 with the external synchronization signal shown in FIG.
Are input to the video signal input of the video display device IC18. With this configuration, it is possible to inexpensively design the video display device compatible with the external synchronization signal by using the device (IC) that does not support the external synchronization signal H1.

By the way, the amplitude of the synchronizing signal H in the video signal V is usually standardized. This standard value is Vstd. On the other hand, in the video display device, the sync signal is often taken out after the video signal V is sync-tip clamped. Therefore, the potential difference ΔV between the potential Vc and the potential Ve is
It is desirable to make it larger than Vstd. However, too much Δ
If V is made too large, the dynamic range of the circuit at the subsequent stage of this circuit may be exceeded. Therefore, ΔV = V
It is considered preferable to use std. It should be noted that the presence of ΔV makes it possible to add the external synchronizing signal H1 having a larger amplitude than the synchronizing signal H of the video signal V to the clamped video signal V1 in FIGS. 2B and 2D. It is obvious without comparing with.

Here, the expected result differs depending on the temporal relationship between the synchronizing signal H in the video signal V and the external synchronizing signal H1. As shown in FIG. 2E, when the timings of the synchronizing signal H in the video signal V and the external synchronizing signal H1 are deviated, the video signal V3 with the external synchronizing signal output from this circuit is As shown in f), the external sync signal H1 is superimposed on the video signal portion between the sync signals H, and a normal video may not be displayed on the video display device. However, as shown in FIG. 2C, as long as the timing of the synchronizing signal H in the video signal V and the timing of the external synchronizing signal H1 match, the video signal V2 with the external synchronizing signal output from this circuit is As shown in FIG. 2D, since the amplitude of the synchronizing signal H in the video signal V is increased as it is, it can be expected that a normal video is displayed on the video display device.

FIG. 4 is a concrete configuration diagram of the synchronizing signal adding circuit according to the embodiment. The sync separation circuit 13 includes a transistor Q1 (2SC2785) and a transistor Q2 (2SA1).
175) and the resistors and capacitors having the ratings shown in the drawing, and a collector current flows through the transistor Q2 at the timing of the sync signal component of the external sync signal (not shown) input to the external sync signal input terminal 11. Further, the reference voltage generation circuit 15 includes three transistors Q3 to Q5 having the same standard as the transistor Q1, resistors and capacitors having the illustrated ratings, and a Zener diode (MTZJ-2.
7), the potential Ve corresponding to the amplitude of the external synchronizing signal H1 is set according to the transistors Q3 and Q4 and the resistance between the collector and the emitter thereof, and the collector current of the transistor Q2. The clamp potential Vc is set according to the collector current of the transistor Q5 which is determined based on the base current of Q3.

The sync tip clamp circuit 14 has a transistor Q6 and the resistors and capacitors having the ratings shown in the figure. The emitter current of the transistor Q6 is determined according to the collector current of the transistor Q5.
The sync signal H of the video signal V input to the base of
It is clamped to the clamp potential Vc by the transistor Q6. The analog switch 16 includes a transistor Q7 having the same standard as the transistor Q1 and a transistor Q7.
2 and transistors Q8 and Q9 of the same standard, the clamped video signal V1 is input to the base of the transistor Q8, the collector current of the transistor Q2 is input to the base of the transistor Q7, and the collector of the transistor Q7 is supplied. The base of the transistor Q9 is connected, and the collectors of the transistors Q8 and Q9 are +9 via a resistor.
Each is connected to a V pull-up power supply.

Therefore, the transistor Q7 is turned on at the timing of the synchronizing signal component of the external synchronizing signal (not shown), the transistor Q8 is turned on by the clamped video signal V1, and the transistor Q9 is turned on when the transistor Q7 is turned on. Conducts, which causes the transistor Q
8, Q9, the video signal V with the external synchronization signal
2, V3 is obtained.

[0022]

According to the present invention, the synchronizing signal in the video signal is clamped to a potential higher than that, and then the external synchronizing signal having a potential lower than the synchronizing signal is superimposed, so that the amplitude of the synchronizing signal is initially reduced. Since the video signal with the external sync signal expanded from the amplitude of the external sync signal can be obtained, the external sync signal can be added to the video signal with an inexpensive configuration, and the external sync signal can be applied to a video display device that does not support the external sync signal. As a result, it becomes possible to design an image display device for a wide range of applications.

[Brief description of drawings]

FIG. 1 is a block diagram of an external synchronization signal adding circuit according to an embodiment of the present invention.

FIG. 2 is a waveform diagram of each part of FIG.

FIG. 3 is a block diagram of the entire video display system to which the present invention is applied.

FIG. 4 is a specific configuration diagram of a sync signal adding circuit according to an embodiment of the present invention.

FIG. 5 is a block diagram of a video display device compatible with an external synchronization signal according to a conventional example.

FIG. 6 is a block diagram of a video display IC that is not compatible with external synchronization signals.

[Explanation of symbols]

 14 sync tip clamp circuit (clamp circuit) 15 reference voltage generation circuit (potential setting means) 16 analog switch (superposition means) 17 external synchronization signal addition circuit

Claims (3)

[Claims] 1. A clamp circuit for clamping a sync signal in a video signal to a potential higher than the sync signal and outputting the clamped video signal, and an external sync signal having a potential lower than the sync signal to the external sync signal. Synchronize and superimpose on the clamped video signal,
An external synchronization signal adding circuit, comprising: a superimposing unit that outputs a video signal with an external synchronization signal. 2. The external synchronization signal adding circuit according to claim 1, further comprising potential setting means for setting the potential of the external synchronization signal. 3. The external synchronization signal adding circuit according to claim 2, wherein the clamp potential of the synchronization signal is set by the potential setting means.