JPH0795569B2 - Semiconductor device - Google Patents

Description

Description: [Object of the invention] (Field of industrial application) [0001] The present invention relates to a semiconductor device in which the way of taking a connection electrode to a wiring layer embedded in a groove of a semiconductor substrate is devised, and particularly a memory in a dynamic memory. It is used for the contact portion of the cell capacitor to the opposite electrode.

(Prior Art) Conventionally, as a cell structure for highly integrating a dynamic RAM, one bit line contact is made to two widely used 1-transistor, 1-capacitor cells. Instead of (FIG. 3), a cell structure of one transistor, one capacitor, and one bit line contact for one cell is promising.
An example of this is the IVEC described in DIGEST P240 to P243 of IEDM (International Association) in 1984.
There is an (Isolation-Marged Vertical Capacitor) cell (Fig. 4).

FIG. 3A is a pattern plan view (here, showing four cells), FIG. 3B is a sectional view taken along the line AA ′ in FIG. 3A, and 1 is a P-type substrate, 2 is an element isolation region, 3 is a capacitor insulating film, 4 is a capacitor electrode, 5 is a gate insulating film, 6 is a transistor gate electrode, 7 is a transistor N-type diffusion layer, 8 is an insulating film, and 9 is a bit line. The contact, 10 is a bit line, C ₁ and C ₂ are first and second cells, respectively, and these cells have a symmetrical arrangement structure.

FIG. 4 (a) is a pattern plan view (for one cell), FIG. 4 (b) is a sectional view taken along the line BB ′ of FIG. 4 (a),
101 is a thermal oxide film formed on the groove 132 of the P-type substrate 100, 102
Is the storage node electrode 1 in the opening pattern of the thermal oxide film 101.
This is the place where 03 and the diffusion region 108 of the transistor are connected. 104 is an insulating film of a storage capacitor, 105 is a plate electrode, and this plate electrode 105 is commonly used for all cells. The data storage capacitor of the cell is formed between the electrodes 103 and 105. 106 is the gate insulating film of the transfer transistor, 107 is the same gate electrode, and 108 and 108 'are the same diffusion regions. 109 is a silicon dioxide film formed by the CVD method, and 110
Is a bit line contact, and 111 is a bit line. In this cell, the charge written by the transfer transistor is stored in the capacitor between the plate electrode 105 and the node electrode 103. This capacitor is formed around each island (convex) of the silicon substrate 100 as shown in FIG. 4 (a). In the system shown in FIG. 4, since the capacitor is of the vertical type, the degree of integration per unit area is high.

(Problems to be Solved by the Invention) The plate electrode 105 of the above-mentioned IVEC remains only inside the groove opened on the substrate 100 and is insulated from other layers on the surface of the substrate. The step of forming the plate electrode 105 is performed by using the substrate 100 among the plate electrode layers deposited on the substrate 100 (including the inside of the groove).
Only the plate electrode layer on the surface is removed, leaving the plate electrode 105 only in the groove. After that, since the plate electrode is oxidized to insulate it from other layers on the substrate 100, it is a complete self-alignment with respect to the groove, and no step for patterning is required.

In order to apply a potential to the plate electrode 105, according to the conventional idea, as shown in FIG. 2, the electrode material 105 ′ is drawn from the groove to the substrate so that the wiring 120 can be contacted on the substrate 100. Therefore, a patterning process by photo-etching is required, and thus the number of processes is increased.

An object of the present invention is to provide a semiconductor device capable of applying a potential to a buried electrode by omitting photolithography when drawing out the buried electrode.

[Structure of the Invention] (Means and Actions for Solving Problems) The present invention relates to a groove for element formation formed on a first conductivity type semiconductor substrate, and a groove formed along the side wall of the groove. Of the first conductive material that does not extend to the surface of the semiconductor substrate and is insulated from the groove, and is embedded in the groove of the first conductive material and extends to the surface of the semiconductor substrate outside the groove. A second conductive material that is absent and is insulated from the first conductive material and the groove; and a groove pattern for a contact having a region that is separated from the connection along the groove with respect to the first conductive material. A contact hole formed on the groove of the groove pattern, and a third conductive material connected to the second conductive material via the contact hole.

That is, in the contact region of the groove pattern, the first conductive material formed along the groove is configured to be separated from other circuits, and the contact hole is provided right above the groove of the groove pattern to form the third conductive material. The second conductive material is connected through the material. By doing so, the contact between the buried first electrode material and the external electrode can be made without using the photoetching process to form the extended electrode 105 'as shown in FIG.

Embodiment An embodiment of the present invention will be described below with reference to the drawings. First
FIG. 7A is a plan view of the pattern of the main part of the embodiment, and FIG. 8B is a sectional view taken along the line CC ′ of FIG. 8A, which corresponds to that of FIG. The same reference numerals are given to the parts to be performed. FIG. 1 shows a connecting portion for applying a potential to the plate electrode 105 shown in FIG. On the other hand, the cells of FIG. 4 are arranged in a matrix to form a cell array, and the structure of FIG. 1 is formed, for example, at the edge of the cell array.
That is, the connecting portion shown in FIG. 1 has a plane date shape as shown in FIG.
Is formed on the groove of the portion connecting one side of the date-shaped groove 132 and its opposite side. Since the cells of FIG. 4 are arranged in a matrix as described above, the grooves 132 pass between the cells, and thus the plate electrode (conductive material) 105 embedded in the grooves 132 is common in the cell array, First
The conductive material 105 in the figure is also commonly connected. The same applies to the capacitor electrode 103 in FIGS. 1 and 4 and is common.
However, the conductive material 103 'of FIG. 1 is electrically isolated as described below.

In FIG. 1, when the conductive material 105 is contacted with another conductive material 133 on the groove 132 opened on the substrate 100,
It also contacts the conductive material 103 'on the side wall of the groove and the Si substrate 100 itself. The following two methods are conceivable in order to separate this electrically or in a pattern.

First, the conductive material 103 'on the side wall of the groove is separated from other circuits in a pattern because it is always left on the side wall of the groove during the patterning process. Therefore, as shown in FIG. 1A, the area of the substrate 100 that is in contact with the contact hole 131 is filled with a groove so that it does not come into contact with the conductive material 103 of another circuit.

Next, at the contact portion between the conductive material 133 and the substrate 100, impurity implantation is performed to electrically separate them. It is necessary that the substrate 100 and the impurities to be implanted have the opposite conductivity type, and the relationship is the plate potential (V _PL ) to be given to the conductive material 105.
And the substrate potential (V _sub ). For example, V
_{If PL} > V _sub , a P-type substrate is used and N-type impurity implantation is performed. Even if the device uses N-type substrate,
It suffices to use a P-well to make only this portion P-type.
When V _PL <V _sub , the above N and P have an inverse relationship. Also
Only when V _PL = V _sub , it is not necessary to perform the impurity implantation of the conductivity type opposite to that of the substrate.

There are two possible methods for implanting impurities. For example, an N-type memory cell is formed using a P-type substrate, and V _PL > V
Consider the case of _sub . The step of forming the memory cell includes the step of bringing a part of the conductive material 103, which is a charge storage node, into contact with the substrate. At this time, N-type impurities are implanted into the contact portion between the conductive material 103 and the substrate. By using this step, the first method is to previously form an N-type diffusion layer in the contact portion with the conductive material 133 before opening the contact hole 131 on the groove 132. The cross-sectional view of the contact formation portion in FIG. 1 (b) is obtained by using this method.
Is a separation diffusion layer.

The second method is to open a contact in the groove and
After depositing 3 (eg polysilicon), conductive material 133
Is a method of injecting N-type impurities from above and permeating the impurities to the substrate by a heat treatment process.

The present invention is not limited to the above-mentioned embodiments, and various applications are possible. For example, it can be applied to the case where a capacitor is formed by the electrodes 103 and 105.

[Effects of the Invention] As described above, according to the present invention, the potential is applied to the conductive material completely filled in the groove without using the photo-etching process, and the manufacturing process is simplified. The cost can be reduced.

[Brief description of drawings]

FIG. 1 (a) is a pattern plan view of an essential part of one embodiment of the present invention, FIG. 1 (b) is a sectional view taken along the line CC 'of FIG. 1 (a), and FIG. A sectional view showing a possible electrode extraction method, FIG. 3 (a) is a pattern plan view of a conventional device, FIG. 3 (b) is a sectional view taken along the line AA 'in FIG. 3 (a), and FIG. (a) is a pattern plan view of another conventional device, and (b) is a sectional view taken along the line BB 'of (a). 100 …… P-type substrate, 101 …… thermal oxide film, 103,105 …… electrode, 104 …… insulating film, 109 …… insulating film, 131 …… contact part, 132 …… groove, 133 …… electrode, 134 …… Separation diffusion layer.

Continuation of front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display area H01L 21/90 D

Claims (5)

[Claims] 1. A groove for element formation formed on a semiconductor substrate of the first conductivity type, and a groove formed along the side wall of the groove that does not extend to the surface of the semiconductor substrate outside the groove and is insulated from the groove. The first conductive material, which is embedded in the groove of the first conductive material, does not extend to the surface of the semiconductor substrate outside the groove, and is insulated from the first conductive material and the groove. A second conductive material, a contact groove pattern having a region separated from the connection along the groove with respect to the first conductive material, a contact hole formed on the groove of the groove pattern, and the contact A third conductive material connected to the second conductive material through a hole, the semiconductor device. 2. The semiconductor device according to claim 1, wherein the contact hole is opened so as to include the semiconductor base portion outside the groove. 3. The second conductivity type semiconductor region is formed on the surface of the semiconductor substrate adjacent to the groove below the contact hole, and the second conductivity type semiconductor region is formed.
The semiconductor device according to the item. 4. The contact hole is opened so as to include the semiconductor substrate portion outside the groove, and the third conductive material is a substance containing a second conductivity type impurity. The semiconductor device according to item 1 or 3. 5. The groove pattern has a substantially sun-shaped plan shape, and the groove in the middle portion connecting one side and the other side of the sun-shaped pattern is connected to the extending side of the groove. The semiconductor device according to any one of claims 1 to 4.