JPH0798982A - Substrate bias circuit - Google Patents

Abstract

PURPOSE:To hold a substrate bias voltage to a fixed level by inserting corrent sources onto both sides of a transistor constituting an inverter constituting a delay circuit and controlling the currents of the current sources with threshold values. CONSTITUTION:When the threshold value of a P channel MOS transistor becomes larger due to the deviation, etc., in a device process, a voltage of a node 10 is made higher, and the currents flowing through the P channel MOS transistor Q4 and N channel MOS transistor Q3 are made larger, and a delay time is shortened. On the contrary, when the threshold value of the P channel MOS transistor becomes smaller, the current flowing through the N channel transistor Q3 constituting a delay inverter circuit 2a is made smaller, and the delay time is prolonged, and an output frequency of a ring oscillator 2 is reduced. In such a manner, by following a charge pump circuit by changing a frequency in response to the change in the threshold value of the transistor, fixed bias power is outputted always.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a substrate bias circuit, and more particularly to a substrate bias circuit for generating and supplying a constant bias voltage to a semiconductor substrate which constitutes a semiconductor memory circuit.

[0002]

2. Description of the Related Art In a semiconductor memory, a predetermined bias voltage is applied to a semiconductor substrate in order to improve its access speed and data retention characteristics. For example,
In a semiconductor memory using a P-type semiconductor substrate and a positive power supply voltage, a negative bias voltage is applied to the substrate. The substrate bias circuit is for generating such a bias voltage and applying it to the substrate, and is composed of an oscillation circuit for generating an oscillation signal of a predetermined frequency and a charge pump circuit for generating a substrate bias voltage based on the oscillation signal.

As an oscillation circuit, there is a ring oscillator in which a delay inverter circuit is connected on an odd-numbered stage ring because no external parts are required. The oscillation frequency of the ring oscillator depends on the delay time of each delay inverter circuit, and the delay time becomes shorter as the power supply voltage increases or the threshold value of the transistor forming the inverter becomes smaller than the design value. That is, the higher the power supply voltage and the lower the threshold voltage of the transistor, the deeper the gate-source bias of the transistor and the higher the current capability. As a result, the oscillation frequency becomes high. On the contrary, when the power supply voltage is low or the threshold voltage of the transistor is higher than the design value, the oscillation frequency is low. Since the substrate bias voltage depends on the frequency of the oscillation signal from the ring oscillator,
The substrate bias voltage will also change according to changes in the power supply voltage and / or changes in the threshold voltage of the transistor with respect to the design value. The change in the substrate bias voltage brings about a change in the effective threshold voltage in operation of each transistor constituting the memory circuit, and causes instability in the data access operation. In the worst case, it may cause an access malfunction and destroy store data.

Since the change of the oscillation frequency is caused by the change of the delay time of the delay inverter circuit, the delay time may be stabilized against the fluctuation of the power supply voltage. For this purpose, in Japanese Patent Laid-Open No. 60-222713, a current source is inserted in series with one of the transistors forming the delay inverter circuit, and the current of the current source is made constant so that the delay time is reduced to the power supply voltage. The delay inverter circuit is shown to be constant regardless of the fluctuation of Also. April 2, 1989
In the "CMOS VLSI design" issued by Baifukan on the 5th, current sources were added to both transistors of the COMS inverter in each delay inverter circuit, and the desired characteristics were given to the current of this current source. It is disclosed that the oscillation frequency can be controlled.

However, the substrate bias voltage depends not only on the oscillation frequency of the ring oscillator, but also on the current capability of the transistor forming the charge pump circuit. For example, even if the oscillation frequency of the ring oscillator is made constant by the method described above with respect to the increase in the power supply voltage, the current capacity of the transistor in the charge pump circuit increases as the power supply voltage increases, and as a result, the substrate bias voltage is It will change. Therefore, when the power supply voltage increases, it is necessary to reduce the oscillation frequency of the ring oscillator, conversely, to keep the substrate bias voltage constant. Further, when the threshold value of the transistor in the charge pump circuit becomes larger than the designed value due to the variation in the manufacturing process, the current capacity of the transistor becomes smaller accordingly. Therefore, in this case, it is necessary to increase the oscillation frequency of the ring oscillator to compensate for the reduced current capacity.

As described above, in order to make the substrate bias voltage constant, it is necessary to control the oscillation frequency of the ring oscillator depending on both the ring oscillator and the charge pump circuit. Such purpose is not realized.

Therefore, an object of the present invention is to provide a substrate bias circuit in which an output bias voltage does not fluctuate due to fluctuations in a power supply voltage and fluctuations in a threshold voltage of a transistor from a designed value.

[0007]

A substrate bias circuit of the present invention comprises a charge pump circuit which receives a drive pulse and which raises or lowers an output voltage in response to the drive pulse, and a ring oscillator which generates the drive pulse. It is characterized by having a ring oscillator in which odd-numbered stages of delay inverter circuits are connected in a ring shape, and a current control circuit for controlling a current flowing through each delay inverter circuit in this ring oscillator.

[0008]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a substrate bias circuit 100 according to one embodiment of the present invention. This circuit 100 is based on this circuit 10
A charge pump circuit 1 having an output 110 connected to a semiconductor substrate on which 0 is formed, and a ring oscillator 2 for supplying a drive pulse to the charge pump circuit 1 are provided. In this embodiment, the ring oscillator 2 has five stages of delay inverter circuits 2a, 2b, 2c, 2d and 2e, which are connected in a ring shape as shown in the figure. Each delay inverter circuit 2a,
The currents flowing in 2b, 2c, 2d and 2e are controlled by the current source circuit 3 described later.

The charge pump circuit 1 has a drive pulse input end 120 for receiving the oscillation signal from the ring oscillator 2 as a drive pulse. The drive pulse input end 120 is connected to the input of the inverter INV and one end of the capacitor C3. The output of the inverter INV is connected to one end of each of the capacitors C2 and C3. The other end of the capacitor C2 is connected to the gate of the P-channel MOS transistor Q11 and the node N1, and its drain / source path is connected between the substrate bias voltage output terminal 110 and the node N1. The back gate of the transistor Q11 is connected to the output of the inverter INV. The other end of the capacitor C4 is connected to the gate of the P-channel MOS transistor Q13, and its drain / source path is connected between the node N3 which is the other end of the capacitor C3 and the ground. The back gate of the transistor Q13 is the input terminal 120.
It is connected to the. Further, it has a P-channel MOS transistor Q14, the gate of which is grounded, and the drain / source path is connected between the other end of the capacitor C4 and ground. The back gate of the transistor Q14 is connected to the output of the inverter INV.

The driving pulse supplied to the driving pulse input terminal 120 includes a power supply voltage line (VDD) and a ground line (GN).
D) and the amplitude of the voltage difference. Drive pulse input terminal 12
When the drive pulse of 0 changes from VDD to GND, the level of the node N3 becomes V due to the coupling of the capacitor C3.
It is stepped down by DD, but the node N2 (input terminal 120) is VD
When it is D, the level of the node N3 is set to the GND level by the P-channel MOS transistor Q13 and the capacitor C4. Therefore, when the node N2 becomes GND, the level of the node N3 becomes -VDD level. Therefore,
The voltage applied to the gate of the P-channel MOS transistor Q12 becomes -VDD and becomes conductive, and the node N1
Is reduced to GND.

Next, when the level of the drive pulse input terminal 120 changes from GND to VDD, and thus the output of the inverter INV changes from VDD to GND, the node N1 is pulled down by VDD by the coupling of the capacitor C2 and becomes -VDD. Become. In this way, the P-channel MOS transistor Q11 becomes conductive, the potential of the substrate bias voltage output terminal 110 is pulled negative, and the voltage difference between the substrate bias voltage output terminal 110 and the node N1 becomes a P-channel MOS transistor.
It continues until the threshold voltage of the transistor Q11 becomes lower than the threshold voltage.

Then, the node N2 changes from VDD to GND, the node N1 becomes GND, and the P-channel MOS transistor Q11 becomes non-conductive.

As described above, the input drive pulse of the predetermined frequency is from VDD to GND and from GND to VDD.
The voltage of the substrate bias voltage output terminal 110 is pulled to a negative level each time it changes to, and becomes stable when it is pulled to a certain voltage.

Next, the ring oscillator 2 is constructed by connecting the delay inverter circuits 2a, 2b, 2c, 2d, 2e in a ring shape. Here, since each delay inverter circuit has the same configuration, only the delay inverter circuit 2a will be described.

In the delay inverter circuit 2a, the gates are commonly connected to the input terminal 10, and the P-channel MOS transistor Q1 and the N-channel MOS transistor Q2 are connected in series between the nodes N4 and N5 via the series connection point N6.
And an output end 20 to which the series connection point N6 is connected, and a capacitor C1 connected between the series connection point N6 and GND.
And a P-channel MOS transistor Q4 having a gate connected to the control terminal 30 and connected between VDD and the node N4.
And an N channel MOS transistor Q3 having a gate connected to the control terminal 40 and connected between the GND and the node N5. In the ring oscillator 2, the output terminal 20 of the delay inverter circuit at the previous stage is connected to the input terminal 10 and the output terminal 2 of the delay inverter circuit 2e at the final stage is connected.
0 is connected to the drive pulse input terminal 100 of the charge pump circuit 1 and the input terminal of the first stage via the output terminal 90 of the ring oscillator 2.

The delay time of the delay inverter circuit 2a changes depending on the amount of electric charge that charges the capacitor C1, that is, the amount of flowing current. However, the current flowing through the inverter formed by the P channel MOS transistor Q1 and the N channel MOS transistor Q2 is determined by the control voltage applied to the gates of the P channel MOS transistor Q4 and the N channel MOS transistor Q3. Therefore, by controlling the current flowing through the inverter to be constant, it is possible to supply a constant current even if the power supply voltage changes.
The delay time can be controlled. Power supply voltage is VDD1
2A showing the input signal IN supplied to the input terminal 10 of the delay inverter circuit, the output signal OUT output from the output terminal 20 and the delay time when the delay inverter circuit is operated in accordance with FIG. When the input signal IN to be changed from GND to VDD, the N-channel MOS transistor Q2 changes from the OFF state to the ON state, and the P-channel M
The OS transistor Q1 changes from the on state to the off state. Therefore, the potential of the series connection point N6 changes from VDD to GN.
Gradually change to D. Therefore, the potential at the series connection point N6 changes from VDD to GND. Where N channel M
When the current constant of the OS transistor Q3 and the P-channel MOS transistor Q4 is I and the total capacitance of the series connection point N6 is the sum C of the capacitor C1 and the parasitic capacitance, the potential change speed of the series connection point N6 is dV / dt = Since it can be expressed as I · (1 / C) ···, the current constant I and the total capacitance C are the power supply voltage V
Since it does not depend on the fluctuation of DD, the potential change speed of the series connection point N6 is constant. Therefore, the time required when the potential of the series connection point N6 changes from VDD to GND is
Since the amplitude is directly proportional to the power supply voltage VDD,
The delay time T1 from the input signal IN to the output signal OUT is directly proportional to the power supply voltage VDD. The input signal IN is G
Even when changing from ND to VDD, the delay time is directly proportional to the power supply voltage VDD1 because the absolute value of dV / dt is constant.

Power supply voltage VD lower than power supply voltage VDD1
Referring to FIG. 2B showing the waveform diagram when operated at D2, the speed of potential change dV / dt is equal to that of FIG. 2A, and the voltage amplitude of the series connection point N6 is small in FIG. It can be seen that the delay time of () is shorter than that of FIG.

Therefore, as shown in FIG. 2C, the delay inverter circuit 2a is directly proportional to the power supply voltage VDD.
It can be seen that the delay time is increased.

The current source circuit 3 includes a P-channel MOS transistor Q8 connected between VDD and the node N7, and an N-channel MOS transistor Q5 whose gate is connected to the node N7 and connected between the node N7 and GND. And node 7
An N-channel MOS transistor Q6 whose gate is connected to the output terminal 60 and the output terminal 60, and which is connected between the node N8 and GND.
And a P-channel MOS transistor Q7 having a gate connected to the output terminal 50 and connected between the node N8 and VDD. The output terminal 50 has the delay inverter circuit 2
a, 2b, 2c, 2d, 2e are connected to the input ends 30,
The output end 60 is likewise connected to the input end 40. here,
N-channel MOS transistor Q5 and N-channel MOS
Since transistor Q6 constitutes a current mirror circuit, the current flowing through N-channel MOS transistor Q6 is determined by N-channel MOS transistor Q5, and the current flowing through N-channel MOS transistor Q5 is determined by the current flowing through P-channel MOS transistor Q8. To be done. This P channel MOS transistor Q8
The current flowing through the gate is determined by the gate-source voltage. The P-channel MOS transistor Q4 and the P-channel MOS transistor Q7 in the delay inverter circuit 2a form a current mirror circuit, and the N-channel MOS transistor Q3 and the N-channel MOS transistor Q6 in the delay inverter circuit 2a form a current mirror circuit. Since the mirror circuit is configured, the current flowing through all the delay inverter circuits 2a, 2b, 2c, 2d, 2e is
It is determined by the current flowing through P channel MOS transistor Q8. In this embodiment, the input / output current ratio of all the current mirror circuits is 1. Therefore, the currents flowing through all the delay inverter circuits 2a, 2b, 2c, 2d, 2e are the same.

The current source circuit 3 further includes a P-channel MOS transistor Q9 having a gate connected to the node N9 and connected between VDD and the node N9, and a gate having a node N10.
P connected to node N9 and node N10
Channel MOS transistor Q10, nodes N10 and G
And a resistor R1 connected to ND. Node N1
0 is connected to the gate of the transistor Q8.

If the threshold value of each P-channel MOS transistor is Vtp, the voltage at the node N10 is VDD-2.
-| Vtp | (where | Vtp | represents the absolute value of Vtp), and the voltage is supplied to the gate of the P-channel MOS transistor Q8. Therefore, P channel M
The voltage applied between the gate and the source of the OS transistor Q8 is 2Vtp. Here, the current flowing through the transistor Q8 is determined by the voltage applied between the gate and the source, and the voltage that depends only on the threshold voltage Vtp of the P channel MOS transistor is applied between the gate and the source. The current flowing through the transistor Q8 depends only on Vtp and not on VDD.

That is, assuming that the conductance constant of the P-channel MOS transistor Q8 is β, the P-channel M
The current constant IQ8 of the OS transistor can be expressed as IQ8 = (1/2) .beta..multidot. (2 | Vtp |-| Vtp |) ^ 2 = (1/2) .beta. | Vtp | ^ 2 ... (However, ^ is a symbol representing exponentiation.)
Further, as described above, since the delay time of the delay inverter circuit is inversely proportional to the current, the delay time T with respect to the threshold voltage Vtp can be expressed as T = 1 / | Vtp | ^ 2 ...

Therefore, when the relationship between the absolute value of the threshold voltage Vtp and the delay time T is shown based on the above equation, the graph of FIG. 3 is obtained. That is, the threshold of the transistor is | Vt
When it is low as p1 |, the delay time T becomes long as T1, and when it is high as | Vtp2 |, the delay time T becomes short as T2. Therefore, the transistor Q1
1 and the capacity of the transistor Q12 becomes low, that is, when the threshold value of the P-channel MOS transistor becomes large due to variations in the device process or the like, the voltage at the node 10 is increased to form the delay inverter circuit 2a.
Channel MOS transistor Q4 and N channel MOS
When the current flowing through the transistor Q3 is increased to shorten the delay time, the output frequency of the ring oscillator 2 is increased, and when the threshold value of the P-channel MOS transistor is decreased, the P-channel M which constitutes the delay inverter circuit 2a is formed.
The current flowing through the OS transistor Q4 and the N-channel MOS transistor Q3 is reduced to lengthen the delay time and lower the output frequency of the ring oscillator 2. Therefore, the capacity of the charge pump circuit 1 changes depending on the frequency of the drive pulse. When the frequency is high, the capacity is high, and when the frequency is low, the capacity is low. As described above, even when the threshold value of the transistor changes, the capacity of the charge pump circuit is made to follow by changing the frequency in response to the change, so that a constant bias voltage can be always output.

Next, a second embodiment of the invention will be described with reference to FIG.

The substrate bias circuit shown in FIG. 4 comprises a charge pump circuit 11, a ring oscillator 2 for supplying a drive pulse to the charge pump circuit 11, and a current control circuit 13 for controlling the current flowing in the ring oscillator 2. It Since the ring oscillator 2 is the same as that shown in FIG. 1, its explanation is omitted. The charge pump circuit 11 has an N-channel MOS transistor Q15 whose gate is connected to the substrate bias voltage output terminal 110 and whose source / drain are connected between the substrate bias voltage output terminal 110 and the node N11.
And an N-channel MO whose gate is connected to the node N11 and whose source / drain are connected between the node N11 and GND.
S-transistor Q16 and input is drive pulse input terminal 10
Inverter INV connected to 0 and inverter INV
C5 connected between the output of node and node N11
Composed of and.

In the charge pump circuit 11, when the drive pulse input terminal 100 is GND, the node N11 is increased from VDD raised by the coupling of the capacitor C5 by the diode N channel MOS transistor Q16.
The voltage of the substrate bias voltage output terminal 110 is pulled to a negative level by pulling it down to ND and lowering the voltage of the node N11 from GND by VDD by the coupling of the capacitor C5 when the drive pulse input terminal 100 changes from GND to VDD. ing. Since the charge pump circuit 11 uses the N-channel MOS transistor, the N-channel MOS transistor based on the change from the design value of the threshold value Vtn of the transistor due to variations in manufacturing process or the like.
In order to suppress the change in the capacity of the charge pump circuit 11 due to the change in the capacity of the transistors Q15 and Q16, it is necessary to change the frequency of the drive pulse output from the ring oscillator 2 by the threshold value Vtn as in FIG.

For this purpose, the current control circuit 13 of this embodiment is composed of a resistor R11, four N-channel MOS transistors Q20 to Q23, and two P-channel MOS transistors Q24 and Q25, as shown in the figure. It is connected. In particular, the current flowing through the transistor Q22 depends only on the threshold voltage of the N-channel MOS transistor, and this current passes through the current mirror circuit of the transistors Q24 and Q4, the current mirror circuit of the transistors Q24 and Q25, and the current mirror circuit of Q23 and Q3. , The currents flowing through the delay inverter circuits are all the same. Thus, also in the present embodiment, a constant substrate bias voltage can be obtained.

In FIG. 1, the same effect can be obtained by changing the conductivity type of the transistor, making VDD and GND opposite to each other, and connecting the charge pump circuit 11 instead of the charge pump circuit 1 to the output terminal 90. . Also, diode-connected transistors Q9, Q10 or Q20,
Q21 may increase that location.

[0030]

As described above, the absolute value of the threshold voltage is low by inserting the current source at both ends of the transistor of the inverter configuration which constitutes the delay inverter circuit and controlling the current of the current source by the threshold value. Sometimes the current is reduced to increase the delay time, and the output terminal of the inverter is charged and discharged by the current of the current source, so the potential change rate at the output terminal is constant regardless of the fluctuation of the power supply voltage. Yes, the higher the power supply voltage, the larger the amplitude of the output voltage, so the frequency of the drive pulse output by the ring oscillator can be lowered. Conversely, when the absolute value of the threshold voltage is high, the current is increased to increase the delay time. Since the amplitude of the output voltage increases as the power supply voltage decreases, the frequency of the drive pulse output from the ring oscillator can be increased. Kill. Therefore, when the capacity of the charge pump circuit becomes high, that is, when the power supply voltage becomes high or the absolute value of the threshold becomes low, the frequency of the drive pulse is lowered so as to suppress the capacity of the charge pump circuit. Of the substrate bias voltage generating circuit by increasing the frequency of the drive pulse so as to improve the capacity of the charge pump circuit when the capacity of the charge pump circuit is low, that is, when the power supply voltage is low or the absolute value of the threshold value is high. The substrate bias voltage output by can be held constant.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a substrate bias voltage generating circuit showing a first embodiment of the present invention.

FIG. 2A is a graph showing the delay time of the delay inverter circuit when the power supply voltage is high in the first embodiment of the present invention. (B) A graph showing the delay time of the delay inverter circuit when the power supply voltage is low in the first embodiment of the present invention. (C) A graph showing the relationship between the power supply voltage and the delay time of the delay inverter circuit in the first embodiment of the present invention.

FIG. 3 is a graph showing the relationship between the threshold voltage of the transistor and the delay time of the delay inverter circuit in the first embodiment of the present invention.

FIG. 4 is a circuit diagram of a substrate bias voltage generating circuit showing a second embodiment of the present invention.

[Explanation of symbols]

Q1, Q3, Q5, Q6, Q15, Q16, Q17 N
Channel MOS transistors Q2, Q4, Q7, Q8, Q9, Q10, Q11, Q1
2, Q13, Q14 P-channel MOS transistors C1, C2, C3, C4, C5 capacitors

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H03K 3/354 A 5/13

Claims (5)

[Claims] 1. A charge pump circuit which receives a drive pulse and which raises or lowers an output voltage in response to the drive pulse, and a ring oscillator which generates the drive pulse, wherein a delay inverter circuit of an odd number of stages has a ring shape. 1. A substrate bias circuit, comprising: a ring oscillator connected to each other; and a current control circuit that controls a current flowing through each delay inverter circuit in the ring oscillator. 2. Each of the delay inverter circuits has a first channel type first gate whose gate is connected to a first control terminal and is connected between the first power supply line and a first node. A transistor; a gate connected to the input end; connected between the first node and the second node; the second transistor of the first channel type; and a gate connected to the input end Between a third transistor of the second channel type connected between the second node and the third node, and between the third node whose gate is connected to the second control end and the second power supply line. 2. The substrate bias circuit according to claim 1, further comprising a second transistor of the second channel type connected to the. 3. The first channel type fifth transistor having a gate connected to the first control end and connected between the first power supply line and the first control end in the current control circuit. A second channel type sixth transistor having a gate connected to the second control terminal and connected between the first control terminal and the second power supply line; and a gate having the second transistor. The second channel type seventh transistor connected to the second control end and the second power supply line, and the gate connected to the third control end. A second channel-type eighth transistor connected between the second control end and the first power supply line; and means for applying a bias voltage to the third control end. The substrate bias circuit according to claim 2. 4. The charge pump circuit includes the fourth node connected between a fourth node that operates as a diode and outputs a bias voltage to an output end when the drive pulse is at a first level, and the output end. A one-channel output transistor, a diode operation when the drive pulse is at the second level, and the fourth node connecting the fourth node to the second power line; and the second power line. The substrate bias circuit according to claim 3, wherein the substrate bias circuit is configured by the restore transistor of the first channel connected in between. 5. The bias voltage applying means has a fifth gate.
The first channel type ninth transistor connected to the node of the first power supply line and connected between the first power supply line and the fifth node, and the gate connected to the third control end of the fifth transistor. A tenth transistor of the first channel connected between the node and the third control end, and a resistive element connected to the third control end and the second power supply line. The substrate bias circuit according to claim 4, further comprising: