JPH08102728A - Receiver - Google Patents

Abstract

PURPOSE: To reproduce the received data on an optional time base by transmitting a control signal to the transmission side in response to the detection result of an occupied variable of a storage means and also generating a read clock signal by a read clock generation means. CONSTITUTION: When a buffer part 1 is set in an enable state by a write clock signal WCK received from a transmission device 4 the part 1 stores the supplied data. Then the part 1 supplies a half flag, for example, to a CPU 3 as the information on a memory area to be occupied. The CPU 3 shows the quantity of data supplied from the transmission side as an occupation rate against an entire memory area based on the half flag received from the part 1 and monitors this occupation rate. When the data written in the CPU 3 exceed a prescribed occupation rate, the transmission of the device 4 is discontinued. Then a request signal REQ is sent to the device 4 for request or transmission of the data written in the CPU 3 is kept less than the prescribed occupation rate. An external synchronizing signal is inputted to a read clock generation part 2, and a read clock RCK synchronizing with the external synchronizing signal is supplied to the part 1. Thus the part 1 reads out its stored data and outputs them.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a receiving apparatus for receiving input data supplied from a transmitting side, and more particularly to a receiving apparatus suitable for time axis control when reading data from a buffer on the receiving side. .

[0002]

2. Description of the Related Art Generally, a reproducing apparatus reproduces data by making one reproduction time axis correspond to one recording medium. An example of such a reproducing device is a video reproducing device that irradiates a laser beam to reproduce the information recorded on the optical disc 30. Such a video reproducing device, for example, as shown in FIG. 8, optically / electrically converts the returned light of the irradiated laser light and supplies the signal-processed reproduced RF signal to the demodulation unit 31.

The demodulation unit 31 outputs the output signal to the video reproduction unit 32.
Supply to. The video reproduction unit 32 outputs the reproduction video signal and outputs the horizontal synchronization signal (PB-H-Syn) of the reproduction video signal.
c) is supplied to one end of the phase comparator 33. Also,
The phase comparator 33 is supplied to the other end side with a reference horizontal synchronization signal (REF-H-Sync) generated by a crystal oscillator 34 provided inside a video reproducing apparatus using this optical disk.

The phase comparator 33 includes a spindle motor 35.
Is supplied with a control signal based on the result of the phase comparison. This control signal is a signal that makes the difference between the phase of the horizontal synchronizing signal of the reproduced video signal and the reference horizontal synchronizing signal zero.
The spindle motor 35 controls the rotation of the optical disc 30 according to the supplied control signal.

If a reference synchronizing signal is supplied from the outside instead of the built-in crystal oscillator 34, the horizontal synchronizing signal of the reproduced video signal can be synchronized with the external synchronizing signal. In the video reproducing device, a demodulation unit 31, a video reproducing unit 32, a phase comparator 33 and a crystal oscillator 34 with respect to the spindle motor 35 constitute a phase locked loop circuit, a so-called PLL circuit.

In the disk-shaped recording medium using other light or magneto-optical property, the reproducing apparatus controls the rotation of the optical disk 30 by comparing the reference clock with the reproducing clock. In the video reproducing apparatus, the rotation speed control of the optical disk 30 by the spindle motor 35 cannot be performed with a signal of a time much shorter than the rotation time of the spindle motor 35. That is, this rotation control cannot be performed with a high-frequency component signal, and time axis control cannot be performed.

[0007] Actually, a video reproducing apparatus is, for example, 15.734kHz.
Although the rotation speed can be controlled up to the frequency near the horizontal sync signal of, the time base collector (T
BC) is required. Further, in a transmission / reception system in which one or a plurality of transmission data are provided with one or a plurality of receivers, the transmission data is reproduced based on time axis information supplied accompanying the transmission data. Therefore, each receiver reproduces the transmission data on the time axis of each transmitter.

As a specific example in this case, an international standard moving picture for reproducing a video signal, an audio signal, etc. by high efficiency coding data compression is reproduced.
Image Expert Group 2 (Moving Picture)
There is a transmission / reception system using the standard of Image Coding Experts Group 2: MPEG2. On the transmission side of this system, the output from the MPEG encoding unit 40A that performs data compression based on the MPEG2 standard is supplied to the multiplexer unit 40B, and the data is output from the multiplexer unit 40B to the reception side. MP above
The EG encoder 40A operates according to the clock supplied from the transmitter system clock reference generator 40C.

The system clock reference generator 40C on the transmitting side generates a clock of, for example, 27 MHz from the output of the crystal oscillator 40D in accordance with the timing of the A / D clock of the audio / video signal. Generally, in such a system, a transport layer is provided to enable uniform data transfer regardless of the communication network used.

The transport layer is provided with a program clock reference generating section (hereinafter referred to as a PCR section) 40E which specifically generates system clock information. The PCR unit 40E uses the PCR as information for preventing audio / video signal synchronization and buffer overflow / underflow.
Supply to 0B.

On the receiving side, the demultiplexer unit 4
1A receives the data supplied from the transmission side. The demultiplexer unit 41A separates the PCR and the compressed data from the received data and supplies them to the MPEG decoding unit 41B and the receiving side system clock reference generating unit 41C, respectively. The reception side system clock reference generation unit 41C is a PC supplied from the transmission side.
The system clock information having the same timing as that of the transmitting side is generated according to R and is supplied to the MPEG decoding unit 41B.

The MPEG decoding unit 41B expands and demodulates the compressed data based on the supplied system clock information, so that the MPEG encoding unit 40A on the transmitting side has the same time relationship as that of the operating time, that is, The transmitted signals are reproduced with the time axes of the transmitting side and the receiving side aligned. In such a system, one type of PCR can be added to one type of system clock, so the transmission lines of multiple encoding and decoding parts can be shared, and only one transmission line is required. it can.

[0013]

By the way, in the case of the reproducing apparatus described above, the reproducing apparatus controls the output speed of the reproduced data by changing the rotational speed of the disk-shaped recording medium based on the phase difference. Has been done. For this reason,
The playback device can support only one type of output, that is, one channel.

Further, if all the plurality of data outputs are synchronized and reproduced, only one data output speed can be used. However, this reproducing apparatus cannot output a plurality of channel outputs at different synchronization timings. Next, the above-mentioned M
In the system using PEG2, the PCR unit 40E must accurately transmit the information of the system clock in order to reproduce the transmission data by matching the time axes of both sides of the transmission and reception sides.

However, there is a possibility that information such as PCR may not be supplied in the middle of the transmission path. In order to match the time axis, the transmission line must be devised so that data interruption does not occur. Even when applied to a multi-channel reproducing apparatus using a plurality of recording media, such a problem requires a device for exactly matching the PCR of the recording system and the PCR of the reproducing system.

Further, with such a configuration, data reproduction on the receiving side and the reproducing side cannot be performed in synchronization with, for example, external synchronization. That is, this means that the time axis on the receiving side or the reproducing side cannot be arbitrarily set. Therefore, the present invention has been made in view of the above-mentioned circumstances, and receives data recorded corresponding to one or more time axes and reproduces the received data on an arbitrary time axis. It is an object of the present invention to provide a receiving device capable of

[0017]

A receiving apparatus according to the present invention is, in a receiving apparatus for receiving input data supplied from a transmitting side, an input buffer section for storing the input data,
A CPU that detects the occupied amount of the input buffer unit and a CPU that sends a control signal according to the detection result of the CPU to the transmission side
And a read clock generation unit that generates a data read clock signal from the input buffer unit.

Here, the read clock generator can have a plurality of configurations. The first read clock generation unit supplies a system clock reference generation unit that generates a system clock reference, a frequency division unit that divides the output from the system clock reference generation unit, and a synchronization signal that is internally generated and externally supplied. A changeover switch that changes the synchronized signal that is generated, a phase comparator that compares the phase between the reference synchronization signal from the changeover switch and the system synchronization signal from the frequency divider, and a system clock reference according to the output from the phase comparator. A read clock output unit that outputs a clock signal for reading data from the input buffer unit based on the signal output by the generation unit.

The second read clock generation section is a synchronization separation section for synchronously separating a video signal obtained by demodulating the data from the input buffer section, a synchronization signal generated internally and a synchronization signal supplied from the outside. , And a phase comparator that compares the phase of the reference synchronization signal from the changeover switch and the signal from the sync separation unit, and a system clock reference that generates a system clock reference according to the output from the phase comparator. It is composed of a generation unit and a read clock output unit that outputs a clock signal for reading data from the input buffer unit based on the output signal of the system clock reference generation unit.

The third read clock generation section demodulates the system clock reference generation section for generating the system clock reference, the frequency division section for dividing the output from the system clock reference generation section, and the data from the input buffer section. A sync separation section for synchronously separating the video signal obtained by the above; a first changeover switch for switching between a sync signal internally generated and a sync signal externally supplied;
A second changeover switch for switching between the output from the frequency division unit and the output from the synchronization separation unit, and phase comparison based on signals respectively supplied from the first changeover switch and the second changeover switch to generate a system clock reference. And a read clock output unit for outputting a clock signal for reading data from the input buffer unit based on the output signal of the system clock reference generation unit.

The fourth read clock generation section includes a reproduction clock generation section for generating a reproduction clock based on the system clock information obtained from the transport layer,
An external phase lock unit for locking the phase of a synchronization signal supplied from the outside, a changeover switch for switching between the output of the external phase lock unit and the output of an oscillator for generating an internal clock, and a regenerated clock generation unit, A phase comparator that performs phase comparison based on the signals respectively supplied from the changeover switch, a system clock reference generation unit that generates a system clock reference according to the output from the phase comparator, and an output signal of the system clock reference generation unit And a read clock output section for outputting a clock signal for reading data from the input buffer section based on the above.

Further, the read clock generating section is composed of a sync separating section for synchronously separating a video signal obtained by demodulating the data from the input buffer section, and an output from the sync separating section and a sync signal supplied from the outside. A first phase comparator for phase comparison, a regenerated clock generation unit for generating a regenerated clock based on system clock information obtained from the transport layer, and a process for locking the phase to a synchronization signal supplied from the outside. A phase lock unit, a changeover switch for switching between an output of the external phase lock unit and an output of an oscillator for generating an internal clock, and a phase comparison based on signals respectively supplied from the regenerated clock generation unit and the changeover switch. Second phase comparator, first phase comparator and second phase comparator
System clock reference generation unit that generates a system clock reference based on the output from the phase comparator, and a read clock output unit that outputs a clock signal for reading data from the input buffer unit based on the output signal of the system clock reference generation unit It consists of and.

[0023]

The receiving apparatus according to the present invention detects the operation of the input buffer section based on the occupancy of the input buffer section, sends a control signal corresponding to the detection result to the transmitting side, and outputs from the read clock generating section. By reading the data from the input buffer section based on the clock signal for reading the data, the time relationship between the system clock of the encoder on the transmitting side and the input video signal can be obtained. Reproduce accurately with the signal.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the receiving apparatus according to the present invention will be described below with reference to the drawings. In this example,
The configuration in the decoder used in this receiving device will be described.

The receiving apparatus is provided with a time adjusting unit 10 having a basic structure as shown in FIG. 1 in a decoder. The decoder includes an input buffer unit 1 for storing data from the transmission side, a read clock generating unit 2 for generating a clock signal for reading data from the input buffer unit 1, and a data occupancy rate of the input buffer unit 1. Then
It has a CPU 3 that outputs a control signal for controlling the output to the transmission device 4 in accordance with the monitoring result.

The read clock generating section 2 in this receiving apparatus can have various configurations. Further, detailed configurations of these will be described later. This receiver is
The data from the transmitter 4 is supplied to the input buffer unit 1 as input data. The transmitter 4 also supplies the write clock signal WCK to the input buffer unit 1.

The input buffer unit 1 internally receives the supplied data when it is enabled by the write clock signal WCK. The input buffer unit 1 is
A half flag, for example, is supplied to the CPU 3 as information regarding the occupied memory area. The CPU 3 monitors the amount of data supplied from the transmitting side with respect to the entire memory area by occupying it based on the information from the input buffer unit 1 and the half flag. For example, when the written data exceeds a predetermined occupancy rate, the CPU 3 causes the transmission apparatus 4 to stop the transmission, and transmits a request signal REQ requesting data transmission under the occupancy rate lower than this occupancy rate. It is output to 4.

An external synchronizing signal supplied from the outside, for example, is supplied to the read clock generating section 2 of this receiving device. The read clock generation unit 2 supplies the read clock signal RCK synchronized with the external synchronization signal to the input buffer unit 1. The input buffer unit 1 outputs the data stored therein according to the read clock signal RCK.
The output data accurately reproduces the time relationship between the system clock of the encoder (not shown) in the transmitter 4 and the input data between the system clock in the decoder on the receiving side and the external synchronization signal.

Further, such a time relationship is obtained by using the horizontal synchronizing signal of the video signal reproduced from the output data of FIG. 1 instead of the external synchronizing signal, and the time between the system clock on the transmitting side and the input data. The relationship can be reproduced on the receiving device. An example in which the receiving device of the present invention is applied to the receiving section of the multi-channel video transmission system shown in FIG. Here, in this multi-channel video transmission system, the MPEG standard, which is one of the standards used for data compression, is used.

The multi-channel video transmission system is
The reception unit 22 that multiplexes the video data of a plurality of channels
And a receiver 22 that reproduces a signal by separating the multiplexed video data from the transmitter 21 for each channel. The transmission unit 21 stores, for example, hard disk devices HD _{1 to} HD _n as a plurality of storage devices that store video data, and outputs M from the hard disk devices HD _{1 to} HD _n , for example.
A signal processing unit 21 for performing data compression based on the PEG2 standard
a and a multiplexer unit 21b that multiplexes output signals from the signal processing unit 21a.

The multiplexer section 21b supplies the output signal as data from the transmitting side to the receiving section 22 via the transmission line 23. Receiver 22, a demultiplexer unit 22a for separating the multiplexed data, for example, every channel from the transmitting unit 21, decoding unit DC ₁ to decoding processing in response to the output from the demultiplexer 22a to DC
have _n and.

Each of the decoding units DC _{1 to} DC _n returns a request signal with the data supply from the transmitting unit 21 as a request signal for each channel and performs transmission control, while transmitting a video signal and an audio signal corresponding to each channel. Each is output. The decoding units DC _{1 to} DC _n are provided with the time adjusting unit 10 shown in FIG. 1 in order to reproduce the time relationship on the transmitting side with an arbitrary time relationship that the receiving unit 22 has. An external synchronizing signal is supplied to the time adjustment unit 10 as a signal for time adjustment corresponding to, for example, the transport layer on the receiving side.

Next, various specific examples of the configuration of the decoder section in the receiving section 22 and modifications of the specific examples will be described with reference to FIGS. 3 to 7. Here, the same parts as those in FIG. Further, as a concrete example, the decoding unit DC ₁ will be taken as an example. MP is applied to the decoding unit DC _1.
EG system demux unit 22A, MPEG video decoding unit 22B, MPEG audio decoding unit 22C
In addition to the above, the time adjustment unit 10 corresponding to the transport layer is provided.

In the decoding unit DC ₁ , the input buffer unit 1
To the MPEG system demux unit 22A in response to a read clock signal RCK from a read clock generation unit 2 which will be described later. MPEG system demux unit 22A
Is supplied to the MPEG video decoding unit 22B and the MPEG audio decoding unit 22C after being separated into video data and audio data. The MPEG video decoding unit 22B outputs the video signal by subjecting the video data compressed by the MPEG standard to data expansion processing and the like. Further, the MPEG audio decoding unit 22C is
Data expansion processing or the like is performed on audio data compressed according to the MPEG standard, and left and right audio signals (L) and audio signals (R) are output.

The time adjusting section 10 in the decoding section is composed of an input buffer section 1, a read clock generating section 2 and a CPU 3, as shown in FIG. Among them, the read clock generator 2 includes a system clock reference generator 201 that generates a system clock reference SCR, a frequency divider 202 that divides the output from the system clock reference generator 201,
A changeover switch SW1 for changing over a synchronization signal generated internally and a synchronization signal supplied from the outside, and a phase comparator 203 for comparing the phases of a reference synchronization signal from the changeover switch SW1 and a system synchronization signal from a frequency divider. And a read clock output unit 204 that outputs a clock signal for reading data from the input buffer unit 1 based on the signal output from the system clock reference generation unit 201 according to the output from the phase comparator 203.

An external video signal is externally supplied to the read clock generation unit 2 to the external synchronization input unit 205. The external synchronization input unit 205 supplies the horizontal synchronization signal of the external video signal, that is, the external synchronization signal EX-H to one end side of the changeover switch SW1. An internal synchronization signal from the internal synchronization generator 206 is supplied to the other end of the changeover switch SW1. Changeover switch SW1
The phase comparator 20 uses either the time relationship of the receiving unit 22 or the external time relationship as the reference synchronization signal REF-H.
3 is being supplied.

At the other end of the phase comparator 203, for example, a synchronization signal SCR-H based on the system clock reference SCR obtained by dividing the system clock reference SCR of 27 MHz output from the system clock reference generator 201 is provided. Is being supplied. In order to divide the system clock reference SCR, the system clock reference generator 201 supplies the system clock reference SCR to the divider 202. Divider 202
Set the system clock reference SCR to 1/14
The synchronization signal SCR-H based on the system clock reference SCR is obtained by dividing the frequency in 3 stages, 3, 1/6, and 1/2. Due to this frequency division, the synchronization signal SCR-H is, for example, NTS.
Corresponding to the case of the C method, if the frequency 27 MHz of the system clock reference SCR is set to 1/1716, the pulse of the horizontal synchronizing signal can be generated.

The phase comparator 203 supplies the output signal corresponding to the difference between the synchronization signal SCR-H and the reference synchronization signal REF-H based on the system clock reference SCR to the system clock reference generator 201. When the reference synchronization signal is the external synchronization signal, the read clock signal RCK corresponding to the external synchronization signal is output. In this way, the phase comparator 203 causes the system clock reference SCR of the system clock reference generator 201 to
To form a PLL circuit.

System clock reference generator 20
1 is a voltage controlled oscillator (hereinafter referred to as VCO) that oscillates a clock frequency of 27 MHz according to the MPEG2 standard, for example.
That is). The system clock reference generation unit 201 performs phase control with the output from the phase comparator 203 to synchronize the system clock reference SCR with the external synchronization signal. In this way, the system clock reference SCR synchronized with the external synchronization signal is supplied to the read clock output unit 204. The read clock output unit 204 supplies the read clock signal RCK to the input buffer unit 1 based on the system clock reference SCR synchronized with the external synchronization signal.

Therefore, the input buffer unit 1 comes to output the output data at the timing depending on the external synchronization as described above. With such a configuration, the time relationship between the system clock and the input data in the encoding unit (not shown) in the signal processing unit 21a on the transmission side is the same as the system clock on the reception side and the external synchronization signal. It will be accurately reproduced with the signal.

In this case, the relationship between the video signal actually output and the external synchronizing signal is not monitored. Therefore, the decoding unit DC ₁ does not have a feedback function of correcting even if the time axis is deviated for some reason. Next, there is a configuration of the read clock generation unit 2 shown in FIG. 4 as a first modification of the specific example described above. Here, also in this case, common portions are given the same reference numerals, and description thereof will be omitted.

The read clock generating section 2 in the first modification has a sync separating section 207 for synchronously separating a video signal obtained by demodulating the data from the input buffer section 1,
The phase of the changeover switch SW2 for changing over the internally generated sync signal and the externally supplied sync signal is compared with the reference sync signal REF-H from the changeover switch SW2 and the signal PB-H from the sync separation unit 207. A phase comparator 203 for
A system clock reference generation unit 201 that generates a system clock reference SCR according to the output from the phase comparator 203, and a clock signal that reads data from the input buffer unit 1 based on the output signal of the system clock reference generation unit 201 are output. It is composed of the read clock output unit 204.

A synchronization signal SCR-H based on the system clock reference SCR performed in the above-described specific embodiment.
Was compared with the reference synchronization signal REF-H in phase, but in the first modification, the reception unit 22 has a phase relative to the reproduction horizontal synchronization signal PB-H obtained from the video signal reproduced by the MPEG video decoding unit 22B. The system clock reference SCR output from the system clock reference generation unit 201 is compared and controlled.

Therefore, the MPEG video decoding unit 22B
Outputs the reproduced video signal as it is and also sends the video signal to the sync separation unit 207. The sync separator 207 separates the reproduced horizontal sync signal PB-H from the supplied video signal and supplies it to the phase comparator 203.
The phase comparator 203 supplies, as a control signal to the system clock reference generation unit 201, a difference in phase comparison between the reference synchronization signal REF-H output from the changeover switch SW2 and the reproduction horizontal synchronization signal PB-H. .

The changeover switch SW2 is the external synchronization input section 20.
When the output from 5, that is, the external synchronization signal EX-H is selected, the system clock reference generation unit 201
When the phase comparator 203 uses the external synchronization signal EX-H as a reference synchronization signal, the system clock reference SC
R will be adjusted to match the phase relationship of the external synchronization signal EX-H. Also, by using the playback horizontal synchronization signal PB-H as the signal for phase comparison, the phase relationship is adjusted with the output video signal, and the system clock reference SCR is controlled so that the phases match. .

With this configuration, the time relationship between the system clock and the input data in the encoder (not shown) in the signal processing unit 21a on the transmitting side is the same as that on the receiving side. It will be accurately reproduced with the output video signal. In this case, it is possible to strengthen the connection of the time relationship with the video signal to be output, as compared with the specific embodiment described above.

Next, as a second modification of the above-mentioned specific example, there is a configuration of the read clock generating section 2 shown in FIG. Here, also in this case, common portions are given the same reference numerals, and description thereof will be omitted. The read clock generation unit 2 in the second modification includes a system clock reference generation unit 201 that generates a system clock reference, a frequency division unit 202 that divides the output from the system clock reference generation unit 201, and an input buffer. A sync separation unit 207 that synchronously separates a video signal obtained by demodulating the data from the unit 1, a changeover switch SW1 that switches a synchronization signal generated internally and a synchronization signal supplied from the outside, and a frequency dividing unit 202. Switch SW2 for switching the output from the switch and the output from the sync separation unit 207, and a switch SW
1 and a phase comparator 203 for phase comparison based on signals supplied from the changeover switch SW, and a read clock output unit for outputting a clock signal for reading data from the input buffer unit based on the output signal of the system clock reference generation unit 201. And 204.

This structure is a combination of the specific embodiment described above and the first modification. With such a configuration, the time relationship between the system clock and the input data in the encoding unit (not shown) in the signal processing unit 21a on the transmission side is the same as the system clock on the reception side and the external synchronization signal. It can be accurately reproduced with the signal.

Next, there is a configuration of the read clock generating section 2 shown in FIG. 6 as a third modification of the above-mentioned specific example. Here, also in this case, common portions are given the same reference numerals, and description thereof will be omitted. The read clock generation unit 2 in the third modified example sets the phase of the reproduction clock generation unit 208 that generates a reproduction clock based on the system clock information PCR obtained from the transport layer and the synchronization signal supplied from the outside. External phase lock unit 2 for locking
09, a changeover switch SW3 that switches between the output of the external phase lock unit 209 and the output of the oscillator 210 that generates the internal clock, and the phase based on the signals respectively supplied from the reproduced clock generation unit 209 and the changeover switch SW3. A phase comparator 203 for comparison, and a system clock reference generation unit 201 for generating a system clock reference SCR according to the output from the phase comparator 203.
And a read clock output unit 204 that outputs a clock signal for reading data from the input buffer unit 1 based on the output signal of the system clock reference generation unit 201.

In the third modification, the transmitter 2 shown in FIG.
The program clock reference PCR in the transport layer, which is the system clock information supplied from 1, is M
It is separated by the PEG system demux unit 22A. MP
The EG system demux unit 22A supplies this program clock reference PCR to the recovered clock generation unit 208.

The reproduced clock generator 208 is, for example, MP
It is an oscillator that generates a 27 MHz clock in accordance with the EG2 standard, and supplies the reproduction clock PB27M to the phase comparator 203 based on the supplied program clock reference PCR. An external video signal is supplied to the external synchronization input unit 205. The external synchronization input unit 205 supplies the external synchronization signal EX-H to the external phase lock unit (hereinafter referred to as PLL) 209. The PLL unit 209 generates an external clock whose phase is synchronized with the supplied external synchronization signal and outputs the external clock to one end of the changeover switch SW3. An output from an oscillator 210 that generates an internal clock is supplied to the changeover switch SW3. Here, the oscillator 210 is a 27 MHz frequency oscillator.

The changeover switch SW3 supplies the selected reference clock R27M to the phase comparator 203. Therefore, the system clock reference generation unit 201 generates the system clock reference SCR according to the control signal which is the difference between the reference clock R27M output from the phase comparator 203 and the reproduction clock PB27M.

The read clock output section 204 outputs the read clock signal RCK to the input buffer section 1 in accordance with the system clock reference SCR. With this configuration also, for example, the signal processing unit 2 on the transmission side
The time relationship between the system clock in the encoding unit (not shown) in 1a and the input data can be accurately reproduced between the system clock on the receiving side and the external synchronizing signal / video signal to be output.

Next, as a fourth modified example of the above-described specific example, there is a configuration of the read clock generation section 2 shown in FIG. Here, also in this case, common portions are given the same reference numerals, and description thereof will be omitted. The read clock generator 2 in the fourth modified example is a combination of the configurations of the first modified example and the above-described third modified example.

The read clock generation unit 2 according to the fourth modification includes a sync separation unit 207 for synchronously separating a video signal obtained by demodulating the data from the input buffer unit 1, an output from the sync separation unit 207 and an external unit. A phase comparator 203a for phase comparison with a synchronization signal supplied from the device, a reproduction clock generation unit 208 for generating a reproduction clock based on system clock information obtained from the transport layer, and a phase of the synchronization signal supplied from the outside. An external phase lock unit 209 that performs a process for locking the clock, a changeover switch SW3 that switches between the output of the external phase lock unit 209 and the output of the oscillator 210 that generates the internal clock, a reproduced clock generation unit 208, and a changeover switch SW3 A phase comparator 203b that compares the phases based on the signals respectively supplied from
A system clock reference generation unit 201 that generates a system clock reference based on the outputs from the phase comparators 203a and 203b, and a clock that reads data from the input buffer unit 1 based on the output signal of the system clock reference generation unit 201. It is composed of a read clock output unit 204 which outputs a signal.

The phase comparator 203a performs a process for adjusting the time relationship between the output video signal and the external synchronizing signal, and the phase comparator 203b performs the reproduction clock based on the PCR which is the system clock information supplied from the transmitter 21. PC
Performing processing to match the time relationship between R27M and the external synchronization signal. System clock reference generation unit 201
Generates a system clock reference SCR according to the control signals respectively supplied from the phase comparators 203a and 203b.

As a result, the read clock output unit 204
Supplies the read clock signal RCK corresponding to the system clock reference SCR to the input buffer unit 1.
With this configuration as well, the time relationship between the system clock and the input data in the encoding unit (not shown) in the signal processing unit 21 on the transmission side is the same as the system clock on the reception side and the external synchronization signal is output. It can be accurately reproduced with the video signal.

With the above configuration, the occupancy of the input buffer is monitored, the data input is controlled, and the time axis of the video output signal is controlled. By individually supplying the request signal in accordance with this monitor, it is possible to transmit and receive data in accordance with the video output rate of the receiving device. Further, for example, the relationship between the time axis of the output of the multiplexer unit 21b of the transmission unit 21 and the input of the demultiplexer unit 22a of the reception unit 22 illustrated in FIG.
The input data as the second input video signal is synchronized with the time axis of the output video signal. This allows
Even if there are multiple receivers connected to the same bus or network, each receiver can output video and audio signals in synchronization with their own time axis, and operate in external synchronization. You can also let it.

Also, when one recording medium has a plurality of outputs via a bus or a network, each output can be operated as an independent video reproducing apparatus, and external synchronization is individually applied to each output. Therefore, the degree of freedom in the output signal of the receiving device can be increased.

[0060]

According to the receiving apparatus of the present invention, the occupancy of the input buffer is monitored, the data input is controlled, and the time axis of the video output signal is controlled. By individually supplying the request signal in accordance with this monitor, it is possible to transmit and receive data in accordance with the video output rate of the receiving device. Further, the relationship between the time axis of the output from the transmission side and the time axis of the input at the reception side is synchronized with the time axis of the input data as the input video signal at the reception side and the time axis of the output video signal. As a result, even when a plurality of receiving devices connected to the same bus or network are provided, each receiving device can output a video signal or an audio signal in synchronization with each individual time axis. It can also be operated in synchronization.

Also, when one recording medium has a plurality of outputs via a bus or a network, each output can be operated as an independent video reproducing apparatus, and external synchronization is individually applied to each output. Therefore, the degree of freedom in the output signal of the receiving device can be increased.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a time adjusting unit in a decoding unit applied to a receiving apparatus according to the present invention.

FIG. 2 is a block diagram showing a system configuration when the time adjustment unit is applied to a multi-channel video transmission system.

FIG. 3 is a block diagram showing a specific configuration of a time adjustment unit in a decoding unit on the receiving side of the multi-channel video transmission system.

FIG. 4 is a block diagram of a first modified example of the time adjustment unit.

FIG. 5 is a block diagram of a second modification of the time adjustment unit.

FIG. 6 is a block diagram of a third modification of the time adjustment unit.

FIG. 7 is a block diagram of a fourth modification of the time adjustment unit.

FIG. 8 is a block diagram illustrating time axis control in the video reproduction device.

FIG. 9 is a block diagram illustrating time axis control in a transmission / reception system to which the MPEG2 system is applied.

[Explanation of symbols]

 1 Input Buffer 2 Read Clock Generator 3 CPU 4 Transmitter 10 Time Adjuster 201 System Clock Reference Generator 202 Divider 203, 203a, 203b Phase Comparator 204 Read Clock Output 205 External Synchronization Input 206 Internal Synchronization Generation 207 Synchronous separation unit 208 Regenerated clock generation unit 209 External phase lock unit 210 Oscillator for generating internal clock SW1 to SW3 changeover switch

Claims (6)

[Claims] 1. A receiving device for receiving input data supplied from a transmitting side, wherein: storage means for storing the input data; detection means for detecting an occupied amount of the storage means; and a detection result of the detection means. A receiving device comprising: a control means for transmitting a control signal according to the control signal to a transmitting side; and a read clock generation means for generating a data read clock signal from the storage means. 2. The read clock generating means includes a system clock reference generating means for generating a system clock reference, a frequency dividing means for dividing an output from the system clock reference generating means, and a synchronizing signal internally generated. And a synchronizing signal supplied from the outside, a phase comparing means for comparing the phases of the reference synchronizing signal from the switching means and the system synchronizing signal from the frequency dividing means, and the phase comparing means from the phase comparing means. 2. The receiving apparatus according to claim 1, further comprising a read clock output unit that outputs a clock signal for reading data from the storage unit based on a signal output by the system clock reference generation unit according to the output. 3. The read clock generation means, a sync separation means for synchronously separating a video signal obtained by demodulating data from the storage means, a sync signal internally generated and a sync signal externally supplied. Switching means for switching between, and phase comparison means for comparing the phase of the reference synchronization signal from the switching means with the signal from the synchronization separation means, and from the storage means based on the output signal of the system clock reference generation means. The receiving apparatus according to claim 1, further comprising a read clock output unit that outputs a clock signal for reading data. 4. The read clock generating means generates system clock reference, system clock reference generating means, frequency dividing means for dividing the output from the system clock reference generating means, and data from the storing means. A sync separation means for synchronously separating a video signal obtained by demodulation, a first switching means for switching a sync signal internally generated and a sync signal externally supplied, an output from the frequency dividing means and the above Phase control is performed on the system clock reference generation unit by performing phase comparison on the basis of signals supplied from the first switching unit and the second switching unit, respectively, which switches the output from the synchronization separating unit. Based on the output signals of the phase comparison means and the system clock reference generation means, the storage means outputs data from the storage means. 2. The receiving apparatus according to claim 1, further comprising a read clock output unit that outputs a clock signal for reading the data. 5. The read clock generation means performs reproduction clock generation means for generating a reproduction clock based on system clock information obtained from the transport layer, and processing for locking the phase to a synchronization signal supplied from the outside. External phase locking means, switching means for switching between the output of the external phase locking means and the output of the internal clock generating means for generating the internal clock, and signals supplied from the regenerated clock generating means and the switching means, respectively. From the storage means based on the output signal of the system clock reference generation means, and the phase comparison means for performing phase comparison based on the output from the phase comparison means. Read clock that outputs a clock signal to read data Receiving apparatus according to claim 1, characterized in that it comprises a click output means. 6. The read clock generation means, a sync separation means for synchronously separating a video signal obtained by demodulating data from the storage means, an output from the sync separation means and a sync signal supplied from the outside. First phase comparison means for performing phase comparison with and, reproduction clock generation means for generating a reproduction clock based on system clock information obtained from the transport layer, and processing for locking the phase to a synchronization signal supplied from the outside. The external phase lock means is provided, switching means for switching the output of the external phase lock means and the output of the internal clock generation means for generating the internal clock, and the recovered clock generation means and the switching means are respectively supplied. A second phase comparing means for comparing phases based on signals; and a first phase comparing means and a second phase comparing means. A system clock reference generating means for generating a system clock reference based on an output; and a read clock output means for outputting a clock signal for reading data from the storage means based on an output signal of the system clock reference generating means. The receiving device according to claim 1, wherein the receiving device is provided.