JPH08116328A - ATM speech path device - Google Patents

Abstract

(57) [Abstract] [Purpose] To provide an ATM speech path device having a speech path configuration for realizing an ATM switching system efficiently and economically. [Structure] The ATM speech path is divided into multiple functional blocks,
It is achieved by combining them. That is, only the fixed-length packet routing (distribution to the destination output line) function and the logical multiplexing function are handled by the switch unit, and among other functions, the functions required for line correspondence (for example, phase synchronization function, The flow rate control function) is integrated into a line-corresponding part, and the line common part is a line common part that can be processed even if it is provided in common.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a channel structure of an exchange, and more particularly, a so-called ATM (Asynchronous Transf) for exchanging time division multiplex communication information using fixed length packets.
er Mode: Asynchronous transfer mode) The present invention relates to a speech path configuration suitable for a speech path of a switching system.

[0002]

2. Description of the Related Art A typical communication path of a conventionally used exchange is a digital time-division communication path, and the configuration and operation outline thereof are described in, for example, the book "Digital Switching System" published by the Institute of Electronics and Communication Engineers (Showa era). First edition issued on March 15, 1986) P
-95.

The digital time-division speech path is a speech path suitable for a circuit switching system and is composed of a speech path memory, a control memory, a space division switch and the like.

The control section of the exchange writes the exchange information in the control memory, and the communication information which is time-division multiplexed should be connected by accessing the control memory for each unit (time slot) in which it is multiplexed. Knowing the destination, the switching connection operation is performed.

[0005]

Since the digital time division speech path basically performs circuit switching, it is not suitable for telephone calls with various speeds, which are expected to increase in the future, and multimedia with various characteristics. Not necessarily suitable. On the other hand, the packet switching method, which seems to be able to deal with these relatively flexibly, is the communication method with the above various speeds in the current method.
Especially, it is difficult to support high-speed broadband communication.

From such a background, a method called ATM has been studied as a new exchange method. ATM
Is characterized in that it handles all information such as communication information and call processing signals in units of fixed length packets called cells. In order to realize the ATM switching system, it is necessary to study the concrete structure of the communication path. If limited to the switch function,
Although some concrete proposals have been proposed, how to realize other functions necessary for the ATM speech path, such as cell phase synchronization, label conversion, cell flow rate control, etc. The question of whether a certain channel structure can be constructed has not been solved.

An object of the present invention is to solve the above-mentioned unsolved problems and to provide a speech path configuration which realizes an ATM switching system efficiently and economically.

[0008]

The above object can be achieved by dividing an ATM speech path into a plurality of functional blocks and combining them. That is, only the fixed-length packet routing (distribution to the destination outgoing line) function and the logical multiplexing function are handled by the switch unit, and among other functions,
Functions required for line support (for example, phase synchronization function and flow rate control function) are grouped together as a line support unit, and processing that can be performed even if shared by the lines and that can be shared by hardware is the line common unit. .

Further, in this function division, those functions are processed in a processing hierarchy (protocol layer) as a system.
Analyzing where they are located on the top, aligning the correspondence of each division and hierarchical structure, improving the functional disconnection, increasing the independence of each functional block, and simplifying the communication between each block Therefore, the feasibility is enhanced.

Further, in the above-mentioned line interface, the phase synchronization circuit is made operable by using a plurality of frequencies, and the phase synchronization function and the fixed-length packet speed conversion function are combined. Further, similarly, in the line interface, control information for controlling the flow rate can coexist in the header conversion table (label conversion table) of the packet.

[0011]

The line interface physically terminates the transmission line and also performs processing (ATM termination) relating to the information in the header of the fixed length packet (referred to as a cell). In addition, phase synchronization is performed to match the temporal position of cells on each line.
Further, flow rate control is performed to avoid applying a load larger than that declared by the subscriber terminal.

The line common unit processes call control signals and
Perform call processing.

The switch unit multiplexes and exchanges cells.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an embodiment of the speech path device of the present invention.
The entire speech path device is composed of n ATM line terminators 101 to 101.
10n, a switch unit 110, a signal processing unit 120, and a control mechanism unit 130.

The ATM line terminators 101 to 10n are provided corresponding to the lines. The switch unit 110 has a plurality of (n + 1 in FIG. 1) incoming lines and a plurality (also n + 1) outgoing lines. Each incoming line is connected to a corresponding ATM line terminating device, and each outgoing line is similarly connected to an ATM line terminating device. However, at least one of the incoming lines and at least one of the outgoing lines are connected to the signal processing unit 120. The signal processing unit 120 and the control mechanism unit 130 are connected to each other.

The ATM line terminator (eg 101) is
The transmission line 140 and the switch input line 150, and the output line 160 and the transmission line 170 are interfaced. Although the details will be described later, the main functions are transmission line termination, cell phase synchronization, cell flow rate control, and label conversion.

The switch unit 110 is a switch for exchanging and connecting communication information from a certain incoming line to a certain outgoing line.
On the incoming and outgoing lines, the communication information is handled in the form of fixed length packets called cells shown in FIG. 9A or 9B. The switch part 110 is included in the header part of the cell. This is a so-called self-routing switch that operates in hardware logic based on the information of the logical channel number VCN which is the call identification number or the information of the routing header. Its functions are cell routing and logical multiplexing.

The configuration of the self-routing switch includes, for example, one using a Banyan network and one using a memory switch, and since it can be realized by a known circuit, it will not be specifically described. When the number of accommodated lines is large, it is possible to adopt a multistage configuration as shown in FIG. Basically, the switch unit should have a structure in which a cell entered from any incoming line can go out to any outgoing line.

The signal processing section 120 is a section for processing a signal cell carrying a call processing signal among cells sent from the transmission line, and its main functions are disassembly / assembly of the signal cell, signal speed matching, and the like. Error control and flow control.

The control mechanism section 130 mainly has a call processing function. The function of this functional block is basically the same as that of the conventional communication path.

The signal processing unit 120 and the control mechanism unit 130 can be realized by a combination of a control computer, a logic circuit, etc., and since no special realization technique is required, detailed description will be omitted.

As described above, one embodiment of the speech path configuration of the present invention is composed of four functional blocks. The ATM line termination device, which is the most characteristic functional block of this configuration, will be described in detail below.

FIG. 2 is a block diagram of an ATM line terminal device according to the present invention. In FIG. 2, 201 is a line terminating circuit that serves as a physical interface between a transmission line and a switch, and 202 is a cell phase synchronization circuit that performs phase matching in cells on a cell-by-cell basis. Yes, 203 is a header detection circuit that detects a header including the exchange control information of the incoming cell, and 204 collectively stores the exchange control information and the flow rate control information for each call identification number logical channel. Information table, 205
Is a flow rate monitor circuit for measuring the flow rate of the input cell for each call identification number and monitoring whether or not it exceeds a preset specified value. Reference numeral 206 denotes a header of the cell and an information table 204 and a flow rate monitor. It is a header conversion circuit that rewrites based on the information from the circuit 205.

The circuit will be described below. The signal from the transmission line is input to the line terminating circuit 201, clock extraction,
Physical termination such as frame detection and bit phase synchronization is performed, and the information is input to the cell phase synchronization circuit 202 as an information stream. The cell phase synchronization circuit 202 detects the phase of a cell that is input with a different phase for each line and performs phase synchronization for each cell. Then, the header detection circuit 203 reads the header information of the phase-synchronized cells. The header information is input to the information table 204, and based on the call identification number included in the header, exchange information related to it,
The flow rate control information is extracted and input to the flow rate monitor 205 and the header conversion circuit 206. The flow rate monitor 205 counts the flow rate of the input cell for each call identification number.
And if the flow rate exceeds a predetermined value,
The header conversion circuit 206 is notified that the flow rate has been exceeded.
Based on the information from the information table 204 and the flow rate monitor circuit 205, the header conversion circuit collectively performs header conversion such as reassignment of the call identification number and display of a flow rate excess cell.

Each part of the ATM termination device will be described in detail below with reference to embodiments.

FIG. 3 shows the cell phase lock circuit 20 shown in FIG.
2 shows an embodiment of a portion for sending transmission information from the line terminating circuit 201 to the header detecting circuit 203.
In FIG. 3, reference numeral 301 is an overhead processing circuit that detects a cell delimiter by the overhead of carrying transmission control information in the information stream, and 302 is a cell head signal indicating the head of the cell based on the information of the overhead processing unit and a cell head signal. A cell cycle generation circuit that outputs a write clock control signal corresponding to the arrival period, and 303 is a demultiplexer (DMU) that distributes three buffers having a capacity capable of storing one cell and an input signal to the three buffers.
X) and a selector (SEL) for selecting one of the outputs of the three buffers, 304 is a cell synchronization buffer unit that is written in one cell buffer based on the cell head signal from the cell synchronization circuit 202. Is a write control circuit for sequentially switching the write buffer to
307 is a read wait flag register having a register for storing the write state of each of the three buffers for each buffer, 306 is a flip-flop for latching the output of the read wait flag register, 307
Reference numeral 308 is a read control circuit that determines a read buffer based on the latched value of the flip-flop 306 and switches the read buffer, and reference numeral 308 is a read cycle generation circuit that generates a read cycle signal indicating a cycle of reading cells from the buffer. , 309 is a buffer read clock creation circuit that creates a buffer read clock from the system clock and the output of the read cycle generation circuit 308, 310 is a read clock creation circuit that creates a write clock from the input signal clock, and 311 is This is a gate for controlling the reset signal of the read flag register 305. The operation of this circuit will be described below. The frequencies of the read clock and the write clock differ from each other by a frequency corresponding to the difference between the overhead and the bit rate required to transmit the routing header described later.

In the signal input to the present circuit, cells are arranged in the frame structure due to the periodically arranged overhead as shown in the input information stream of FIG.
As shown in this figure, cells may be fragmented due to the overhead. When viewed in one frame, it has the structure shown in FIG. One frame has 10 bytes of overhead and 2 between overheads
An area containing a 70-byte cell constitutes 9 overhead cycles. On the other hand, the positional relationship between each cell and the frame is included in the overhead as pointer information. The overhead processing circuit 301 detects the positional relationship between the frame and the cell by looking at the pointer information, and sends the information to the cell cycle generation circuit 304.
The cell cycle generation circuit 302 includes an overhead processing circuit 3
An output of 01 generates a cell generation period signal and a write clock control signal. The AND gate 310 is controlled by the write clock control signal, and the write clock is output only during the cell arrival period. On the other hand, the write control circuit 304 is generated by the cell cycle signal output from the cell cycle generator.
Switches the write buffer in order. The cell synchronization buffer 303 writes only a portion of cells in the information stream into the buffer one cell at a time according to the write clock. The read wait flag register 305 is set to a corresponding register each time cell writing is completed.

Next, when reading a cell from the cell synchronous buffer, the value of the read wait flag register is latched by the flip-flop 306 by the read cycle signal and the result is input to the read control circuit 307 to determine the read buffer. The result can be read out from the buffer by sending it to the cell synchronization buffer at the cell sending timing.

The read clock generation circuit 309 is
The first 2 bytes of the cell operate so as to stop the clock, and secure an area of the routing header which is the exchange control information in the switch for each cell.

At the time of reading, if there is no buffer in which cell writing has been completed in the cell synchronization buffer, the read control circuit 307 controls the cell synchronization buffer 303 and sends out an empty area having the same length as the cell. And gate 3
11 is controlled so that the read wait flag register is not reset.

Next, the operation of this circuit will be described with reference to the time chart of FIG. When the overhead in the input information stream arrives, the cell cycle generation circuit 302 outputs the overhead cycle signal, and the AND gate 310 stops the write clock. Therefore, only the cell part in the input information stream is selectively selected by the cell synchronization buffer 3.
Write in 03. Further, the cell head signal is output from the cell cycle generation circuit 302 immediately before the cell division, and the write control circuit 304 switches the cell synchronization buffer.
At the same time, the buffer for which writing has been completed is stored by setting the corresponding register in the read wait flag register. Next, at the rising edge of the read cycle signal output from the read cycle generation circuit 308, the output of the read flag register is latched by the flip-flop 306. Then, at the fall, the read control circuit 307 selects the buffer to be read next, and switches the selector in the cell synchronization buffer. At the same time, it corresponds to the buffer to be read next. Reset the registers in the read flag register. 2 after the read buffer is switched
The read clock generation circuit 309 is used for the period for transmitting the bytes
Does not output the read clock, and the area between them becomes the routing header area. After the routing header area,
One cell is continuously read from the buffer selected for reading.

As shown in the figure, the cell synchronization circuit of this embodiment has the function of removing the overhead area from the input information stream at the same time as performing cell synchronization on each line and at the same time securing the routing header area. .

Next, an embodiment of the portion of the cell phase synchronizing circuit 202 for transmitting the transmission information from the switch to the line terminating circuit will be described with reference to FIG. In FIG. 4, reference numeral 401 denotes three buffers capable of storing one cell and a demultiplexer (DEMUX) for allocating cells from the switch to each buffer, and a selection circuit (SEL) for selecting the outputs of the three buffers and the overhead generating circuit. A write control circuit for switching the write buffers by a cell head signal from a switch, and 403 has registers corresponding to the three buffers of the cell sync buffer 401. Reference numeral 404 denotes a read wait flag register that is set at the end of writing and reset at the time of reading. Reference numeral 404 denotes a flip-flop that latches the output of the read wait flag register.
Reference numeral 05 is a read control circuit that determines a read buffer based on the value latched in the flip-flop 404 and that switches the output to the overhead generation circuit in the overhead cycle, and 407 indicates the read cycle signal of the output cell and the output overhead area. A readout cycle generation circuit that outputs the overhead cycle signal shown
Reference numeral 408 is a write clock generation circuit that outputs a write clock during the period excluding the routing header area assigned to the cell. Reference numeral 409 is the output of the read control circuit 405. If there is no write end buffer, the read wait buffer register is reset. It is an AND gate to stop.

The operation of this circuit will be described below. As shown in FIG. 9 (b), the cell input from the switch is provided with a routing header, and during that time, the write clock generation circuit 406 stops the clock to write only the cell to the buffer. The write buffer is switched every time one cell is written by the cell head signal. At the same time, the corresponding register in the read wait flag register is set.

Next, when reading a cell from the cell synchronous buffer, the value of the read flag register 403 is latched by the flip-flop 404 by the read cycle signal and the result is input to the read buffer selection circuit 405 to determine the read buffer. . The result can be read from the buffer by sending the result to the cell synchronization buffer at the cell read timing. on the other hand,
The read cycle generation circuit 407 periodically outputs an overhead cycle signal indicating an overhead area.
When this signal is input to the read control circuit 405, the read control circuit 405 controls the cell synchronization buffer 401 and outputs overhead information. During this time, the read operation from the cell synchronization buffer 401 is stopped.

At the time of reading, if there is no buffer in which cell writing has been completed in the cell synchronization buffer, the read control circuit 404 controls the cell synchronization buffer 401 to send out an empty cell. Also, the AND gate 409 is controlled so that the read waiting flag register is not reset.

Next, the operation of this circuit will be described with reference to the time chart of FIG. When the routing header in the cell stream from the switch arrives, the write clock is stopped and the cell is not written during that time. Further, the write control circuit 402 controls the cell synchronization buffer 401 by the cell head signal, switches the write buffer, and starts writing to the next buffer. At the same time, the buffer for which writing has been completed is stored by setting the corresponding register in the read wait flag register 403. next,
At the rising edge of the read cycle signal output from the read cycle generation circuit 407, the output of the read flag register 403 is latched by the flip-flop 404. Then, at the trailing edge, the read control circuit 405 selects and switches the buffer to be read next. At the same time, the register in the read flag register 403 corresponding to the buffer to be read next is reset. On the other hand, when an overhead cycle signal is output from the read cycle generation circuit, cell reading is stopped during that time, and overhead is output from the cell synchronization buffer 401.

The cell phase synchronization circuit of this embodiment removes a routing header which is unnecessary on the transmission line and at the same time inserts an overhead required on the transmission line.

Next, an embodiment of the flow rate monitor circuit is shown in FIG. In FIG. 5, reference numeral 501 denotes a cell counting memory that stores a count value of the number of input cells for each call identification number.
2 is a timer memory that stores the measurement start time, and 5
Reference numeral 03 denotes a declared value memory that stores a value that each subscriber declares the minimum time for sending a predetermined number N of predetermined times at the time of call setup, and 504 adds 1 to the output value of the cell counting memory 501. An adder 510 is a timer that outputs the current time, 505 is a subtracter that calculates the measurement time by subtracting the output of the timer memory 502 from the output of the timer 510, and 506 is the number of cell arrivals. Is a comparator that compares the number of arrivals with a fixed number N to see if the number of arrivals exceeds a certain number. Reference numeral 507 compares the measurement time output from the subtractor 505 with the declared value, and the measured time is the declared value. 508 is a comparator for checking whether or not the flow rate is exceeded, and the output of the comparator 506 indicates that the header conversion circuit 2 outputs a flow rate control signal for instructing discard or marking of the flow rate excess cell.
Is a violating cell processing circuit for sending to 06, 509, while the cell flow rate measurement operation is not performed, access each call identification number to the timer memory 502 in order, and whether the measurement time exceeds the declared value A time-out monitoring circuit that generates a memory address for monitoring is provided. Reference numeral 511 is a selector that switches the memory access address during the cell counting period and the time-over monitoring period. In FIG. 5, the cell counting memory 501, the timer memory 502, and the declared value memory 503 are accessed by the call identification number of the input cell, and therefore may be placed in each information table 204 (or the like) of the ATM line terminators 101 to 10n. It is possible.

The operation of this circuit will be described below. When the cell arrives at the ATM converter, the header detection circuit 203 sends a call identification number. Using the call identification number as an address, the cell counting memory 501, the timer memory 502, and the declared value memory 503 are accessed to obtain the flow rate control information corresponding to the call identification number. And the cell counting memory 501
1 is added to the count value from the adder circuit 504, and the result is rewritten in the cell count memory 501. On the other hand, the added count value is input to the comparator 506 and compared with the fixed number N. If the count value is larger than N, the flow rate excess information is notified to the violating cell processing circuit 508. When the violation cell processing circuit 508 receives the notification of the flow rate excess, it sends a flow rate control signal to the header conversion circuit 206 to instruct discarding or marking of the excess cell. Depending on the traffic state of the line, the selection of discarding or adding a mark is performed in the congestion state and is added in the case where the line capacity has a margin. The marked cells are discarded by the switch at the time of congestion or in a state close to it.

On the other hand, in parallel with the cell counting operation, the subtractor 506 calculates the measurement time from the output values of the timer 510 and the timer memory 502, and the comparator 507 compares the measurement time with the declared value. If it exceeds, the count value for the call identification number of the input cell in the cell count memory 501 is reset, and the current time is written in the timer memory 502. As a result, the measurement starts again from the beginning.

Next, the operation of this circuit will be further described with reference to FIG. FIG. 14 shows the state of arrival of a cell having one call identification number. In this case, the fixed number N is four. As shown in this figure, cells are counted at a declared value (time) interval, and cells exceeding a fixed number of four are regarded as excess cells. When the declared value (time) is exceeded, the next measurement period starts and the cell flow rate is constantly monitored.

In this circuit, since the timer memory is not accessed unless the cell arrives in the case of only the above operation, the measurement time cannot be correctly obtained when the time exceeds the time limit of the information length of the timer memory. During the non-operation period, the timer memory 502 is sequentially accessed by the time-over monitoring circuit to monitor whether the declared value is exceeded, and if it is, the timer memory 501 is reached.
Is reset and the timer memory 502 is rewritten to the current time to start the next measurement period.

According to this embodiment, the cell counting memory 50
1. Timer memory 502 and declared value memory 503 are ATM
Since it can be placed in the information table 204 (or the like) of the line terminators 101 to 10n, the amount of hardware can be reduced. Further, as in the present embodiment, a fixed number N for each call identification number
Since the flow rate is measured based on, the accurate measurement is possible irrespective of the call speed when measuring a large volume speed.

Next, another embodiment of the flow rate monitor circuit 205 is shown in FIG. In FIG. 6, 601 is a cell counting memory that stores the count value of the number of input cells for each call identification number, 602 is a timer memory that stores the measurement start time, and 603 is a call for each subscriber. Numeral 604 is a declared value memory for storing a value declared as the maximum number of cells to be transmitted within a predetermined time T set at the time of setting, 604 is an adder for adding 1 to the cell count memory 501, and 610 is the present 605 is a timer for outputting the time of
Reference numeral 606 is a subtractor that calculates the measurement time by subtracting the output of the timer memory 602 from the output of 10, and a comparator 606 that compares the number of arrivals of cells and the declared value to see if the number of arrivals exceeds the declared value. 607 is a comparator that compares the measurement time output from the subtractor 605 with the fixed time T to see whether the measurement time exceeds the declared value.
Reference numeral 8 denotes a violating cell processing circuit which sends a flow rate control signal for instructing discarding or marking of an excess flow rate cell by the output of the comparator 606 to the header conversion circuit 206.
Reference numeral 9 is a time-over monitor for generating a memory address for accessing each call identification number in order in the timer memory 602 while the cell flow rate measurement operation is not performed and monitoring whether the measurement time exceeds the declared value. Circuit, 611
Is a selector that switches between the memory access address in the cell counting period and the memory access address in the timeout monitoring period. In FIG. 6, the cell counting memory 601, the timer memory 602, and the declared value memory 603 are accessed by the call identification number of the input cell, and therefore can be placed in each information table 204 (or the like) of the ATM line terminators 101 to 10n. It is possible.

The operation of this circuit will be described below. When the cell arrives at the ATM converter, the header detection circuit 203 sends a call identification number. Using the call identification number as an address, the cell counting memory 601, the timer memory 602, and the declared value memory 603 are accessed to obtain the flow rate control information corresponding to the call identification number. And the cell counting memory 601
1 is added to the count value from the adder circuit 604, and the result is rewritten in the cell count memory 601. On the other hand, the added count value is input to the comparator 606 and compared with the declared value. If the count value is larger than the declared value, the flow rate excess information is sent to the violation cell processing circuit 608. When the violation cell processing circuit 608 receives the notification of the flow rate excess, it sends a flow rate control signal to the header conversion circuit 206 to instruct discarding or marking of the excess cell. Depending on the traffic state of the line, the selection of discarding or adding a mark is performed in the congestion state and is added in the case where the line capacity has a margin.

On the other hand, in parallel with the cell counting operation, the subtractor 606 calculates the measurement time from the output values of the timer 610 and the timer memory 602, and the comparator 607 compares it with the constant time T. If it exceeds, the count value for the call identification number of the input cell is reset in the cell calculation memory 601, and the current time is written in the timer memory. As a result, the measurement starts again from the beginning.

Next, the operation of this circuit will be further described with reference to FIG. FIG. 15 shows how a cell with one call identification number arrives and pays attention to it. In this case, the declared value is four. As shown in this figure, cells are counted at a constant time interval, and cells exceeding the declared value of 4 are regarded as excess cells. In addition, the flow rate of the cell is constantly monitored by entering the next measurement period from the time when the fixed time is exceeded.

In this circuit, since the timer memory is not accessed unless the cell arrives in the case of the above operation only, the measurement time cannot be correctly obtained when the time exceeds the time limit of the information length of the timer memory. The timer memory 602 is sequentially accessed by the time-over monitoring circuit during the period when the timer memory 602 has not been performed, and it is monitored whether or not the predetermined time T has been exceeded.
01 is reset, the timer memory 602 is rewritten to the current time, and the next measurement period starts.

According to this embodiment, the cell counting memory 60
1. Timer memory 602 and declared value memory 603 are ATM
Since it can be placed in the information table 204 (or the like) of the line terminators 101 to 10n, the amount of hardware can be reduced. Further, when the flow rate is measured for each call identification number based on a fixed time as in this embodiment, the upper limits of the cell count memory 601 and the timer memory 602 are determined regardless of the call speed when the measurement time such as the average speed is long. There is an advantage.

Next, FIG. 7 shows an embodiment of the header conversion circuit 206. In FIG. 7, reference numeral 701 is a selector for inserting the routing information and the new call identification number at a predetermined timing, and 702 is an AND for discarding the cell by setting the cell identification number to “0”. 704 is a gate, and the mark bit 704 in the cell header is "1".
705 is an OR gate, and 706 is a flip-flop for reproducing a signal. The operation of this circuit will be described below. When sending cells from the ATM line terminators 101 to 10n to the switch, the format is as shown in FIG. 9B. Therefore, in the header conversion circuit,
First, the timing creation circuit 703 controls the selector 701 to insert the routing header information corresponding to the call identification number of the cell from the information table 204 into the 2-byte routing header area provided at the beginning of the cell.
Next, similarly, the call identification number from the information table is inserted at a predetermined position in the cell in place of the input call identification number.
At this time, if a cell discard flow control signal is input from the flow monitor circuit 205, the call identification number becomes "0" by the AND gate 702, and the cell is discarded by the switch.

Next, when the mark flow rate control signal from the flow rate monitor circuit 205 is input, "1" is inserted in the mark bit shown in FIG. 9B by the control signal from the timing generation circuit. To be done. The cell for which the above header conversion processing has been completed reproduces the signal in the flip-flop, so that the self-routing switch 11 has an accurate phase.
Input to 0.

According to the present embodiment, the insertion of the routing header, the rewriting of the call identification number, and the marking can be executed at the same time, and the hardware amount and the cell delay can be reduced.

Finally, the information table 204 will be described with reference to FIG. FIG. 8 is a diagram showing an example of information stored in the information table 204 and a storage format. In the case of the present embodiment, the output call identification number assigned to the cell by the header conversion circuit 206 using the input call identification number as an address, the declared value, the cell count value, the timer value and the violating cell used in the flow rate monitor circuit 205. The number is remembered. In this way, the amount of hardware can be reduced by collectively storing information for each call identification number.

[0055]

According to the present invention, a fixed length packet (cell) including a header part for routing and an information part
Use to exchange communication information. The ATM communication channel can be realized economically and efficiently. The functional block configuration is highly compatible with the processing layer (protocol layer) of the system, and therefore each block is highly independent and connections between blocks are easy. On the other hand, in the block, a plurality of functions can share the same hardware, and an efficient and economical structure can be achieved.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a speech path device according to the present invention.

FIG. 2 is a configuration diagram of an ATM line terminal device in FIG.

3 is a configuration diagram showing an embodiment of a cell phase synchronization circuit in FIG.

4 is a configuration diagram showing another embodiment of the cell synchronization circuit in FIG.

5 is a configuration diagram showing an embodiment of a flow rate monitor circuit in FIG.

FIG. 6 is a diagram showing another embodiment of the flow rate monitor circuit in FIG.

7 is a configuration diagram showing an embodiment of the header conversion circuit in FIG.

FIG. 8 is a diagram illustrating an information table in FIG.

9 is a diagram showing input / output signals of the cell phase synchronization circuit in FIG.

10 is a diagram for explaining an input signal of the cell phase locked loop circuit in FIG.

11 is a diagram showing a configuration example of a switch unit in FIG.

FIG. 12 is a time chart explaining the operation of the cell phase locked loop circuit of FIG.

13 is a time chart diagram explaining the operation of the cell phase synchronization circuit of FIG.

14 is a diagram for explaining the operation of the flow rate monitor circuit of FIG.

15 is a diagram for explaining the operation of the flow rate monitor circuit of FIG.

[Explanation of symbols]

Reference numerals 101 to 10n ... ATM line termination device, 110 ... Switch unit, 120 ... Signal processing unit, 130 ... Control mechanism unit, 201 ... Line termination circuit, 202 ... Cell phase synchronization circuit, 203 ... Header detection circuit, 204 ... Information table, 205 ... Flow rate monitor circuit, 206 ... Header conversion circuit, 301 ... Overhead processing circuit, 302 ... Cell cycle generation circuit, 303, 401 ... Cell synchronization buffer, 304, 402 ... Write control circuit, 305, 403 ... Read wait flag register, 306, 404, 706 ... Flip-flop, 307, 405 ... Read control circuit, 308, 407 ... Read cycle generating circuit, 309 ... Read clock creating circuit, 310, 311, 409, 702, 704 ... And gate, 406 ... Write clock Generation circuit, 501, 01 ... Cell counting memory, 502, 602 ... Timer memory, 503, 603 ... Declaration value memory, 504, 604 ... Adder, 505, 506 ... Subtractor, 506, 507, 605, 606 ... Comparator, 508, 608 ... Violation cell processing circuit, 509, 609 ... Timeout monitoring circuit, 609, 610 ... Timer, 511, 611, 701 ... Selector, 703 ... Timing generation circuit, 705 ... OR gate.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Shinobu Gohara 216 Totsuka-cho, Totsuka-ku, Yokohama, Kanagawa Stock, Hitachi Co., Ltd. Totsuka Plant (72) Inventor, Otsuki, Kanagawa 216 Totsuka-cho, Totsuka-ku, Yokohama-shi, Kanagawa Hitachi, Ltd. Totsuka factory

Claims (1)

[Claims] 1. An ATM speech path apparatus for handling information such as communication information and call processing signals using a fixed length packet as a unit cell, and fixed length packet routing based on call identification information included in the header of the cell. A switch unit that performs logical multiplexing, and a cell that is connected to the switch unit through an input line and an output line and that is transmitted from a transmission line, is used for disassembling and assembling a signal cell for carrying a call processing signal, and adjusting the speed of a signal. A signal processing unit that performs error control and flow control, a control unit that is connected to the signal processing unit and controls call processing, and a line termination circuit that serves as a physical interface between the transmission line and the switch unit. , A cell phase synchronization circuit that is connected to the line termination circuit and inputs cells in different phases on each line and performs phase adjustment in cell units, and exchange of cells input from the cell phase synchronization circuit A header detection circuit that detects a header containing control information, an information table that collectively stores the exchange control information detected by the header detection circuit for each call identification number logical channel, and an input cell from the header detection circuit. A line having a flow rate monitor circuit that measures the flow rate for each call identification number and monitors whether it exceeds a specified value, and a header conversion circuit that rewrites the header of the input cell based on the information table and the information from the flow rate monitor circuit. An ATM speech path device having a terminating device.