JPH08125510A - Signal delay circuit - Google Patents

Abstract

PURPOSE: To realize a circuit obtaining a highly precise and stable delay signal in LSI. CONSTITUTION: A decoder 20 which selectively outputs input signals is provided on latch circuits 21-24 obtaining delay quantity to be delayed with signals to be delayed as inputs. Plural latch circuits 21-24 giving clocks different in delay quantity from the external part of LSI as latch clocks and setting the output of the decoder 20 as input data are provided. Thus, the signal having target delay quantity is obtained through a gate 25 which OR-operates the outputs of the latch circuits.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delay circuit for delaying a signal with a resolution T inside an LSI.

[0002]

2. Description of the Related Art Conventionally, when an attempt is made to delay a signal with a resolution T inside an LSI, a circuit is generally realized by switching delay paths as shown in FIG. That is, a circuit in which delay elements such as the delay element T10 and the delay element 2T11 are cascade-connected by the multiplexer 12 and the multiplexer 13 is provided. And as a signal path,
The delay amount is controlled by selecting the delay element or not selecting the delay element. Delay element T10 and delay element 2
T11 has a configuration in which logic gates are cascaded in multiple stages.

[0003]

When a large number of delay circuits as described above are present inside the LSI, a temperature difference occurs depending on the frequency of use of the delay circuits, and the delay time varies. Especially, in the CMOS circuit, the variation of the delay time is a serious problem. Also, due to variations in manufacturing,
The delay time may be a different value and may cause a problem. An object of the present invention is to realize a circuit that obtains a highly accurate and stable delay signal inside an LSI.

[0004]

To achieve the above object, in a signal delay circuit according to the present invention, a signal to be delayed is input to a latch circuit that selectively obtains a desired delay amount. A decoder that outputs a signal is provided. Then, a plurality of latch circuits are provided which use clocks having different delay amounts as latch clocks from the outside of the LSI and which use the output of the decoder as input data. Then, a signal having a target delay amount is obtained through a gate that logically sums the outputs of the latch circuits.

[0005]

By providing the clock generation unit for obtaining the delay amount outside the LSI, it is possible to easily correct the accuracy of the clock with various delay amounts and obtain a stable delay with respect to temperature changes and voltage changes. You can Further, since the multistage gate delay element for delay is not provided inside the LSI, the circuit inside the LSI can be used for circuits other than the delay, and the LSI can be efficiently designed.

[0006]

EXAMPLE FIG. 1 shows an example of the present invention. A decoder 20 that receives a delayed signal A as an input and outputs the signal A to one circuit of a plurality of latch circuits that latch at different delay timings and a decoder that receives a clock with a delay amount of 0 from the outside A latch circuit 21 for latching the signal A selected by 20; a latch circuit 22 for latching the signal A selected by the decoder 20 with a clock having a delay amount T supplied from the outside; and a delay amount 2 supplied from the outside.
A latch circuit 23 that latches the signal A selected by the decoder 20 with a clock of T, and a delay amount 3 supplied from the outside
A latch circuit 24 for latching the signal A selected by the decoder 20 with the clock of T and a gate 25 for ORing the outputs of the latch circuits 21 to 24 are configured. Latch circuit 2
Which of the circuits 1 to 24 is effective as a circuit for delaying the signal A depends on the selection input signals S0 and S of the decoder 20.
It depends on 1.

When this circuit is used, a clock synchronized with the delayed signal A is preliminarily set outside the LSI as shown in FIG.
It is prepared by providing a phase difference as shown in (B). By inputting a clock having these phase differences from the outside of the LSI into the inside of the LSI as a latch clock, a delayed signal of the signal A having the resolution T can be obtained. Clocks given from the outside and having different phase differences are generated by a delay amount generation circuit due to differences in the lengths of delay lines and cables outside the LSI. Since the phase difference of the clock generated externally is outside the LSI, the accuracy can be easily corrected.

[0008]

Since the present invention is constructed as described above, the desired signal delay can be realized accurately and stably. Further, since the gate delay element is not formed inside the LSI, the LSI can be efficiently realized as a circuit other than the delay element.

[Brief description of drawings]

FIG. 1 is a block diagram and a timing diagram showing a signal delay circuit of the present invention.

FIG. 2 is a block diagram showing a conventional signal delay circuit.

[Explanation of symbols]

 10, 11 Delay circuit 12, 13 Multiplexer 20 Decoder 21-24 Latch circuit 25 Logical sum gate

Claims (1)

[Claims] 1. A decoder (20) that selectively outputs the input signal to a latch circuit that receives a delayed signal as an input and obtains a desired delay amount, and a clock having a different delay amount as a latch clock. A signal delay circuit comprising: a plurality of latch circuits (21 to 24) that use the output of the decoder (20) as input data; and a gate (25) that performs an OR operation on the outputs of the latch circuits.