JPH08126011A - Image decoding method and image decoder - Google Patents

Abstract

PURPOSE: To provide an image decoding method and a decoder in which the utilizing efficiency of a memory is enhanced. CONSTITUTION: When data are written in a prediction frame memory, an address space to store one frame data and an address space for 8 slices or over are provided, and after data of one frame are written, read for displaying one frame is started and write of succeeding frame data is started from the address space of remaining 8-slices or over, and read/write of the data are executed while deviating the read address of one frame and write address of a succeeding frame are deviated by 8 slices or over, the data are overwritten in the address space whose read is finished while keeping the address space by 8 slices and the processing above is repeated cyclicaly.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image decoding method and an image decoding apparatus for decoding an image signal coded by forward prediction, and more particularly to a writing / reading means for a frame signal to / from a predictive frame memory. is there.

[0002]

2. Description of the Related Art When transmitting or storing digitally represented image data, encoding is performed to reduce the amount of data. As a coding method, there is a method of reducing redundancy by utilizing temporal or spatial correlation of image information.

As a method of utilizing the temporal correlation, there is a method of encoding a difference between two consecutive screens (frames) or detecting a motion of an image to perform motion compensation.
As a method of utilizing spatial correlation, an image is divided into blocks of a predetermined size (for example, 8 pixels in each of the vertical direction and the horizontal direction), the data in each block is orthogonally converted, and the conversion coefficient is scan-converted. However, there is one that performs variable length coding (for example, rearranges in order from low frequency components to high frequency components). An image coding method (hereinafter abbreviated as MPEG2), which is being standardized by the Moving Picture Experts Group (MPEG), uses the above two methods together.
The provisional recommendation for MPEG2 is "Generic Coding of Moving Pi
ISO / IEC13818- entitled "Ctures and Associated Audio"
It is described in 2.

FIG. 4 shows an example of the configuration of an image decoding apparatus for decoding data encoded by such a method. In FIG. 4, 10 is a memory accumulating means, which comprises a buffer memory control unit 11 and a buffer memory 12. Decoding unit 20 includes a variable length decoder 21, a scan converter 22, an inverse quantizer 23, an inverse DCT unit 24, a motion compensation image reproducing unit 25, and a prediction frame memory 26. Reference numeral 40 is prediction data, 41 is decoded data, and 42 is display data. In addition, reference numeral 100 denotes an input bitstream representing an encoded image, and 200 denotes a reproduced image.

Next, the operation will be described.

The input bit stream 100 is stored in the buffer memory 12 under the control of the buffer memory control unit 11. The data read from the buffer memory 12 is variable length decoded by the variable length decoder 21.

Although not all data is variable length coded, it is assumed that the fixed length code is also decoded by the variable length decoder 21. Next, after the order of the data is rearranged by the scan converter 22, it is inversely quantized by the inverse quantizer 23. Next, the inverse DCT unit 24 performs inverse discrete cosine transform. When the inter-frame difference is received, the motion compensation image reproduction unit 25 reads the prediction data 40 from the prediction frame memory 26, adds the prediction data 40 to the reception data from the inverse DCT unit 25, and then the decoded data 41 to the prediction frame memory 26. Write. When the data encoded in the frame is received, the received data is written in the predictive frame memory 26 as it is. The reproduced image 200 is reproduced as described above.

In forward (one-sided) prediction, a frame (here, P frame) that is temporally later than a preceding frame (here, I frame) is predicted. For this reason, the prediction data 4 of the I frame that has been decoded in advance is reproduced for reproducing the P frame.
It is necessary to read 0. The P frame is reproduced by the prediction data 40 and the prediction error output from the inverse DCT unit 24, and is written in the prediction frame memory 26 as the decoded data 41. Further, the written data is read as the display data 42, and is output as the reproduced image 200 from the motion compensation image reproducing unit 25.

[0009] In addition, Dual Prime
In the prediction, it is necessary to average the predictions of the two fields of the referenced I frame or P frame to predict the field.

[0010]

In the forward prediction, the information of the previous frame is left and the next frame is predicted with reference to it. Therefore, in order to perform normal reading and reading (when there is no memory overtaking control), the predicted frame memory 26 needs at least 1.5 frames of the frame image to be handled. In particular, PAL (Phas
e Alternation by Line) system uses NTSC (National T
elevision System Committee)
This requires double the memory capacity, which is a major economic drawback. The present invention solves the above problems in the conventional image decoding method and apparatus, and provides a predetermined memory address space in addition to the one frame memory instead of the conventional storage method using a memory of 1.5 frames or more. It is an object of the present invention to provide an image decoding method and an image decoding device that improve the memory usage efficiency (minimize the memory capacity) by overwriting on the same memory.

[0011]

According to the image decoding method of the present invention, when data is written in a prediction frame memory,
An address space for storing one frame data and an address space for 8 slices or more are provided, and after writing one frame of data, reading for displaying one frame is started, and further the next frame data is stored as the remaining one. Writing is started from the address space of 8 slices or more, and at this time, the reading and writing of data is executed while the read address of one frame and the write address of the next frame are shifted by 8 slices or more, and the address space of 8 slices is executed. While overwriting, the address space that has been read is continuously overwritten and this is cyclically performed.

Further, in the image decoding apparatus according to the present invention, when the decoded data is written in the prediction frame memory, the address space for storing the previous frame data and the subsequent 8 slices or more (that is, 360 macroblocks or more in the NTSC system, here, 1 slice takes 16 lines in a frame image), and an address space of 1 frame + 360 is provided.
It has an overwriting means for overwriting the same memory for macro blocks and a reading means for the frame signal.

[0013]

According to the image decoding method and the image decoding apparatus of the present invention, the fact that the maximum vertical motion compensation range is 8 slices in each profile (system classification) defined by MPEG2 is utilized. When writing data to the predictive frame memory, in addition to the memory for one frame on the memory, by providing an address space of 8 slices or more, that is, 360 macroblocks or more in the NTSC / PAL system, the minimum required for motion compensation is provided. Minimal memory (1 frame + memory for 360 macroblocks or more) by performing motion compensation for the subsequent frame using only the limit information
Enables the memory storage operation in the decoding process.

[0014]

Embodiments of the present invention will be described with reference to FIGS. 1, 2 and 3.

FIG. 1 is a block diagram showing an embodiment of the present invention, and the same reference numerals as those in FIG. 4 denote the same parts. Reference numeral 27 denotes an address space corresponding to 8 slices or more according to the present invention, and 50 is a memory including the buffer memory 12 and a prediction frame memory 26 having an address space 27.
Mbit dynamic RAM is used. Reference numeral 30 is an address control unit. Further, 25A is an overwriting means, 25B
Indicates a reading means.

FIG. 2 is a diagram for explaining a method of writing to the prediction frame memory 26.

FIG. 3 is a diagram showing the timing of writing / reading to / from the prediction frame memory 26.

Next, the operation of the embodiment shown in FIG. 1 will be described. First, the input bit stream 100 passes through the buffer memory control unit 11 and the buffer memory 12 and is subjected to each processing as described in FIG. 4 and reaches the motion compensation image reproduction unit 25. Then, the decoded data 41 of the motion-compensated frame is written in the predicted frame memory 26 via the address control unit 30. Then, from the head of this frame, each field data is sent as the display data 42 to the motion compensation image reproducing unit 25, and is output as the reproduced image 200.

Next, the written decoded data 41 is read out as the prediction data 40.

At this time, in each profile (system classification) defined by MPEG2, the fact that the maximum motion compensation range in the vertical direction is 8 slices is utilized, and 8 slices or more for the prediction frame memory 26 are used. Address space 2
7 (macroblock: address space of 1105920 bits or more) is provided, and the decoded data 41 of the next frame, which is motion-compensated while referring to the first 8 slices of the previous frame, is provided on the prediction frame memory 26. It is written in the address space 27 of 8 slices or more.

Similarly, the prediction data 4 of the previous frame is sequentially obtained.
Motion compensation is performed while referring to 0, decoded data 41 of the next frame is generated, and the memory addresses for reading the previous frame and writing the subsequent frame on the prediction frame memory 26 are continuously deviated by 8 slices or more. The decrypted data 41 is read and written. As described above, the decoded data 41 of the frame after motion compensation is overwritten on the prediction frame memory 26 while shifting the address by 8 slices or more with respect to the read address of the previous frame.

As a result, the prediction data 40 for 8 slices for the reference of the previous frame, which is the maximum vertical motion compensation range required when performing the motion compensation, is secured without being lost by the overwrite, and the subsequent frame is secured. Motion compensation is performed. Similarly, writing and reading are continuously repeated by the overwriting unit 25A and the reading unit 5B while shifting the address space 27 for the subsequent 8 frames or more.

FIG. 2 shows the operation of continuously repeating writing and reading in the prediction frame memory 26 while shifting the address space of 8 slices or more, and FIG. 3 shows the timing relationship between the prediction data 40, the decoded data 41 and the display data 42. Indicates. The motion-compensated decoded data 41 of the first frame is written in the prediction frame memory 26. First
Each odd number (Odd) and even number (Eve) from the beginning of the frame
n) The field data is sent to the motion-compensated image reproduction unit 25 as the display data 42 and output as the reproduced image 200. The decoded data 41 written next is the predicted data 40
Read as. At this time, the decoded data 41 of the second frame, which is created by motion compensation with reference to the first 8 slices of the first frame, is provided in the predicted frame memory 26 with the address space 27 of 8 slices or more. The data is written in the address space 27 of 8 slices or more provided on the memory 26. Further, the motion compensation is performed with reference to the next predicted data 40 of the first frame, and the decoded data of the second frame is continuously written while the memory addresses of the reading of the previous frame and the writing of the subsequent frame are shifted by 8 slices or more. go. Similarly, the decoded data 41 of the third frame after motion compensation is used as the predicted frame memory 26.
Overwriting is performed while shifting the address by 8 slices or more with respect to the read address of the second frame.

At the time of writing, 8 Mbit dynamic RA
Writing is performed from the head address of the prediction frame memory 26 mapped on the M50, and when a predetermined address set to 1 frame + 8 slices or more is reached, the writing is repeated at the head of the prediction frame memory 26 and repeated writing is performed.

Since the memory is used cyclically as described above, an address control unit 30 is provided between the motion compensation image reproducing unit 25 and the prediction frame memory 26 as shown in FIG. 1 to store each frame start address, Used to generate the address of the next frame.

[0026]

According to the image decoding method of the present invention, when data is written in the prediction frame memory, an address space for storing 1 frame data and an address space for 8 slices or more are provided and after writing 1 frame of data. , The reading for displaying the one frame is started, and the writing of the next frame data is started from the address space of the remaining eight slices or more. At this time, the reading address of the one frame and the next frame are read. Data is read and written while the write address shifts by 8 slices or more, and the address space that has been read is overwritten continuously while maintaining the address space of 8 slices, and this is performed cyclically. ,
The image decoding apparatus according to the present invention, when writing data in the predictive frame memory, provides a predetermined address space between the frame signal and the next frame signal so as to overwrite the same frame memory, and the writing means as described above. Since a reading means for reading the stored frame signal is provided, the memory capacity for one frame + 8 slices is 4147200 + 1105920 bits in the NTSC system and 4976640 + 1105920 bits in the PAL system. The maximum buffer capacity of the profile defined by MPEG2 is 1835008bit.
7088 128bit in NTSC system and 79 in PAL system
17568bit, SP @ ML in MPEG2 specifications
In the (simple profile @ main level) specification, one NTC and PAL system each have 8 Mbit
It has an advantage that a buffer memory and a prediction frame memory can be constructed on the dynamic RAM.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration diagram of an embodiment of the present invention.

FIG. 2 is a diagram showing a method for writing to a prediction frame memory.

FIG. 3 is a diagram showing a write / read timing to a predicted frame memory.

FIG. 4 is a block diagram showing a configuration example of a conventional image decoding device.

[Explanation of symbols]

 10 Memory Accumulation Means 11 Buffer Memory Control 12 Buffer Memory 20 Decoding Means 21 Variable Length Decoder 22 Scan Converter 23 Inverse Quantizer 24 Inverse DCT Unit 25 Motion Compensated Image Reproducing Unit 25A Overwriting Means 25B Reading Means 26 Prediction Frame Memory 278 Address space over slices 30 Address control unit 100 Input bit stream 200 Reproduced image

Continuation of the front page (51) Int.Cl. ⁶ Identification number Office reference number FI Technical indication location H03M 7/36 9382-5K G06F 15/66 330 D (72) Inventor Takayuki Kobayashi 4-36 Yoyogi, Shibuya-ku, Tokyo No. 19 within Graphics Communications Laboratories, Inc. (72) Inventor Shigeru Komatsu 4-36-19 Yoyogi, Shibuya-ku, Tokyo Within Graphics Communications Laboratories, Inc. (72) Inventor Ryuji Nishito Tokyo 4-36-19 Yoyogi, Shibuya-ku, Graphics Communications Laboratories Co., Ltd. (72) Inventor Tomoyuki Shindo 4-36-19 Yoyogi, Shibuya-ku, Tokyo Within Graphics Communications Laboratories (72) Inventor Norihiko Nagai 4-36-19 Yoyogi, Shibuya-ku, Tokyo Graphics Communications Laboratories, Inc.

Claims (2)

[Claims] 1. A method for decoding an image by inputting an input bitstream representing an encoded image using forward prediction, wherein when writing data to a prediction frame memory, an address space for storing one frame data. And an address space of 8 slices or more are provided, and after writing one frame of data, reading for displaying one frame is started.
Further, writing of the next frame data is started from the remaining address space of 8 slices or more, and at this time, the read address of one frame and the write address of the next frame are shifted by 8 slices or more to read and write data. An image decoding method characterized by executing the operation, overwriting continuously after the address space for which reading has been completed while maintaining the address space for 8 slices, and performing this cyclically. 2. An apparatus for decoding an image by inputting an input bitstream representing an encoded image using forward prediction, when writing data to a prediction frame memory, and an address space for storing the frame data. An image decoding apparatus comprising: an overwrite unit for providing an address space of 8 slices or more to overwrite the same frame memory; and a read unit for reading the frame signal written as described above.