JPH08137748A - Computer having copyback cache and copyback cache control method - Google Patents

Abstract

(57) [Summary] [Purpose] To improve performance by suppressing the writing back of an originally unnecessary cache block to the main memory. A computer having a copy-back type cache memory 20 managed in cache block units, wherein the contents of the cache block are used as a status for managing the cache memory 20.
The data indicating that the data is in the write-only state that can be written in the same cache block without writing back to the cache block is set in cache block units, and the contents of the cache block are stored in the main memory 1 according to a predetermined condition.
When the data needs to be written back to 2, if the data indicating that the corresponding cache block is in the write-only state is set, the cache control unit 22 that does not write back to the main memory is provided. .

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer having a copyback cache and a copyback cache control method.

[0002]

2. Description of the Related Art Generally, in a computer, a cache memory is provided between a processor and a main memory so that the speed difference between the processing speed in the processor and the read / write speed with respect to the main memory is filled.
The cache uses the locality of the program to hold recently accessed instructions and data to improve the apparent memory access performance.

The cache memory is composed of a data area that holds the data body and a tag area that holds the address and access history of the data. Each area is divided into a plurality of blocks (cache blocks) and managed.

The data in the cache memory must be finally written back to the main memory.
A copy-back method is one of the write-back methods.
The copyback cache that performs writeback by the copyback method has the following functions.

(1) Copyback cache The copyback cache provided in the computer is
Each cache block (tag area) has a flag (dirty bit) indicating whether or not the data stored in the cache block has been rewritten. If the dirty bit determines that the data in the cache block that is evicted from the cache is dirty (rewritten) when the data in the cache block is replaced, this data is stored in the main memory. Write back. The reason for writing back to the main memory is to prevent the change result from being lost the next time this block is referenced.

However, a variable in a program in many programming languages is not referenced until a new value is set after the variable is last referenced (this is called a "dead" period). Has the property of being relatively long. If the data in the corresponding cache block is evicted from the cache while this variable is "dead", writing back to the main memory, which is not necessary originally, will occur.

For variables in the "dead" period, invalidation of the cache block can suppress the occurrence of write-back, but when a write to a dead variable occurs, the cache is cached. Since it becomes a mistake, reading from the main memory will occur and the processing time will increase, which is not effective.

(2) Fault Tolerant Using Copy Back Cache A fault tolerant computer can be realized by using a copy back cache. In this fault-tolerant computer, when it is necessary to write back data from the cache to the main memory, at the same time, the context of the processor (state in which the processor executes instructions such as values held by registers etc.) and all the writing The changed cache block data is written back to the main memory (this operation is called a checkpoint).

Immediately after the checkpoint, the values of the data stored in the main memory and the data stored in the cache completely match. When a processor fails, another processor uses the context of the processor written back to the main memory by the checkpoint to re-execute the process from the time when the checkpoint is generated. The value of the cache memory of the processor in which the failure has occurred is lost, but since it matches the main memory at the checkpoint, the operation can be executed without contradiction.

In such a fault-tolerant computer, the processing time at the checkpoint is greatly influenced by the number of cache blocks to be written back to the main memory, so reducing unnecessary writeback blocks is very important in terms of performance. Has become. However, in reality, there is cache block write-back that is not originally necessary, which causes performance degradation.

[0011]

As described above, in the computer having the conventional copy-back cache, there is a case where the originally unnecessary data is written back to the main memory, and the performance is deteriorated. Further, even in a fault tolerant computer using the copyback cache, there is a cache block write-back that is not originally necessary at the checkpoint, which causes performance degradation.

The present invention has been made in consideration of the above circumstances, and has a copyback cache capable of improving the performance by suppressing the writing back of an originally unnecessary cache block to the main memory. An object of the present invention is to provide a computer and a copyback cache control method.

[0013]

According to the present invention, there is provided a computer which has a cache memory managed in cache block units and which writes back the contents of an updated cache block to a main memory according to a predetermined condition. As a status for managing the cache memory, data indicating a write-only state in which the contents of the cache block can be written to the main memory without being written back to the main memory is set for each cache block. , When it is necessary to write back the contents of the cache block to the main memory under the above-mentioned predetermined conditions, if the data indicating that the corresponding cache block is in the write-only state is set, the data is written back to the main memory. Equipped with cache control means not to perform And wherein the door.

The cache control means sets the write-only state based on a cache control instruction output by execution of a program.
The cache control instruction is embedded in an appropriate position of the program when the compiler compiles the program.

Further, the computer realizes a fault-tolerant computer that writes back the data of all rewritten cache blocks in the cache memory to the main memory together with the processor context by the checkpoint. The writing back is performed based on the data indicating the write-only state.

Further, according to the present invention, in a computer having a cache memory managed in cache block units and writing back the contents of the updated cache block to the main memory according to a predetermined condition, the contents of the cache block The data indicating that it is in the write-only state that can be written to the same cache block without writing it back to the main memory is set as the status for managing the cache memory, and the data indicating that it is in the write-only state is set. When a write request for a cache block causes a cache hit, the data in the cache block is written without being written back to the main memory, the write-only state is canceled, and data indicating the write-only state is set. Cashe If the read request for click results in a cache hit, and executes the predetermined processing.

[0017]

According to such a configuration, the data stored in the cache block of the copyback cache corresponding to the cache block of the copyback cache is last referenced, and
After that, during a period in which no reference is made until a new value is written, a flag indicating the “write-only state” is set in the tag area, so that writing back to the main memory can be suppressed.

Further, in order to put the cache block into the "write-only state", the cache control instruction is issued from the processor. By embedding the cache block in the program at the time of compiling the program, the cache block is "write-only" properly and effectively. State "is set. That is, for example, with respect to the variables in the program, the compiler can accurately determine whether the value stored in the variable is read by the subsequent execution of the program at the time of execution of the certain program.

In the fault-tolerant computer, the operation of writing back all the rewritten cache block data in the cache to the main memory by the checkpoint is executed, but this processing requires a lot of time. Therefore, the cache block that originally does not need to be written back to the main memory is "write-only".
By doing so, the processing time at the checkpoint can be shortened and the system performance can be improved.

[0020]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a computer according to the embodiment. As shown in FIG. 1, the computer according to the present embodiment is provided with a cache memory 20 of a copyback system between a CPU 10 and a main memory 12.

The cache memory 20 has a cache control unit 22 and a storage unit 24. The storage unit 24 includes a data memory (area) 24a that holds the data body and a tag memory (area) 24b that holds the address (address tag) of the data and the access history (status for managing the cache block).

The CPU 10 causes the cache control unit 22 to
Data is exchanged with the storage unit 24 by passing an address and a cache control signal. Main memory 12
Stores programs and data.

The cache control unit 22 has a tag area 24b.
The cache access is controlled in cache block units based on the contents stored in. Storage unit 2
In the tag area 24b of No. 4, for each cache block, a status flag (dirty flag) indicating whether the address tag and the data have been rewritten, and a write indicating whether the status is a write-only state (details will be described later). The dedicated status flag is stored.

When the CPU 10 secures an area for writing data (for example, allocation of a stack area), the write-only state flag is explicitly linked with the designation of the address or by a predetermined instruction embedded in the program. First, it is set in the corresponding cache block. Further, in the cache block in which the write-only status flag is set, the same writing is executed as usual, but at the time of copy back, the data in the cache block is written back to the main memory 12. Absent.

That is, local data exists in a program, for example, a variable used only when executing a certain function, or a variable used in a certain process but not referred to by another process. . Also,
There is data handled in the stack area that is temporarily secured. This kind of data has the property that it is not referenced elsewhere, and the period after it is last referenced is not referenced until a new value is set (“dead” period). Therefore, it is sufficient if it can be handled on the cache, and it is not necessary to write it back to the main memory 12 during the "dead" period.

In the present invention, as described above, the cache block in which the data that originally does not need to be written back to the main memory 12 is stored is linked with the operation of the CPU 10,
Alternatively, the write-only state flag is explicitly set by an instruction to put the corresponding cache block in the write-only state so that write-back does not occur in the main memory 12 when replacement or the like becomes necessary. .

Next, the operation of this embodiment will be described with reference to the flow charts shown in FIGS. Here, a case where a cache block that originally stores data that does not need to be written back to the main memory 12 is explicitly set to the write-only state will be described with reference to FIG. 2 (in synchronization with the operation of the CPU 10). When set, it will be described later using the stack operation as an example).

The CPU 10 puts the cache block corresponding to the specific address into the write-only state.
The address and the request signal are output to the cache control unit 22 (step A1). For example, a local variable
When a variable that is not referred to until a new value is set after the last reference enters a "dead" period, the CPU 10 puts the cache block in which the data of this variable is stored into a write-only state. Set.

A request signal for setting the write-only state is output according to a predetermined instruction embedded in the program. This instruction is, for example, embedded in an appropriate execution position according to the content of the program when the program is compiled (details will be described later).

The cache control unit 22 examines the tag area 24b of the storage unit 24 and determines whether or not there is a cache block corresponding to the address from the CPU 10 (step A2).

If there is a corresponding cache block, the cache control unit 22 sets the write state exclusive flag corresponding to the cache block (step A3).

The cache block thus set in the write-only state is controlled as shown in FIG. When there is a write request from the CPU 10 to the cache control unit 22 (step B1), the cache control unit 22 checks the tag area 24b of the storage unit 24, and the CPU
It is determined whether or not there is a cache block corresponding to the address from 10 (step B2). If there is a cache hit, the cache control unit 22 writes to the corresponding cache block in the data area 24a (step B3).

At this time, the cache control unit 22 sets (indicates that it has been rewritten) the dirty flag corresponding to the write-target cache block and resets the write-only state flag (step B).
4). That is, since the data may be rewritten to the main memory 12 by being rewritten, the write-only state is released (when the variable is out of the "dead" period).

Further, from the CPU 10 to the cache control unit 2
When there is a read request to the memory 2 (step B5), the cache control unit 22 checks the tag area 24b of the storage unit 24 and determines whether or not there is a cache block corresponding to the address from the CPU 10 (step B6). ).
If there is a cache hit, the cache control unit 22
Checks whether the write-only status flag is set for the corresponding cache block (step B
7).

If the write-only status flag is not set, the cache controller 22 reads the data from the corresponding cache block and returns it to the CPU 10 (step B8).

On the other hand, when the write-only status flag is set, the cache control unit 22 returns the program error status to the CPU 10 (step B9).
That is, even though the target cache block is a local variable that is not referenced by other processing, and the variable has entered the "dead" period and has been placed in the write-only state, the read request is still If there is, it is regarded as a program error and the error is notified.

When a write request or a read request is issued from the CPU 10 to the cache control unit 22 and a mishit occurs, the cache control unit 22 determines the cache block to be replaced if the replacement is necessary (step B10). , B11).

Here, when the write-only status flag is not set and the dirty flag is set for the cache block to be replaced, the cache control unit 22 sets the cache block of the corresponding cache block. The data is written back to the main memory 12, and the data to be accessed is written to the same cache block (steps B12 to B15).

On the other hand, when the write-only status flag is set for the cache block to be replaced, the cache control unit 22 sets the dirty flag for the data of the corresponding cache block. Is not written back to the main memory 12. The cache control unit 22 writes the data to be accessed in the same cache block (steps B12 and B1).
5).

In this way, by setting the write-only status flag for the cache block storing the variables in the "dead" period, even if the cache block is to be replaced, it is not necessary for the main memory 12. Since the write back is suppressed, the time required for memory control can be shortened and the system performance can be improved.

In the execution of the program, if there is a read request for an undefined variable that is not originally referred to, that is, a write-only cache block, it is detected as a program error. It can also be used for program debugging.

Next, the case where the write-only state is set in conjunction with the operation of the CPU 10 will be described by taking a stack operation as an example. By the instruction "alloc (<size>)" for allocating a stack area, the CPU 10 newly creates an area of <size> on the stack (indicated by the stack pointer SP) in the state of FIG. 4A. It is assumed to be secured as shown in FIG. After the processing is completed, the stack in the state of FIG. 4C is reduced by <size> by the instruction “free <size>” for releasing the stack area as shown in FIG. 4D. It shall be.

When executing the "free" instruction, the CPU 1
0 outputs to the cache control unit 22 a request for putting each address in the released area into a write-only state. In response to a request from the CPU 10, the cache control unit 22 sets the write-only state flag corresponding to the relevant cache block and puts it in the write-only state. That is, in the released area, there is data that is not referred to by others and does not need to be written back in the main memory 12.

As a result, when the stack area is secured on the area previously released by the "alloc" instruction again, the possibility of a cache hit at the time of writing data for initialization is equivalent to that of the conventional case. And even if the released area becomes a replacement target, the main memory 1
Writing to 2 does not occur.

In this way, the corresponding cache block can be put into the write-only state in synchronization with the operation of the CPU 10. Next, a specific example of a compiler of a program executed in a computer capable of setting a write-only state in a cache block as described above will be described.

Here, the CPU 10 in this embodiment is
The "lwo" (load to write only) instruction is newly supported. The "lwo" instruction is one of the "load" instructions, but at the same time as loading the value from the main memory 12, if the data is in the storage unit 24 and the dirty flag is set, this data is This is an instruction to put a cache block to be stored in a write-only state.

The compiler statically sets the variable to the variable based on the survival information of the program variable (information indicating whether the value stored in the variable at the time of execution of a certain program is read by the subsequent execution of the program). The reference is parsed to determine when the variable is "dead", that is, the position of the last reference that will not be referenced until a new value is set.

The compiler uses the normal "loa" at the reference position for the variable that matches the above condition.
Instead of the "d" instruction, the cache block that stores the target variable is replaced with the "lwo" instruction that puts it in the write-only state.

Therefore, in the period when the variable is "dead", the cache block in which this variable is stored is explicitly set to the write-only state by the "lwo" instruction, so that it may be written back to the main memory 12. Therefore, the amount of copy back generated can be reduced.

In this way, the compiler can more strictly determine the state of the variable being "dead" based on the survival information of the variable, so that it can be executed by the computer that can set the cache block to the write-only state. When a program that compiles is compiled, the cache block corresponding to the "dead" period of the variable is set to "write-only state" to suppress the write-back of data that does not need to be reflected in the main memory. be able to. Therefore, the system performance can be improved.

Next, a fault tolerant computer realized by using the copyback cache will be described. It is assumed that the fault-tolerant computer according to the present embodiment uses the above-described copyback cache in which the write-only state can be set in the cache block and the compiler that embeds the instruction for making the write-only state at compile time. .

In the fault-tolerant computer realized by using the copy-back cache, when write-back from the cache memory 20 to the main memory 12 becomes necessary, the context of the CPU 10 (processor such as a value held by a register etc.) is simultaneously processed. The state of executing the instruction) and the data of all rewritten cache blocks in the data memory 24a are stored in the main memory 12
Write back to (flash operation).

When a failure occurs, the context and data saved in the main memory 12 are written back by the checkpoint, and re-executed by another normal CPU that has been multiplexed from the time of the previous checkpoint. Avoid obstacles.

In the cache memory 20 of this embodiment, the cache block in which data that need not be written back to the main memory 12 is stored is set to the write-only state. Therefore, during the flush operation, the data in the cache block in the write-only state is dirty (rewritten) in the main memory 1
It is not written back to 2.

In this way, in the fault tolerant computer, by using the copyback cache according to the present invention, all the cache blocks that do not need to be written back to the memory can be set to the "write only state". The time required for checkpoint generation, which is the biggest problem in the system, can be greatly reduced.

In the above embodiment, the program error status is returned when a read request is made to a cache block in which the write-only status flag is set, but a predetermined specific You may make it perform a process.

[0057]

As described in detail above, according to the present invention, the write-back state to the main memory can be suppressed by setting the write-only state for an originally unnecessary cache block. The time required for control can be shortened and the system performance can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a computer according to an embodiment of the present invention.

FIG. 2 is a flowchart for explaining a process when a cache block is explicitly set to a write-only state in this embodiment.

FIG. 3 is a flowchart for explaining a process for a cache block set to a write-only state in this embodiment.

FIG. 4 is a diagram for explaining a case where a write-only state is set in association with the operation of the CPU 10 in the present embodiment.

[Explanation of symbols]

10 ... CPU, 12 ... Main memory, 20 ... Cache memory, 22 ... Cache control unit, 24 ... Storage unit, 24
a ... Data memory (area), 24b ... Tag memory (area).

Claims (4)

[Claims] 1. A computer having a cache memory managed on a cache block basis and writing back the contents of an updated cache block to a main memory according to a predetermined condition, as a status for managing the cache memory. , The data indicating that the cache block is in a write-only state that can be written to the main memory without being written back to the main memory is set for each cache block, and the content of the cache block is set to the main memory according to the predetermined condition. When it is necessary to write back data to the main memory, cache control means is provided that does not write back to the main memory if data indicating that the corresponding cache block is in the write-only state is set. Computer. 2. The cache control means sets the write-only state based on a cache control instruction output by execution of a program, and the cache control instruction is appropriate for the program when the compiler compiles the program. The computer according to claim 1, wherein the computer is embedded in various positions. 3. The computer realizes a fault-tolerant computer that writes back the data of all rewritten cache blocks in the cache memory to the main memory together with the context of the processor by a checkpoint. 2. The computer according to claim 1, wherein write-back is performed based on the data indicating the write-only state. 4. A computer having a cache memory managed in cache block units, wherein the contents of the updated cache block are written back to the main memory according to a predetermined condition, and the contents of the cache block are stored in the main memory. Data that can be written to the same cache block without writing back is set as the status for managing the cache memory, and for the cache block to which the data that is write-only is set When a write request results in a cache hit, the data in the same cache block is written without being written back to the main memory, the write-only state is canceled, and the cache block for which the data indicating the write-only state is set Read A copy-back cache control method, wherein predetermined processing is executed when a cache request hits a protruding request.