JPH08139918A - Image processor - Google Patents

Abstract

PURPOSE: To simplify the circuit configuration for processing a binary and intermediate image in an image by inputting image data of a prescribed value or below to a 1st image processing system and image data of a prescribed value or over to a 2nd image processing system as processing objects respectively. CONSTITUTION: A data separate section 620 of an image processing section 160 divides the image of one page into a binary section such as a character and line drawing and an intermediate tone component such as a photograph. Data of maximum density 63 in excess of a prescribed value 62 in image data D610 having 64-gradation of 0-63 are given to a data delay section 640 as data D620b corresponding to the intermediate tone component. Thus, each picture element is shared defending on the density and a maximum density is allocated to the character of the image read by an image reader in the stage of gradation conversion. Since the data representing the maximum density are recognized as data corresponding to the character image, the character image and the intermediate tone image are separated with simple circuit configuration.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus for concurrently performing different image processing on a binary image and a halftone image.

[0002]

2. Description of the Related Art In an image forming apparatus such as a page printer, a digital copying machine, a facsimile machine, etc., as a gradation reproducing method for outputting a halftone image on a paper,
An area gradation method such as a dither method or a density pattern method is used.

For example, in the dither method, one pixel of an original image is associated with a threshold value of each dot of an m × n matrix in a one-to-one correspondence, and a number of dots corresponding to a gradation level is output. Is.

On the other hand, when gradation reproduction processing is performed on a binary image such as a character or a line drawing, moire fringes appear in the reproduced image or the edges or thin lines of the character are cut off (edge breakage).
Is likely to occur. In addition, it is preferable to perform smoothing (smoothing) for smoothing the contour, particularly for a curved portion or an oblique line of an enlarged character.

From this, it can be considered that the original image is divided into a binary portion and a halftone portion, and preferable processing is performed for each. However, in practice, it is difficult to reliably distinguish between the binary part and the halftone part.

Therefore, in general, the conventional image processing apparatus is
The two-dimensional window (matrix) in which the smoothing coefficient is defined is used to perform the filtering process on the multi-valued image data, and then perform the tone reproduction process. That is, the data value (density) of the pixel of interest
Are sequentially performed by a smoothing process for correcting by a calculation based on the density of each pixel in the window and a smoothing coefficient, and a gradation reproduction process for converting the corrected multivalued data into data for gradation reproduction. Was configured.

Further, conventionally, in a system in which an image forming apparatus (host) such as a computer or a word processor and a printer are connected, area discrimination data is added to the image data on the host side, and the printer side is based on the area discrimination data. There is proposed a method in which an image is separated into a binary part and a halftone part and different image processing is performed on each part (Japanese Patent Laid-Open No. 30354/1993).

[0008]

When the smoothing process by filtering is performed as described above, the image processing circuit is complicated in order to realize the operation of multiplying the multi-valued data value by the coefficient, and the cost is reduced. There was a problem that it was difficult. Further, it is necessary to optimize the smoothing coefficient in consideration of the influence on the gradation reproduction processing in the subsequent stage.

When the area discrimination data is added to the image data, there is a problem that the data processing becomes complicated and it is disadvantageous in versatility. The present invention has been made in view of these problems, and simplifies a circuit configuration for applying image processing suitable for each of a binary area and a halftone area in an image, and reduces the image processing apparatus. The purpose is to reduce the price.

[0010]

According to a first aspect of the present invention, there is provided an image processing apparatus which performs gradation reproduction processing on multi-valued image data indicating the density of each pixel obtained by subdividing an image. 1
An image processing system, a second image processing system for binarizing the image data and performing a smoothing process on the binary image data, and the image data having a certain value or less for the first image processing system. To the second image processing system and the image data output from the first image processing system and the data separating unit that outputs the image data exceeding the predetermined value to the second image processing system. And a data synthesizing unit.

[0011]

The data separating section sorts the image data corresponding to each pixel into the first image processing system and the second image processing system according to the magnitude of the data value of one pixel.

Image data having a predetermined value or less is input to the first image processing system as a processing target. Further, image data exceeding a certain value is input to the second image processing system as a processing target.

The image data processed by the first image processing system for gradation reproduction and the binary image data processed by the second image processing system for smoothing are combined by a data combining section. It is output to the subsequent device.

[0014]

1 is a block diagram showing the configuration of a page printer 1 having an image processing section 160 according to the present invention.

The page printer 1 has print data (image information and command) D0 input from an external host.
And an engine (image forming system) 200 for printing an image corresponding to the output image data D2 on a sheet.

The data processing system 100 controls C for controlling this.
A ROM that mainly stores the PU 110 and stores the program
120, DRAM for temporarily storing various data
130, a host interface 140 for communication with the host, a line buffer 150 for data transfer, an image processing unit 160 for improving image reproducibility, an engine 20.
It is composed of an engine interface 170 for communication with 0, a data bus BD, an address bus BA and the like. The CPU 110 plays the role of a print controller that manages the overall operation of the page printer 1.
The DRAM 130 is also used as a reception buffer, a frame buffer (bitmap area), and the like.

The CPU 101 sequentially reads the print data D0 from the reception buffer and analyzes it, interprets the print instruction content in, for example, the page description language, and the DRAM 13
Bit map expansion such as a character code is performed on the frame buffer area within 0. At that time, regarding a binary image such as a character or a line drawing, the maximum value is the data value indicating the density of each pixel.

When the bit map expansion for one page is completed, the CPU 101 reads the image data D from the DRAM 130.
1 is read and sent to the image processing unit 160. Image processing unit 1
60 performs gradation reproduction processing and smoothing processing on the image data D1 as described later, and outputs the processed binary output image data D2 to the engine interface 170. The output image data D2 is transferred to the engine 200 via the engine interface 170.

On the other hand, the engine 200 has an image forming unit for carrying out an electrophotographic process and a paper carrying system for carrying paper (recording paper), and is constructed so that full-color printing is possible. When the output image data D2 is input from the data processing system 100, latent image formation (exposure) is started, and the sheet moves from the transfer position to the fixing position in accordance with the subsequent image forming process (developing, transferring, fixing). After that, they are sequentially conveyed to the discharge port. When outputting a full-color image, Y (yellow), M (magenta), C (cyan),
A toner image of each developing color of K (black) is sequentially formed one by one, and toner images of four colors are superposed on the paper.

FIG. 2 is a perspective view showing the outline of the scanning optical system 11 incorporated in the engine 200. Engine 200
The light source for the exposure process in FIG. The semiconductor laser 21 is controlled based on the output image data D2 sent from the data processing system 100 and outputs a binary-modulated light beam. Light beam
The light is collimated by the collimator lens 22 and is deflected in the main scanning direction by the rotary polygon mirror 23. The polarized light beam forms an image forming lens 24 called an fθ lens.
Photosensitive drum (latent image carrier) rotating in one direction by
An image is formed on 12 and beam scanning in line-sequential format is performed. At the time of this beam scanning, the light at the beginning of each scanning line of the light beam is reflected by the mirror 25 and guided to the detector 26. The detection signal from the detector 26 is used to set the timing of the line clock SH that is a synchronization signal for H-direction scanning (sub-scanning).

FIG. 3 is a block diagram of the image processing section 160. The image processing unit 160 has a gradation conversion unit 610, a data separation unit 620, a binarization unit 630, a data delay unit 640, an area gradation processing unit 650, a smoothing processing unit 660, and a data synthesis unit 670. . Data delay unit 640
And the area gradation processing unit 650, the first image processing system G1
And a binarization unit 630 and a smoothing processing unit 66.
A second image processing system G2 is constituted by 0 and.

The gradation conversion unit 610 is composed of a ROM or the like which stores conversion table data, and converts the input 8-bit (256 gradation) image data D1 into 6-bit (64 gradation) image data D610. . The image data D1 which is the input data includes the density of each pixel of the original image "0 to 25".
5 ”, and 8 bits are serially input for each pixel from the line buffer 150 in the pixel arrangement order of line sequential scanning.

When converting the image data D1 into the image data D610, a value in a certain range on the maximum value side of the image data D1 (for example, "255 to 250") is converted into the image data D61.
It is associated with the maximum value "0" of 0. The image data D610, which is output data, is output in synchronization with the pixel clock SYNCK (see FIG. 5) that defines the transfer cycle of one pixel. The data separation unit 620 outputs one page of an image such as a character or line drawing. It is provided to divide a binary portion and a halftone portion such as a photograph and perform different image processing on each portion. In the present embodiment, the maximum density of "63" in the image data D610 of 64 gradations having values of "0" to "63".
Image data D610 (that is, data exceeding a fixed value “62”) is the image data D620 corresponding to the binary part.
It is sent to the binarization unit 630 as a. Then, the image data D610 of the densities “0” to “62” other than the maximum density (that is, the data of the fixed value “62” or less) is converted into the image data D620b corresponding to the halftone part, and the data delay unit 64 is provided.
Sent to 0. That is, each pixel is sorted according to its density.

Here, the character image often has the maximum density. For example, a character in an image created on a personal computer is usually output as a maximum density area. Further, the characters in the image read by the image reader may not show the maximum density due to some errors, but are assigned to the maximum density at the stage of the gradation conversion described above. Therefore, in this embodiment, the data indicating the maximum density is recognized as the data corresponding to the character image. Thereby, the character image and the halftone image can be separated with a simple circuit configuration.

The image data D610 is the image data D.
When output as 620a, the image data D62
The value of 0b is “0”, and conversely, when the image data D610 is output as the image data D620b, the value of the image data D620a is “0”. Such a function of the data separation unit 620 can be realized by combining a multi-output selector and a logic circuit. For example, the 6-bit data that is the output of the above-described gradation conversion unit 610 is input to the multi-output selector and also to the AND circuit. Then, the output of the AND circuit may be input as the switching signal of the multi-output selector. As a result, when 6 bits are all "1" and other cases,
The data output destination is switched in the multi-output selector.

The binarizing unit 630 converts the 6-bit image data D620a ("63" or "0") into 1 bit ("1").
Alternatively, it is converted into image data D630 of "0") and sent to the smoothing processing unit 660. Also, the data delay unit 640
Delays the halftone image data D620a and sends it to the area gradation processing unit 650.

The smoothing processing unit 660 performs smoothing processing on the binary image data D630. The area gradation processing unit 650 performs area gradation processing on the image data D620a (image data D640) input via the data delay unit 640. Smoothing processing unit 660,
The configurations of the area gradation processing unit 650 and the data delay unit 640 will be described later.

The data synthesizing unit 670 is composed of, for example, a logical sum circuit, and the 1-bit image data D650 and D660 respectively output from the area gradation processing unit 650 and the smoothing processing unit 660 are converted into logical data. The output image data D2 indicating the sum is combined. The output image data D2 is used for binary control of the exposure scanning beam as described above.

FIG. 4 is a block diagram of the area gradation processing unit 650, FIG. 5 is a timing chart of address designation, and FIG. 6 is a timing chart of operation of the shift register 656. 4, the area gradation processing unit 650 includes a pattern ROM 651, an X address counter 653, a Y address counter 654, a color address designating unit 655, and a shift register 656.

The content of the area gradation processing of this embodiment is basically to realize gradation reproduction by a dot concentration type matrix. However, as a pattern of exposure to the matrix area, a method of providing patterns in which the total exposure time is the same and the positions of the exposed portions are different (Japanese Patent Application No. 5-2).
No. 59691 gradation recording method is used, whereby the number of gradations is increased without lowering the resolution.

The pattern ROM 651 is provided as an output density setting means for setting the density of the print image, and stores a large number of exposure patterns (dither patterns) consisting of an m × n matrix corresponding to each gradation level and developing color. are doing. Each of the m × n sections TD forming the matrix is composed of k elements EM.
k is the number of pixel divisions, and in the following, this is 4 (k = 4)
It will be described as.

An exposure pattern group corresponding to one gradation level is designated by the image data D640, and an exposure pattern group suitable for the developing color is designated by the color address AC output from the color address designating section 655. As a result, one exposure pattern is designated. At the same time, 1 of the m × n sections DT that form the specified exposure pattern
One is designated by the X address AX and the Y address AY. Then, 4-bit image data (modulation data) D6 indicating the exposure pattern in one designated section DT
51 is read in synchronization with the pixel clock SYNCK.

The X address AX is the X address counter 6
It is a count value of the pixel clock SYNCK by 53. The X address counter 653 repeats counting within a predetermined value range according to the number of sections DT arranged in the horizontal direction (row direction, horizontal direction, or main scanning direction) of the exposure pattern. For example, the size of the exposure pattern PS is 4 (vertical)
If x4 (horizontal), as shown in FIG. 5, counting in the range of 0 to 3 is repeated.

The Y address AY is the Y address counter 6
This is a count value of the line clock SH by 54. Y
The address counter 654 is a section D arranged in the vertical direction (column direction, vertical direction, or sub-scanning direction) of the exposure pattern.
Counting is repeated within a predetermined value range according to the number of Ts. For example, the size of the exposure pattern PS is 4 (vertical) x 4
If it is (horizontal), counting in the range of 0 to 3 is repeated as shown in FIG.

The maximum count values in the X address counter 653 and the Y address counter 654 are changed according to the color address AD. As a result, the color selection signal S
It is possible to use a matrix having a different size according to the development color indicated by C or change the screen angle, and it is possible to enhance the color reproducibility.

4 read from the pattern ROM 651
The bit image data D651 is the pixel clock SYNC.
It is input to the shift register 656 in synchronization with K. The shift register 656 data-shifts the image data D651 in synchronization with the shift clock 4SYNCK and serially outputs the image data 650 bit by bit as shown in FIG.

The shift clock 4SYNCK is a pulse signal having a frequency four times that of the pixel clock SYNCK. That is, in the area gradation processing unit 650,
Output side data transfer cycle is 1/4 of input side data transfer
Is.

Next, the exposure pattern stored in the pattern ROM 651 will be described. FIG. 7 is a diagram showing an example of the exposure pattern. Exposure pattern PS illustrated in FIG.
The patterns 0 to 11 are patterns corresponding to the gradation levels Z0 to 11 on the low density side among the 64 gradation levels Z0 to 63. Each of the exposure patterns PS0 to PS11 is a 4 × (4 × 4) array in which each section DT of a square matrix consisting of four sections DT in the vertical and horizontal directions is divided into four in the horizontal direction, and each of the four small sections is an element EM. It consists of a size matrix. Each element EM takes a value of "0" or "1". In the figure, each element E
For M, "0" is shown in white and "1" in black. In the case of "0", the semiconductor laser 21 is off,
In the case of "1", the semiconductor laser 21 is on. On the photosensitive drum 12, a portion of the semiconductor laser 21 corresponding to the ON element EM is exposed and its potential is lowered, and toner of a predetermined color adheres to the portion. On the other hand, on the recording paper, the portion corresponding to the element EM in which the semiconductor laser 21 is off remains as the background color (usually white). In the following, the element EM having a value of "0" is replaced with the element EM having a value of "white" (EMW) and "1".
Is called a "coloring element (EMB)".

It should be noted here that 1
The area of the image visualized on the recording paper corresponding to the one coloring element EMB differs depending on whether the element adjacent to the coloring element EMB is the white element EMW or the coloring element EMB, and whether the adjacent positions are left and right. It depends on whether it is up or down.

The reason is that the energy of the light beam is high at the center and becomes lower toward the periphery,
The exposure is line-sequential scanning, and the elements EM in the same row are continuously scanned, while the elements E in different rows are different from each other.
This is because M is discretely scanned with a space between each other.

That is, when the coloring elements EMB are laterally adjacent to each other, the irradiation energies of the light beams are added to each other to increase, and the maximum irradiation energy increases. On the other hand, when the coloring elements EMB are vertically adjacent to each other,
The maximum irradiation energy does not increase. Therefore, even if the number of the coloring elements EMB is the same, in other words, the total exposure time is the same, the maximum irradiation energy is large when the coloring elements EMB are arranged continuously in the lateral direction, and the coloring elements EMB are large. When the EMBs are arranged in the vertical direction, the maximum irradiation energy becomes smaller than that. Therefore, even if the total exposure time is the same, an electrostatic latent image with different irradiation energy is formed on the photosensitive drum 12.

Then, when the electrostatic latent images formed with such different irradiation energies are developed,
Depending on the sensitivity of the photosensitive drum 12 and the magnitude of the developing bias, the toner adheres only to the portion that receives the irradiation energy exceeding a certain threshold value, and the latent image is visualized. As a result, even if the number of coloring elements EMB is the same, the area of the image recorded on the recording paper differs depending on the arrangement position.

By utilizing such a phenomenon, in the printer apparatus 1 of the present embodiment, the positions of the coloring elements EMB are different from each other for a plurality of exposure patterns PS having the same total number of coloring elements EMB. By doing so, recording with different gradations is performed.

FIG. 8 is a block diagram of the smoothing processing unit 660. The smoothing processing unit 660 includes a line buffer 661, a window extraction unit 662, a pattern matching unit 664, a modulation register 665, and a shift register 666, and p × q (for example, 5 × 5).
Performs pipeline-type smoothing processing using the windows.

The line buffer 661 stores the binary image data D630 input from the preceding stage for the required number of lines. The window extraction unit 662 reads the image data D630 corresponding to the pixel of interest and a predetermined number of pixels around it from the line buffer 661 and sends it to the pattern matching unit 664.

The pattern matching unit 664 has a look-up table 6 for associating an input with a smoothing result.
64, and outputs data D663 corresponding to the combination of data values in the window.

The modulation register 665 is provided to optimize smoothing according to the image forming characteristics of the engine 200, and outputs the image data D665 obtained by correcting the data D663.

The shift register 666 is provided to match the data output cycle with the above-described area gradation processing section 650, and the image data D665 is input at a cycle of ¼ and four times for each pixel. Image data D660
Output as

Now, the smoothing processing unit 6 having the above configuration
In 60, for example, when using a 5 × 5 window, when the image data D630 of the line next to the line including the pixel of interest and the next line are stored in the line buffer 661, the peripheral pixels corresponding to the window are displayed. Can be extracted. That is, a data delay of three lines occurs at the stage of storing data in the line buffer 661. Further, when the latch and the like are included, the window extraction unit 6
In the 62, the pattern matching unit 663, and the shift register 666, data delays of 4 pixels, 2 pixels, and 1 pixel occur in order.

On the other hand, in the area gradation processing unit 650, only one pixel of data delay is caused in each of the pattern ROM 651 and the shift register 656 for a total of two pixels. That is, the area gradation processing (first image processing) requires a processing time shorter than the smoothing processing (second image processing) by the data transfer time of (3 lines + 5 pixels).

Therefore, the image processing unit 160 (see FIG. 3) has a data delay unit on the input side of the area gradation processing unit 650 in order to compensate for the difference in the required time between the processes and to adjust the timing of data combination. 640 is provided.

FIG. 9 is a block diagram of the data delay unit 640. The data delay unit 640 is composed of a line delay unit 641 responsible for data delay of 3 lines and a pixel delay unit 642 responsible for data delay of 5 pixels.

The line delay unit 641 has three FIFO memories ME1 to ME3 each having a data capacity of one line.
Consists of First, the delay target image data D620b is F
The data is input to the IFO memory ME1 and then sequentially transferred to the FIFO memories ME2 and ME3. In addition, each FIF
In the O memories ME1 to ME3, the address counter value is reset in response to the input of the line clock SH.

The pixel delay unit 642 uses the pixel clock SYN.
It is composed of a shift register RE1 of 5 steps which performs a shift operation in synchronization with CK. The image data D620b input from the line delay unit 641 is the pixel clock SYNCK.
After being delayed by 5 cycles, the image data D640 is sent to the area gradation processing unit 650.

The data delay unit 640 is replaced by the area gradation processing unit 65.
By providing on the input side of 0, the pixel clock SYNC
You can use a device that operates on K
The cost of the data delay unit 640 can be reduced as compared with the case where the data delay unit 640 is provided on the output side which is required to operate at high speed.

In the above embodiment, the data separation unit 6
The separation threshold in 20 is “62”, and the maximum value is “6”.
Although the example in which the image data D610 of “3” is distributed to the smoothing processing side is shown, the image data D610 of a value in a certain range on the maximum value side (for example, “60 to 63”) is distributed to the smoothing processing side, Image data D610
May be distributed to the area gradation processing side.

In the above embodiment, the contents of the area gradation processing and the smoothing processing can be variously changed.
For example, in reproducing the gradation, the output image data D2 may be generated by a normal dither method without dividing the pixel, or the IH method of performing pulse width modulation may be used.

[0058]

According to the present invention, it is possible to simplify the circuit configuration for applying image processing suitable for each of the binary area and the halftone area in the image, and the image processing apparatus can have a low cost. The price can be increased.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a page printer having an image processing unit according to the present invention.

FIG. 2 is a perspective view showing an outline of a scanning optical system incorporated in an engine.

FIG. 3 is a block diagram of an image processing unit.

FIG. 4 is a block diagram of an area gradation processing unit.

FIG. 5 is a timing chart of address designation.

FIG. 6 is a timing chart of the operation of the shift register.

FIG. 7 is a diagram showing an example of an exposure pattern.

FIG. 8 is a block diagram of a smoothing processing unit.

FIG. 9 is a block diagram of a data delay unit.

[Explanation of symbols]

 160 image processing unit (image processing device) 620 data separation unit 650 area gradation processing unit 660 smoothing processing unit 670 data synthesis unit D630 binary image data D610 multi-valued image data G1 first image processing system G2 second image processing system

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location H04N 1/405 1/409 1/407 G06F 15/68 320 A H04N 1/40 B 101 C 101 D 101 E

Claims (1)

[Claims] 1. A first image processing system for performing gradation reproduction processing on multi-valued image data indicating the density of each pixel obtained by subdividing an image; and binarizing the image data. A second image processing system for performing a smoothing process on the value image data; outputting the image data of a fixed value or less to the first image processing system; and outputting the image data exceeding the fixed value to the first image processing system. A data separation unit for outputting to two image processing systems, and a data combining unit for combining the image data respectively output from the first image processing system and the second image processing system. Image processing device.