JPH08148996A - Pll circuit - Google Patents

Abstract

PURPOSE: To realize the PLL circuit which is operated around a set frequency when the center frequency is set once. CONSTITUTION: A phase comparator 101 compares a clock 2 being an oscillated output signal from a voltage controlled oscillator 108 whose oscillating frequency is changed in response to a control voltage with a clock 1 being a reference signal. A control voltage generating circuit 106 generates a control voltage in response to the phase comparison signal 3 and a bias voltage 7 from an external setting circuit 107. The external setting circuit 107 controls the bias voltage 7 so that an oscillating frequency of the voltage controlled oscillator 108 is kept constant against a change in ambient temperature. Thus, after the center frequency is once set, the oscillated frequency is generated around the set frequency even when ambient temperature is subject to change.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL circuit, and more particularly to a variable frequency PLL circuit capable of handling a plurality of types of input clocks.

[0002]

2. Description of the Related Art Conventionally, a variable frequency type PLL circuit of this type has N highly stable N (N is an integer of 2 or more, and the same below) having different free-run frequencies that oscillate at a center control voltage (center control voltage). The above-mentioned voltage-controlled oscillator is provided, and these are switched and selectively used to cope with N kinds of input clocks. This conventional PLL circuit will be described with reference to the drawings.

FIG. 7 is a block diagram showing a structure of a conventional PLL circuit, and shows a structure of a frequency variable type PLL circuit which can cope with two kinds of clocks. In the figure, a conventional PLL circuit includes two voltage controlled oscillators (VCOs) 102 and 103, a selection circuit 104 that selectively outputs the oscillation outputs 4 and 5, and a control circuit that controls the selection circuit 104. 105 and the selection circuit 104
Phase comparator 10 for comparing the phases of the output clock 2 which is the output signal of the input signal 1 and the input clock 1 which is the reference signal and sending out the phase comparison signal 3 which is the control voltage having a value corresponding to the phase difference.
1 is included.

According to such a configuration, either one of the two voltage controlled oscillators 102 and 103 and the phase comparator 101 are provided.
Well-known PLL (Phase Locked Loo)
p) is configured, and the output signal 2 synchronized with the clock 1 is transmitted. The voltage controlled oscillator whose oscillation frequency changes according to the control voltage may be configured, for example, by adding a variable capacitance diode in parallel to the tuning capacitor of a well-known LC oscillation circuit and applying the control voltage thereto.

The operation of the above-mentioned PLL circuit will be described with reference to FIG. 8 as well. FIG. 8 is a waveform diagram showing the modulation sensitivity of each voltage controlled oscillator in the PLL circuit of FIG. 7, and shows the relationship between the control voltage applied to each voltage controlled oscillator and the oscillation frequency.

In the figure, the characteristic of the voltage controlled oscillator 102 and the characteristic of the voltage controlled oscillator 103 with respect to the change of the phase comparison signal 3 are indicated by reference numeral 12 and 13, respectively.

First, when the frequency of the input clock 1 is f02, the selection condition of the control circuit 105 is set to the voltage controlled oscillator 102 side by an external operation. The selection circuit 104 selects the oscillation frequency 4 of the voltage controlled oscillator 102 by the control signal 6 and outputs it as the output clock 2.

The phase comparator 101 compares the phases of the input clock 1 and the output clock 2. The phase comparison signal 3 as the result of the phase comparison is input to the voltage controlled oscillators 102 and 103, and the oscillation frequency of each oscillator is controlled.

The voltage amplitudes V01 to V11 of the phase comparison signal 3 are in the frequency fluctuation range H12 (f21 to f21) of the voltage controlled oscillator 102.
It corresponds to 22). When the phase of the output clock 2 leads the phase of the input clock 1, the phase comparison signal 3 causes the VCO control voltage 8 to approach V / 2 by V01.
It is controlled in the direction (direction of arrow Y01). That is, the oscillating frequency of the voltage controlled oscillator 102 is lowered and controlled to approach f02.

On the contrary, when the phase of the output clock 2 is delayed from the phase of the input clock 1, the phase comparison signal 3
Thus, the VCO control voltage 8 is controlled in the V11 direction (direction of arrow Y11) so as to approach V / 2. That is, the oscillating frequency of the voltage controlled oscillator 102 is increased and controlled so as to approach f02.

By repeating the above two operations, the phase synchronization between the input clock 1 and the output clock 2 is established.

When the frequency of the input clock 1 is f01, the selection condition of the control circuit 105 is set to the voltage controlled oscillator 103 side by an external operation. The voltage amplitudes V01 to V11 of the phase comparison signal 3 correspond to the oscillation frequency range H13 (f11 to f12) of the voltage controlled oscillator 103.

In response to the control signal 6 from the control circuit 105, the selection circuit 104 causes the oscillation frequency of the voltage controlled oscillator 103 to be 5
Is selected and output as the output clock 2. Then, the phase synchronization between the input clock 1 and the output clock 2 is established through the same synchronization process as described above.

However, in the above circuit configuration, N expensive voltage controlled oscillators are required in order to handle N kinds of input frequencies. Therefore, the price of the PLL circuit as a whole is high, the number of components is large, and a large component mounting space is required.

A circuit that solves this problem is disclosed in Japanese Patent Laid-Open No.
It is disclosed in JP-A-144640 and JP-A-4-101515. Each of these uses a wide band voltage controlled oscillator, and the oscillation center frequency is changed by increasing or decreasing the bias voltage value. According to this configuration, the number of parts is reduced and the component mounting space is not increased.

[0016]

However, the above-mentioned PL is used.
In the L circuit, even if the center frequency is once set by changing the bias voltage value, there is a drawback that the set center frequency shifts as the temperature rises thereafter.

The present invention has been made to solve the above-mentioned drawbacks of the prior art, and an object thereof is to provide a PLL circuit which can always operate centering on the set frequency once the center frequency is set. That is.

[0018]

A PLL circuit according to the present invention comprises a voltage controlled oscillating means whose oscillating frequency changes according to a control voltage, and a phase comparing means for comparing the phases of the oscillation output signal and a reference signal, A PLL circuit including a control voltage generating means for generating the control voltage according to a phase comparison output of the phase comparing means and an externally set bias voltage, wherein the oscillation frequency is constant according to a change in ambient temperature. Bias voltage control means for controlling the change of the bias voltage so as to keep

Another PLL circuit according to the present invention is a voltage-controlled oscillating means whose oscillating frequency changes according to a control voltage, a phase comparing means for comparing the phases of the oscillating output signal and a reference signal, and the oscillating output signal. A synchronization detecting means for detecting a synchronization state between the reference signal and the reference signal; and a phase difference detecting means for detecting a phase difference of the oscillation output signal with respect to the reference signal only when it is detected as asynchronous by the detection result. A bias voltage generating means for generating a bias voltage according to the detected phase difference, and a control voltage generating means for generating the control voltage according to the generated bias voltage and the phase comparison output of the phase comparing means. It is characterized by including and.

[0020]

The phase of the voltage-controlled oscillation output signal whose oscillation frequency changes according to the control voltage and the reference signal are compared. A control voltage is generated according to the phase comparison output and the externally set bias voltage. The bias voltage is controlled to change so as to keep the oscillation frequency constant according to the change in ambient temperature.

[0021]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of a first embodiment of a PLL circuit according to the present invention, and the same portions as those in FIG. 7 are designated by the same reference numerals.

In the figure, the PLL circuit according to the first embodiment of the present invention includes a single voltage control oscillator 108 having a wide band modulation sensitivity capable of oscillating corresponding to N kinds of input clock frequencies, and an output signal of this voltage control oscillator 108. The phase comparator 101 compares the phases of the output clock 2 which is the input signal 1 and the input clock 1 which is the reference signal, and outputs the phase comparison signal 3 which is the control voltage having a value corresponding to the phase difference, and the phase comparison signal 3. A control voltage generation circuit 106 that generates a VCO control voltage 8 according to the bias voltage 7 and an external setting circuit 107 that generates the bias voltage 7 are included. And this PLL
The circuit can cope with N kinds of input clock frequencies by externally setting the bias voltage to the voltage controlled oscillator 108. The voltage controlled oscillator whose oscillation frequency changes according to the control voltage may be configured, for example, by adding a variable capacitance diode in parallel to the tuning capacitor of a well-known LC oscillation circuit and applying the control voltage thereto.

Here, the external setting circuit 107 is provided with a temperature sensor for detecting the ambient temperature (not shown). Further, the external setting circuit 107 includes a voltage controlled oscillator 10 in spite of the temperature change amount and the temperature change.
A table is provided (not shown) that holds the correspondence relationship with the bias voltage value that keeps the oscillation frequency of 8 constant.
Since these temperature sensors and tables are provided,
It is possible to detect the ambient temperature and control the change of the bias voltage according to the detection result. Therefore, once the center frequency is set, the PLL circuit can always be operated centering on the set frequency even if the ambient temperature changes thereafter.

In the table in the external setting circuit 107 described above, the voltage value for keeping the oscillation frequency constant is measured against the increase value of the ambient temperature in advance, and the value is held. It is assumed that Then, the held value in the table is read according to the detected value of the temperature sensor.

In such a configuration, the external setting circuit 107
Is set by an external operation according to N kinds of input clocks, and the bias voltage 7 is output according to this set value and the contents of the above-mentioned table. Control voltage generation circuit 106
Applies to the voltage controlled oscillator 108 a VCO control voltage 8 that oscillates a free-run frequency corresponding to the input clock 1 based on the bias voltage 7.

The phase comparator 101 sends the result of phase comparison between the input clock 1 and the output clock 2 as the phase comparison signal 3 to the control voltage generation circuit 106. In the control voltage generation circuit 106, the phase comparison signal 3
The VCO control voltage 8 corresponding to is applied to the voltage controlled oscillator 108.

Next, the operation of the PLL circuit shown in FIG. 1 will be described with reference to FIG.

FIG. 2 is a waveform diagram showing the modulation sensitivity of the voltage controlled oscillator in the PLL circuit of FIG. In this figure, the same parts as those in FIG. 8 are indicated by the same reference numerals, and the relationship between the control voltage applied to the voltage controlled oscillator 108 and the oscillation frequency is shown. In the figure, the characteristic of the voltage controlled oscillator 108 with respect to the change of the phase comparison signal 3 is 1
Shown at 8.

First, when the frequency of the input clock 1 is f01, the bias voltage 7 is set to the voltage V1 as shown in FIG. The voltage amplitudes V01 to V11 of the VCO control voltage 8 correspond to the frequency fluctuation range H1 (f11 to f12) of the broadband voltage controlled oscillator 108.

Here, when the phase of the output clock 2 leads the phase of the input clock 1, the VCO control voltage 8 generated by the control voltage generating circuit 106 approaches the voltage V1 in the V01 direction (arrow). Control in the Y01 direction).
In other words, the oscillation frequency of the wide band voltage controlled oscillator 108 is lowered and controlled so as to approach f01.

On the contrary, when the phase of the output clock 2 is behind the phase of the input clock 1, the VCO control voltage 8 is controlled in the V11 direction (direction of arrow Y11) so as to approach the voltage V1. That is, the broadband voltage controlled oscillator 10
The oscillating frequency of No. 8 is increased to control it toward f01.

By repeating the above two operations, the phase synchronization between the input clock 1 and the output clock 2 is established. Since the bias voltage 7 is controlled to be changed according to the change in ambient temperature, the PL is always centered around the set frequency.
The L circuit can be operated.

When the frequency of the input clock 1 is f02, the bias voltage 7 is set for the voltage V2. V
The voltage amplitude V21 to V31 of the CO control voltage 8 is in the frequency variation range H2 (f21 to f22) of the wide band voltage controlled oscillator 108.
It corresponds to. Then, the phase synchronization between the input clock 1 and the output clock 2 is established by going through the synchronization establishing process indicated by the arrow Y21 and the arrow Y31 in the same manner as described above.

As described above, since the bias voltage 7 is controlled by changing the ambient temperature by using the wide band voltage controlled oscillator, the PLL circuit can always be operated with the set frequency as the center. That is, the VCO control voltage 8 generated by the control voltage generation circuit 106 based on the phase comparison signal 3 causes the wide band voltage controlled oscillator 10 to operate.
8 is controlled, and the lock state is maintained with respect to the input clock 1.

On the other hand, FIG. 3 is a block diagram showing the configuration of the second embodiment of the PLL circuit according to the present invention, and the same portions as those in FIGS. 1 and 7 are designated by the same reference numerals. This PL
The L circuit is a frequency variable PLL capable of supporting N kinds of input frequencies by automatically setting the VCO bias voltage.
Circuit.

In the figure, the PLL circuit of this embodiment has N
The phase of a single voltage control oscillator 108 having a wide band modulation sensitivity capable of oscillating corresponding to the input clock frequency of a seed, the phase of the output clock 2 which is this output signal and the phase of the input clock 1 which is the reference signal are compared. A phase comparator 101 which sends out a phase comparison signal 3 which is a control voltage having a value corresponding to the phase difference.
And V in accordance with the phase comparison signal 3 and the bias voltage 7.
The control voltage generating circuit 106 for generating the CO control voltage 8 is included.

Further, the PLL circuit of this embodiment operates only when the asynchronous detection circuit 111 which detects the synchronous state of the clock 2 and the clock 1 and the asynchronous state of both clocks is detected by the detection circuit 111. 2 and clock 1
And a bias setting circuit 109 that generates a bias voltage 7 according to the detection result.

In such a configuration, the voltage controlled oscillator 10
8, the phase comparator 101 and the control voltage generation circuit 106 form a PLL. The synchronization process of this PLL is the same as in the case of the first embodiment described above, and therefore its explanation is omitted.

The asynchronous detection circuit 111 uses the input clock 1
The synchronous state (synchronous or asynchronous) with the output clock 2 is detected and output as a detection signal 11. Phase difference detection circuit 1
10 and the phase comparator 110 and the phase comparator 101 are PL
Considering the stability of L, both are controlled so as not to operate at the same time by the detection signal 11 described above.

That is, when the asynchronous detection circuit 111 detects an asynchronous state, the detection signal 11 causes the phase comparator 101 to stop operating and the phase difference detection circuit 110 to operate. When the synchronization is detected, the detection signal 11
Thus, the operation of the phase difference detection circuit 110 is stopped and the phase comparator 101 is operated. That is, the PLL is formed by the phase comparator 101 as described above, but when the phase difference detection circuit 110 is operating, conversely, the phase comparator 1
01 will not work. The detection signal 11 is "H" in the asynchronous state and "L" in the synchronous state.

Now, when the frequency of the input clock is f01 and the frequency of the output clock 2 is f11 (f01> f11), the asynchronous detection circuit 111 outputs the asynchronous detection signal 11 to stop the phase comparator 101, Phase difference detection circuit 11
0 is operated. From the phase difference detection circuit 110, the pulse of the lead signal 10 is not output, but the pulse of the delay signal 9 is output and input to the bias setting circuit 109.

The bias setting circuit 109 sends the bias setting signal 7 corresponding to the phase difference to the control voltage generating circuit 106 based on the pulse of the delay signal 9, and the control voltage generating circuit 10
As the VCO control voltage 8 which is the output of 6 continues to change, the VCO oscillation frequency changes from f11 to f01.

The operation of this PLL circuit will be described with reference to the time chart of FIG.

As shown in FIG. 4, the bias voltage 7 generated by the pulse of the delay signal 9 has a voltage value B01.
To the voltage value B0. The VCO control voltage 8 also changes from V01 to V1 in proportion to the change, and the VCO oscillation frequency changes from f11 to f01. Then, when the pulse of the delay signal 9 stops at time T1, the change of the bias setting signal 7 also stops and the state is held.

Therefore, the VCO control voltage 8 is also maintained in that state (when the frequency of the input clock 1 is f01), and the bias voltage is set so that the free-run frequency of the voltage controlled oscillator 108 becomes f01. .

Next, the asynchronous detection circuit 111 outputs the synchronous detection signal 11 to stop the phase difference detection circuit 110,
This time, the phase comparator 101 is operated. As a result, the control voltage generation circuit 106 is generated based on the generated phase comparison signal 3.
VCO control voltage 8 based on the bias voltage 7 is generated from the voltage control oscillator 108 according to the input clock 1.
Is controlled. As a result, the output clock 2 is kept in synchronization with the input clock 1.

FIG. 5 is a waveform diagram showing the modulation sensitivity of the voltage controlled oscillator in the PLL circuit of FIG. In this figure, the same parts as those in FIGS. 2 and 8 are indicated by the same reference numerals, and the relationship between the control voltage applied to the voltage controlled oscillator 108 and the oscillation frequency is shown. In the figure, the voltage controlled oscillator 10 with respect to the change of the phase comparison signal 3 is shown.
The characteristic of 8 is indicated by reference numeral 18.

As in the case of FIG. 2, when the frequency of the input clock 1 is f01, the bias voltage 7 is the voltage V1.
Set for. Voltage amplitude V01 to V of VCO control voltage 8
Reference numeral 11 corresponds to the frequency variation range H1 (f11 to f12) of the broadband voltage controlled oscillator 108. Then, the phase synchronization between the input clock 1 and the output clock 2 is established by going through the synchronization establishing process shown by the arrow Y01 and the arrow Y11 in the same manner as described above.

Similarly, when the frequency of the input clock 1 is f02, the bias voltage 7 is set for the voltage V2. The voltage amplitude V21 to V31 of the VCO control voltage 8 is in the frequency variation range H2 (f21 to V21) of the wide band voltage controlled oscillator 108.
It corresponds to f22). Then, in the same manner as described above, the arrow Y0
1, the phase synchronization between the input clock 1 and the output clock 2 is established through the synchronization establishment process indicated by the arrow Y21.

In this case, in the first embodiment described above, the bias voltage 7 is controlled to change according to the change in ambient temperature, but in this embodiment, the ambient temperature itself is not detected but is caused by the temperature change. The out-of-synchronization state is detected, and the state is controlled so as to return to the synchronized state.

Further, description will be made with reference to FIG. FIG. 6 is a diagram showing the relationship between the bias voltage and the oscillation frequency of the voltage controlled oscillator in the PLL circuit of FIG.

As shown in the figure, when the detection signal 11 is in the asynchronous state ("H"), the delay signal 9 is sent from the phase difference detection circuit 110. Then, this delay signal 9
Bias voltage 7 generated by the pulse of
The value changes from 01 to the voltage value B0. In proportion to the change, the control voltage 8 to the voltage controlled oscillator also changes from V01 to V1 (the direction of arrow 11 in FIG. 5), and the oscillation frequency fVCO of the voltage controlled oscillator changes from f11 to f01. It goes. Then, when the pulse of the delay signal 9 stops at time T1, the change of the bias voltage 7 also stops and the state is held. After that, the frequency fluctuation range H1 with the frequency f01 as the center frequency (corresponding to f11 to f12 in FIG. 5)
The oscillation frequency fVCO changes in the range of.

Although the case of the phase delay has been described above, the advance signal 10 is transmitted and the same operation is performed in the case of the phase advance. That is, when it is detected that the phase of the output clock 2 is delayed, a bias voltage for increasing the oscillation frequency of the voltage controlled oscillator is generated, and conversely, when it is detected that the phase of the output clock 2 is advanced, the voltage is increased. A bias voltage is generated that lowers the oscillation frequency of the controlled oscillator.

As described above, by using a single wide band voltage controlled oscillator, the state of out-of-synchronization due to temperature change is detected, and control is performed to return the state to the synchronized state. It is possible to realize a variable frequency PLL circuit corresponding to. As a result, the number of parts can be reduced, the device can be downsized, and the cost can be reduced, and once the center frequency is set, the P
The LL circuit can be operated.

[0056]

As described above, according to the present invention, by detecting the ambient temperature and controlling the change of the bias voltage according to the detection result, once the center frequency is set, the PLL circuit is centered around the set frequency. There is an effect that it can be operated. Further, even when the bias voltage is controlled to be pulled into the synchronized state when the loss of synchronization caused by the temperature change is detected, once the center frequency is once set, the PLL circuit can be operated around the set frequency. There is an effect.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a PLL circuit according to a first embodiment of the present invention.

2 is a waveform diagram showing the modulation sensitivity of the voltage controlled oscillator in the PLL circuit of FIG.

FIG. 3 is a block diagram showing a configuration of a PLL circuit according to a second embodiment of the present invention.

FIG. 4 is a time chart showing the operation of the PLL circuit of FIG.

5 is a waveform diagram showing the modulation sensitivity of the voltage controlled oscillator in the PLL circuit of FIG.

6 is a diagram showing a relationship between a bias signal and an oscillation frequency of a voltage controlled oscillator in the PLL circuit of FIG.

FIG. 7 is a block diagram showing a configuration of a conventional PLL circuit.

8 is a waveform diagram showing the modulation sensitivity of the voltage controlled oscillator in the PLL circuit of FIG.

[Explanation of symbols]

 101 Phase Comparator 106 Control Voltage Generation Circuit 107 External Setting Circuit 108 Voltage Controlled Oscillator 109 Bias Setting Circuit 110 Phase Difference Detection Circuit 111 Asynchronous Detection Circuit

Claims (4)

[Claims] 1. A voltage-controlled oscillation means whose oscillation frequency changes according to a control voltage, a phase comparison means for comparing the phases of this oscillation output signal and a reference signal, and a phase comparison output of this phase comparison means and an external setting. PLL including control voltage generating means for generating the control voltage according to the generated bias voltage.
A PLL circuit, comprising: a bias voltage control means for controlling the change of the bias voltage so as to keep the oscillation frequency constant according to the change of the ambient temperature. 2. The bias voltage control means includes a temperature sensor for detecting an ambient temperature, a variation amount of the ambient temperature, and a bias voltage value for keeping the oscillation frequency constant despite the temperature variation. Including the table held,
The bias voltage value corresponding to the temperature detected by the temperature sensor is read from the table.
The described PLL circuit. 3. A voltage-controlled oscillating means whose oscillation frequency changes according to a control voltage, a phase comparing means for comparing the phases of the oscillating output signal and a reference signal, and a synchronization between the oscillating output signal and the reference signal. A synchronization detecting means for detecting a state, a phase difference detecting means for detecting a phase difference of the oscillation output signal with respect to the reference signal only when it is detected as asynchronous by the detection result, and the detected phase difference. Bias voltage generating means for generating a bias voltage according to
A PLL circuit comprising: a control voltage generating means for generating the control voltage according to the generated bias voltage and the phase comparison output of the phase comparing means. 4. The bias voltage generating means generates a bias voltage for increasing the oscillation frequency when the phase difference detecting means indicates that the phase of the oscillation output signal is delayed, and the oscillation output signal is generated. 4. The PLL circuit according to claim 3, wherein a bias voltage for lowering the oscillation frequency is generated when it is shown that the phase of the signal is advanced.