JPH08149171A - Modulator - Google Patents

Abstract

PURPOSE: To make the frequency of a digital frequency conversion signal higher. CONSTITUTION: A digital frequency conversion circuit is made up of polarity inverters 41, 44, 45, parallel serial converters 42, 43, 46, 47 and ROMs 39, 40 conducting multiplication of 1/√2 and the ROMs 39, 40 are inserted to a pre- stage of the parallel serial converters 42, 43 to provide the output of a digital frequency conversion signal whose frequency is equivalent to 1/8 of a processing speed of the D/A converters 8, 9.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a modulator used for a wireless device such as digital mobile communication.

[0002]

2. Description of the Related Art FIG. 5 is a block diagram showing the structure of a conventional modulator. In FIG. 5, reference numerals 1 and 2 are digital band limiting filters for band limiting the base band I and Q signals 18 and 19, and 3 and 4 are band limited base band I and Q signals 20 and 21 and carrier signals (COS waveform signals). 24, SIN waveform signal 25) for multiplying digital multipliers, 5 and 6 for outputting COS waveform signal 24 and SIN waveform signal 25 respectively, 7 for counters for calling carrier signals from ROMs 5, 6 and 8, 9 for digital D / A converter for converting signals (I signal 26, Q signal 27) into analog signals, 10, 11
Is a low-pass filter that removes unnecessary frequency components of the analog signals 28 and 29 obtained by the D / A converters 8 and 9, and 12 and 13 are variable attenuators that adjust the amplitudes of the analog baseband I and Q signals 30 and 31. (ATT), 14 and 15 are direct current (DC) offset adjustment circuits that perform direct current offset adjustment on the analog baseband I and Q signals 32 and 33, and 16 is quadrature modulation on the analog baseband I and Q signals 34 and 35. A quadrature modulator 17 is a bandpass filter for removing unnecessary frequency components of the quadrature modulation signal 37 output from the quadrature modulator 16.

The operation of the modulator configured as described above will be described. First, the baseband I signal 18 and the baseband Q signal 19 are input to the digital band limiting filters 1 and 2, respectively, band-limited and band-limited. A limited baseband I signal 20 and a baseband Q signal 21 are obtained.

Next, these band-limited baseband I signal 20 and baseband Q signal 21 are input to digital multipliers 3 and 4, respectively. Further, the sampling clock 22 is input to the counter 7, and the control signal 23 is output. The control signal 23 is input to the addresses of the ROMs 5 and 6, the COS waveform signal 24 and the SIN waveform signal 25 are output, and are input to the digital multipliers 3 and 4, respectively. The band-limited baseband I signal 20 and the COS waveform signal 24 are multiplied by the digital multiplier 3 to obtain a digital frequency-converted baseband I signal 26. In addition, the band-limited baseband Q signal 21 and SI
The N waveform signal 25 is multiplied by the digital multiplier 4,
A baseband Q signal 27 whose digital frequency has been converted is obtained.

The baseband I signal 26 and the baseband Q signal 27 are input to the D / A converters 8 and 9, respectively, and an analog I signal 28 and an analog Q signal 29 are obtained, respectively.

These analog I signal 28 and analog Q signal 29 are input to low-pass filters 10 and 11, respectively,
The unnecessary frequency components are removed, and the analog baseband I and Q signals 30 and 31 are obtained, respectively.

Next, the analog baseband I and Q signals 30 and 31 are input to variable attenuators (ATT) 12 and 13, respectively, and the analog baseband I and Q signals 3 and 3 are input.
2,33 is obtained. These analog baseband I,
Q signals 32 and 33 are direct current (DC) offset adjustment circuits, respectively.
The analog baseband I and Q signals 34 and 35 are obtained by inputting them to 14 and 15 and adjusting the DC offset.

Next, the analog baseband I, Q signals 34,
35 is input to the quadrature modulator 16. Further, the local oscillation signal 36 from the local oscillator LO is input to the quadrature modulator 16, the analog baseband I, Q signals 34, 35 are quadrature modulated, and the quadrature modulated signal 37 is obtained.

Finally, the quadrature modulation signal 37 is input to the bandpass filter 17 and the unnecessary frequency components are removed, whereby the modulation signal 38 is obtained.

[0010]

In the above-mentioned conventional modulator, the digital frequency-converted base band I,
Carrier leak and image leak that occur after quadrature modulation of the Q signal are generally removed by a band pass filter in the subsequent stage. However, as the frequency of the digital frequency conversion signal becomes lower, carrier leak and image leak that occur after quadrature modulation occur closer to the desired signal, so that a steep filter is required and it becomes difficult to realize the filter. Therefore, it is necessary to increase the frequency of the digital frequency converted signal.

However, in the digital frequency conversion circuit having the above structure, the frequency of the digital frequency conversion signal output by the digital frequency conversion circuit is generally determined by the processing speed of the digital multiplier. If the number of samplings per cycle is 8, there is a drawback that the frequency of the digital frequency converted signal is limited to 1/8 of the processing speed of the digital multiplier.

The present invention solves the above-mentioned conventional drawbacks. By inserting a ROM in the preceding stage of the parallel-serial converter, the processing speed of the digital frequency conversion circuit is increased and the digital frequency conversion is performed. A first object is to increase the frequency of the output signal of the circuit.

Further, by inserting the ROM in the preceding stage of the parallel-serial converter, the processing speed of the digital frequency conversion circuit can be increased, and the higher harmonic components of the digital frequency conversion signal can be converted into the digital frequency conversion signal. The second purpose is to further increase the frequency of the output signal of the digital frequency conversion circuit by outputting as.

By inserting the ROM in the preceding stage of the parallel-serial converter, the processing speed of the digital frequency conversion circuit can be increased, and the aliasing noise component of the digital frequency conversion signal is output as the digital frequency conversion signal. By doing so, the third object is to further increase the frequency of the output signal of the digital frequency conversion circuit.

[0015]

In order to achieve the first object of the present invention, the first solution is a digital band limiting filter for band limiting baseband I and Q signals, and a polarity inverter. Parallel-serial converter and 1 / √2
And a digital frequency conversion circuit configured by a ROM for performing multiplication of
A converter, a low-pass filter that removes unnecessary frequency components of the analog signal, a variable attenuator that adjusts the amplitude of the analog signal, a DC offset circuit that performs DC offset adjustment on the analog signal, and the baseband signal On the other hand, a quadrature modulator that performs quadrature modulation and a bandpass filter that removes unnecessary frequency components of the output signal of the quadrature modulator are provided, and the modulation signal is obtained from the output of the bandpass filter.

In order to achieve the above-mentioned second object, the second solving means is a digital band limiting filter for band limiting the baseband I and Q signals, a polarity inverter, a parallel-serial converter, and a 1 / A digital frequency conversion circuit configured by a ROM that performs multiplication by √2, a D / A converter that converts a digital signal obtained by the digital frequency conversion circuit into an analog signal, and a high-order harmonic component of the analog signal A bandpass filter that extracts as an output signal and removes unnecessary frequency components, a variable attenuator that adjusts the amplitude of the analog signal, a DC offset circuit that performs DC offset adjustment on the analog signal, and a quadrature to the baseband signal. A quadrature modulator that performs modulation, and removes unnecessary frequency components of the output signal of the quadrature modulator It consists of a bandpass filter, characterized in that to obtain a modulated signal from the output of the bandpass filter.

In order to achieve the third object, the third means for solving the problems is a digital band limiting filter for band limiting the baseband I and Q signals, a polarity inverter, a parallel-serial converter and A digital frequency conversion circuit configured by a ROM that performs multiplication by √2, a polarity inverter that inverts the polarity of a digital signal obtained by the digital frequency conversion circuit, and a D / A converter that converts the digital signal into an analog signal. A bandpass filter for removing the aliasing noise component of the analog signal as an output signal and removing unnecessary frequency components, a variable attenuator for adjusting the amplitude of the analog signal, and a DC offset for performing DC offset adjustment on the analog signal. A circuit and a quadrature modulator that performs quadrature modulation on the baseband signal, It consists of a band-pass filter for removing an unnecessary frequency component of the output signal of the serial quadrature modulator, and wherein the obtaining a modulation signal from the output of the bandpass filter.

[0018]

According to the first solution of the present invention, the digital frequency conversion circuit is constituted by the polarity inverter, the parallel-serial converter, and the ROM for multiplying by 1 / √2, and the ROM is parallel-connected. By inserting in the front stage of the serial converter, high frequency is achieved, and in the present invention, the
Since the number of oversamplings per cycle is 8, it is possible to output a digital frequency conversion signal having a frequency that is ⅛ the processing speed of the D / A converter.

Further, according to the second solving means, the digital frequency conversion circuit of the first solving means, and further D
Since a high-order harmonic component of the analog signal output from the A / A converter is extracted as an output signal and a bandpass filter for removing unnecessary frequency components is included, the processing speed of the D / A converter is reduced to 1/8. In addition to outputting a digital frequency conversion signal of a frequency, by further outputting the high-order high-frequency component of the digital frequency conversion signal as a digital frequency conversion signal, it is possible to further increase the frequency of the output signal of the digital frequency conversion circuit. You can

Further, according to the third solving means, since the digital frequency converting circuit of the first solving means and the polarity inverter for inverting the polarity of the digital signal obtained by the digital frequency converting circuit are provided, D /
It is possible to output a digital frequency conversion signal having a frequency that is ⅛ the processing speed of the A converter, and further to output a folding noise component of the digital frequency conversion signal as a digital frequency conversion signal to further increase the digital frequency. It is possible to increase the frequency of the output signal of the conversion circuit.

[0021]

Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 is a block diagram showing the configuration of a modulator in a first embodiment of the present invention. In FIG. 1, 42 and 43 are signals of four systems, and 46 and 47 are 2 signals.
Parallel-serial converters (hereinafter referred to as P / S converters) that convert signals of one system into signals of one system, 39 and 40 multiply the input signal by 1 / √2
OM, 41, 44 and 45 are polarity inverters that invert the polarity of digital signals. And ROM39,40 is P / S converter
It is inserted before 42 and 43. Here, the same numbers are assigned to the respective blocks, signals and the like having the same functions shown in FIG. 5, and the description thereof will be omitted.

FIG. 2 is also a timing chart of the digital frequency conversion circuit in the modulator of FIG. 1 and FIGS. Hereinafter, the correspondence with FIG. 1 will be described, but the same applies to FIGS. 3 and 4.

A is a sampling clock and corresponds to 22 in FIG. B is a sampling clock obtained by dividing the sampling clock A by four, and C is a band-limited baseband I signal, which corresponds to 20 in FIG. D is a band-limited baseband Q signal, which corresponds to 21 in FIG. E is 0 signal
(For example, if the number of operation bits is 8 bits, 1000000
8 bit signal of 0) corresponds to 48 in FIG. F
Is a baseband I signal (20), a signal 49 obtained by multiplying the baseband I signal by 1 / √2, and an E 0 signal.
(48) and a signal 51, which is a signal obtained by multiplying the baseband I signal by 1 / √2, and whose polarity is inverted, are combined in time order to obtain 1
This signal is divided into two systems and corresponds to 52 in Fig. 1. G is a signal obtained by inverting the polarity of the signal F (52) and corresponds to 54 in FIG. H
Is a baseband I signal that has been digitally frequency converted,
It corresponds to 26 in FIG. I is a signal 50 obtained by multiplying the 0 signal (48) of E and the baseband Q signal (21) by 1 / √2.
, And a signal 50 which is obtained by synthesizing the baseband Q signal (21) and the signal 50 obtained by multiplying the baseband Q signal by 1 / √2 in order of time, and corresponds to 53 in FIG. To do.
J is a signal obtained by inverting the polarity of the signal I (53) and corresponds to 55 in FIG. K is the baseband Q that is digital frequency converted
The signal corresponds to 27 in FIG.

The operation of the modulator constructed as described above will be described with reference to the timing chart of FIG. First, the baseband I signal 18 and the baseband Q signal 19
Are inputted to the digital band limiting filters 1 and 2, respectively, and band-limited to obtain the baseband I signal 20 and the baseband Q signal 21 shown in C and D of FIG. 2, respectively.

Next, the band-limited C baseband I
The signal 20 is divided into signals of two systems, and the signal of one system is multiplied by 1 / √2 by the ROM 39 and a signal 49 is output. This signal 49 is divided into signals of two systems, and the signal of one system is inverted in polarity by the polarity inverter 41 and a signal 51 is output. Band-limited baseband I signal 20 and signal 49 and E 0 signal
The signals of the four systems of (48) and the signal 51 are combined in time order by the P / S converter 42 at the timing of the sampling clock 22 of A to be the signal 52 of F of one system shown in FIG. The signal I1 (nT) of F (52) is output. The signal I1 (nT) of this signal F (52) is expressed by (Equation 1).

[0027]

[Equation 1] However, n; 1,2,3, ..., k; 1,2,3, ..., T; Sampling clock cycle Next, the signal I1 (nT) of the signal F (52) is converted into signals of two systems. The signal of one of them is divided into polarity reversals 44
The polarity of the signal is inverted by the signal I2 (nT) of the G signal 54 shown in FIG. The signal I2 (nT) of this signal G (54) is
It is shown by (Equation 2).

[0028]

[Equation 2] However, n; 1,2,3, ..., k; 1,2,3, ..., T; Sampling clock cycle Next, the signal I1 (nT) of the signal F (52) and the signal G (54) Signal I2
The signals of the two systems (nT) are converted by the P / S converter 46 into the A
2 is divided into four to be combined in time sequence at the timing of the B sampling clock to be the H signal 26 shown in FIG. 2 of one system, and the signal H (26) is digitally frequency-converted I signal I3. (nT) is output. The signal I3 (nT) of the signal H (26) is expressed by (Equation 3).

[0029]

(Equation 3) However, n; 1,2,3, ..., k; 1,2,3, ..., T; Sampling clock cycle In the same way, the band-limited D baseband Q signal 21 has two systems. The signal of one system is divided by the ROM40 and multiplied by 1 / √2,
The signal 50 is output. Further, the band-limited baseband Q signal 21, the signal 50, and the 0 signal (48) of E are combined by the P / S converter 43 at the timing of the sampling clock 22 of A in chronological order, and a diagram of one system is shown. I signal shown in 2
The signal Q1 (nT) of the signal I (53) is output. The signal Q1 (nT) of this signal I (53) is expressed by (Equation 4).

[0030]

[Equation 4] However, n; 1,2,3, ..., k; 1,2,3, ..., T; Sampling clock cycle Next, the signal Q1 (nT) of the signal I (53) is converted into two system signals. The signal of one of the two is divided and the polarity invertor 45
The signal Q2 (nT) of the signal 55 of J shown in FIG. The signal Q2 (nT) of this signal J (55) is
It is shown by (Equation 5).

[0031]

(Equation 5) However, n; 1,2,3, ..., k; 1,2,3, ..., T; Sampling clock period Next, the signal Q1 (nT) of the signal I (53) and the signal J (55) Signal Q2
The system of the two signals of (nT) is A by the P / S converter 47.
2 is divided into four to be combined in time order at the timing of a B sampling clock to form a K signal 27 shown in FIG. 2 of one system, and a digital frequency-converted Q signal Q3 of the signal K (27) is generated. (nT) is output. The signal Q3 (nT) of this signal K (27) is expressed by (Equation 6).

[0032]

(Equation 6) However, n; 1, 2, 3, ..., k; 1, 2, 3, ..., T; baseband I signal (26) of sampling clock period H and baseband Q of K
The signal (27) is input to the D / A converters 8 and 9, respectively,
An analog I signal 28 and an analog Q signal 29 are obtained respectively.

These analog I signal 28 and analog Q signal 29 are input to low pass filters 10 and 11, respectively,
The unnecessary frequency components are removed, and the analog baseband I and Q signals 30 and 31 are obtained, respectively.

Next, these analog basebands I,
Q signals 30 and 31 are variable attenuators (ATT) 12 and 1, respectively.
3 to obtain analog baseband I and Q signals 32 and 33, respectively. This analog baseband I, Q
Signals 32 and 33 are direct current (DC) offset adjustment circuit 1 respectively
The analog baseband I and Q signals 34 and 35 are obtained by inputting the signals to 4 and 15 and adjusting the DC offset.

Next, these analog basebands I,
The Q signals 34 and 35 are input to the quadrature modulator 16. The local oscillator signal 36 from the local oscillator LO is input to the quadrature modulator 16, the analog baseband I, Q signals 34, 35 are quadrature-modulated, and the quadrature modulated signal 37 is obtained.

Finally, the quadrature modulation signal 37 is input to the bandpass filter 17 and the unnecessary frequency components are removed, whereby the modulation signal 38 is obtained and output.

As described above, according to the present embodiment (1), the polarity inverter, the parallel-serial converter, and the multiplication of 1 / √2 are performed.
A digital frequency conversion circuit is configured with OM, and RO
By inserting M in the preceding stage of the parallel-serial converter, a high frequency is achieved, and in the present invention, the number of samplings per carrier cycle is set to 8, so that it is 1/8 of the processing speed of the D / A converter. It is possible to output a digital frequency conversion signal having a frequency of.

For example, when the number of operation bits is 10 bits, the maximum processing speed of the current general commercially available 10-bit digital multiplier is about 40 MHz, and in the conventional configuration, the frequency of the digital frequency conversion signal is limited to about 5 MHz. Is.
However, since the maximum processing speed of a general commercially available 10-bit D / A converter is about 400 MHz, the frequency of the digital frequency conversion signal can be set to about 50 MHz in this embodiment (1), and the conventional configuration is used. It is possible to obtain a digital frequency converted signal having a frequency of about 10 times.

(Embodiment 2) FIG. 3 is a block diagram showing the structure of a modulator according to a second embodiment of the present invention. The difference between this second embodiment and the first embodiment (FIG. 1) is that D
A / A converters 8 and 9 are respectively provided with bandpass filters 56 and 57 for extracting high-order harmonic components of the analog I signal 28 and analog Q signal 29 as output signals and removing unnecessary frequency components. is there.

Here, the same numbers are assigned to the blocks, signals and the like having the same functions described in FIG. 1, and the description thereof will be omitted.

Next, the operation of this embodiment (2) is performed according to the timing chart of FIG.

The procedure until the analog I signal 28 and the analog Q signal 29 are obtained by the D / A converters 8 and 9 is the same as in the first embodiment.

The analog I signal 28 and the analog Q signal 29 are taken out by the band pass filters 56 and 57, for example, as the output signal of the second harmonic, and the unnecessary frequency components are removed. An I signal 30 and an analog baseband Q signal 31 are obtained.

Since the subsequent operation is the same as that of the first embodiment (FIG. 1), its explanation is omitted.

As described above, this embodiment (2) is the same as the above embodiment.
In addition to the function and effect of (1), for example, the second-order harmonic signal can be taken out as an output signal by the bandpass filter, and the unnecessary frequency component can be removed.

According to the sampling theorem, the frequency of the second harmonic component is 9 times the frequency of the fundamental component. Therefore, in this embodiment (2), it is possible to obtain a digital frequency conversion signal having a frequency of 9/8 of the processing speed of the D / A converter.

For example, when the number of operation bits is 10 bits, the maximum processing speed of the current general commercially available 10-bit digital multiplier is about 40 MHz, and in the conventional configuration, the frequency of the digital frequency converted signal is limited to about 5 MHz. Is.
However, since the maximum processing speed of a general commercially available 10-bit D / A converter is about 400 MHz, the frequency of the digital frequency conversion signal can be set to about 450 MHz in this embodiment (2), and the conventional configuration is used. It is possible to obtain a digital frequency converted signal having a frequency of about 90 times the frequency.

(Embodiment 3) FIG. 4 is a block diagram showing the structure of a modulator according to a third embodiment of the present invention. This third embodiment differs from the first embodiment (FIG. 1) in that P
Digital signals (I signal 2) output from the / S converters 46 and 47
6 / Q signal 27) polarity invertor 58, 59 for inverting polarity is D / A
D / A converters 8 and 9 provided at the input stages of the converters 8 and 9
The bandpass filters 60 and 61 for removing the aliasing noise components of the analog I signal 28 and the analog Q signal 29 from the output signal and removing unnecessary frequency components are provided.

Here, each block, signal and the like having the same function described in FIGS. 1 and 3 are denoted by the same reference numerals, and the description thereof will be omitted.

Next, the operation of this embodiment (3) will be described with reference to the timing chart of FIG.

The procedure is the same as that of the first embodiment until obtaining the H digital frequency-converted baseband I signal (26) and the K digital frequency-converted baseband Q signal (27).

The H digital frequency-converted baseband I signal (26) and the K digital frequency-converted baseband Q signal (27) are polarity-inverted by the polarity inverters 58 and 59, respectively. A signal 62 and a baseband Q signal 63 are obtained.

The baseband I signal 62 and the baseband Q signal 63 are input to the D / A converters 8 and 9, respectively,
An analog I signal 28 and an analog Q signal 29 are obtained respectively.

For the analog I signal 28 and the analog Q signal 29, aliasing noise components are taken out as output signals by band pass filters 60 and 61, respectively, and unnecessary frequency components are removed. And an analog baseband Q signal 31 is obtained.

Since the following operation is the same as that of the first embodiment (FIG. 1), its explanation is omitted.

As described above, this embodiment (3) is the same as the above embodiment.
In addition to the action and effect of (1), the polarity inverter reverses the I and Q signals digitally converted by the P / S converter.
The polarity-inverted baseband I and Q signals are converted to analog I and Q signals by a D / A converter, and a folding noise component is extracted as an output signal by a bandpass filter.
Remove unnecessary frequency components.

According to the sampling theorem, the frequency of the aliasing noise component is 7 times the frequency of the fundamental wave component. Therefore, in this embodiment (3), it is possible to obtain a digital frequency conversion signal having a frequency of 7/8 of the processing speed of the D / A converter.

For example, when the number of operation bits is 10 bits, the maximum processing speed of the current general commercially available 10-bit digital multiplier is about 40 MHz, and in the conventional configuration, the frequency of the digital frequency conversion signal is limited to about 5 MHz. Is.
However, since the maximum processing speed of a general commercially available 10-bit D / A converter is about 400 MHz, the frequency of the digital frequency converted signal can be set to about 350 MHz in this embodiment (3), and the conventional configuration is used. It is possible to obtain a digital frequency converted signal having a frequency of about 70 times the frequency.

[0059]

As described above, the modulator of the present invention does not use a digital multiplier in a conventional digital frequency conversion circuit, but a polarity inverter, a parallel-serial converter, and 1 / √2 multiplication. And a ROM that performs
By inserting the OM in the preceding stage of the parallel-serial converter, high frequency is achieved, and the processing speed of the D / A converter is reduced to 8
It is possible to output a digital frequency conversion signal having a frequency of one-half.

In the invention according to claim 1, for example,
When the number of operation bits is set to 10 bits, the maximum processing speed of the current general commercially available 10-bit digital multiplier is about 40 MHz, and in the conventional configuration, the frequency of the digital frequency converted signal is limited to about 5 MHz. But the general market 1
Since the maximum processing speed of the 0-bit D / A converter is about 400 MHz, in this embodiment (1), the frequency of the digital frequency converted signal can be set to about 50 MHz, which is 1
It is possible to obtain a digital frequency conversion signal having a frequency of about 0 times.

According to the second aspect of the invention, for example, the second-order harmonic signal is taken out by the bandpass filter and the unnecessary frequency component is removed.

According to the sampling theorem, the frequency of the second harmonic component is 9 times the frequency of the fundamental component. Therefore, according to the present invention, it is possible to obtain a digital frequency conversion signal having a frequency of 9/8 of the processing speed of the D / A converter.

For example, when the number of operation bits is 10 bits, the maximum processing speed of the current general commercially available 10-bit digital multiplier is about 40 MHz, and in the conventional configuration, the frequency of the digital frequency converted signal is limited to about 5 MHz. Is.
However, since the maximum processing speed of a general commercially available 10-bit D / A converter is about 400 MHz, the frequency of the digital frequency conversion signal can be set to about 450 MHz in this embodiment (2), and the conventional configuration is used. It is possible to obtain a digital frequency converted signal having a frequency of about 90 times the frequency.

According to the third aspect of the present invention, the baseband I and Q signals obtained by reversing the polarities of the I and Q signals digitally converted by the P / S converter are converted into analog I and Q signals by the D / A converter. The signal is converted into a signal, a folding noise component is extracted as an output signal by a bandpass filter, and unnecessary frequency components are removed.

According to the sampling theorem, the frequency of the aliasing noise component is 7 times the frequency of the fundamental wave component. Therefore, according to the present invention, it is possible to obtain a digital frequency conversion signal having a frequency of 7/8 of the processing speed of the D / A converter.

For example, when the number of operation bits is 10 bits, the maximum processing speed of the current general commercially available 10-bit digital multiplier is about 40 MHz, and in the conventional configuration, the frequency of the digital frequency conversion signal is limited to about 5 MHz. Is.
However, since the maximum processing speed of a general commercially available 10-bit D / A converter is about 400 MHz, the frequency of the digital frequency converted signal can be set to about 350 MHz in this embodiment (3), and the conventional configuration is used. It is possible to obtain a digital frequency converted signal having a frequency of about 70 times the frequency.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a modulation device according to a first embodiment of the present invention.

FIG. 2 is a timing chart of the digital frequency conversion circuit in the modulator of FIGS. 1, 3 and 4.

FIG. 3 is a block diagram showing a configuration of a modulation device according to a second embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a modulation device according to a third embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration of a conventional modulation device.

[Explanation of symbols]

1, 2 ... Digital band limiting filter, 8, 9 ... D /
A converter, 10, 11 ... Low pass filter, 12, 13 ... Variable attenuator (ATT), 14, 15 ... Direct current (DC) offset circuit, 16 ... Quadrature modulator, 17, 56, 57, 60, 61 ... Band pass Filter, 18 ... Baseband I signal, 19 ... Baseband Q signal, 20 ... Bandlimited baseband I signal
Signal, 21 ... Baseband Q signal with band limitation, 22
... Sampling clock, 26 ... Digital frequency-converted baseband I signal, 27 ... Digital frequency-converted baseband Q signal, 28 ... Analog I signal,
29 ... Analog Q signal, 30 ... Analog baseband I signal from which unnecessary frequency components of analog I signal 28 are removed,
31 ... An analog baseband Q signal from which unnecessary frequency components of the analog Q signal 29 are removed, 32 ... An analog baseband I signal obtained by adjusting the amplitude of the analog baseband I signal 30,
33 ... Analog baseband Q signal with amplitude adjustment of analog baseband Q signal 31, 34 ... Analog baseband I signal with analog offset adjustment of analog baseband I signal 32, 35 ... DC offset adjustment of analog baseband Q signal 33 Analog baseband Q signal,
36 ... Local oscillation signal, 37 ... Quadrature modulation signal, 38 ... Modulation signal, 39, 40 ... ROM for multiplication by 1 / √2, 41, 4
4, 45, 58, 59 ... Polarity inverter, 42, 43, 46, 47 ... Parallel-serial (P / S) converter, 48 ... 0 signal, 49 ...
A signal obtained by multiplying I signal by 1 / √2, 50 ... A signal obtained by multiplying Q signal by 1 / √2, 51 ... A signal obtained by inverting the polarity of signal 49, 52 ... I signal 20 and signal 49 And 0 signal 48
And the signal 51 are combined in time order to form a single system, 53
... A signal in which the 0 signal 48, the signal 50, and the Q signal 21 are combined in time order to form one system, 54 ... A signal in which the polarity of the signal 52 is inverted,
55 ... A signal obtained by reversing the polarity of the signal 53, 62 ... Baseband I
A baseband I signal in which the polarity of the signal 26 is inverted, 63 ... A baseband Q signal in which the polarity of the baseband Q signal 27 is inverted.

Claims (3)

[Claims] 1. A digital frequency converter comprising a digital band limiting filter for band limiting a baseband I signal and a baseband Q signal, a polarity inverter, a parallel-serial converter and a ROM for multiplying 1 / √2. Circuit, a D / A converter for converting a digital signal obtained by the digital frequency conversion circuit into an analog signal, a low-pass filter for removing unnecessary frequency components of the analog signal, and a variable attenuator for adjusting the amplitude of the analog signal. A DC offset circuit that performs DC offset adjustment on the analog signal; a quadrature modulator that performs quadrature modulation on the baseband signal; and a bandpass filter that removes unnecessary frequency components of the output signal of the quadrature modulator. And obtain a modulated signal from the output of the bandpass filter. And a modulator. 2. A digital frequency converter comprising a digital band limiting filter for band limiting the base band I signal and the base band Q signal, a polarity inverter, a parallel-serial converter and a ROM for multiplying 1 / √2. Circuit, a D / A converter for converting a digital signal obtained by the digital frequency conversion circuit into an analog signal, and a bandpass filter for extracting a high-order harmonic component of the analog signal as an output signal and removing an unnecessary frequency component A variable attenuator that adjusts the amplitude of the analog signal, a DC offset circuit that performs DC offset adjustment on the analog signal, a quadrature modulator that performs quadrature modulation on the baseband signal, and an output of the quadrature modulator. And a bandpass filter for removing unnecessary frequency components of the signal. A modulator that obtains a modulated signal from the output of a bandpass filter. 3. A digital frequency conversion filter comprising a digital band limiting filter for band limiting the baseband I signal and the baseband Q signal, a polarity inverter, a parallel-serial converter and a ROM for multiplying 1 / √2. A circuit, a polarity inverter for inverting the polarity of the digital signal obtained by the digital frequency conversion circuit, and a D / A converter for converting the digital signal into an analog signal,
A bandpass filter that extracts the aliasing noise component of the analog signal as an output signal and removes unnecessary frequency components, a variable attenuator that adjusts the amplitude of the analog signal, and a DC offset circuit that performs DC offset adjustment on the analog signal. A quadrature modulator that performs quadrature modulation on the baseband signal, and a bandpass filter that removes unnecessary frequency components of the output signal of the quadrature modulator, and obtain a modulated signal from the output of the bandpass filter. Characteristic modulator.