JPH08149799A - Booster circuit and drive method therefor - Google Patents

Abstract

PURPOSE: To obtain a highly efficient booster circuit in which the loss is reduced. CONSTITUTION: The booster circuit comprises a power supply 1, an oscillation means 2, a first boost means 3, a level conversion means 4, and a second boost means 5. A pulse output from the oscillation means 2 is connected with the pulse inputs of the first boost means 3 and the level conversion means 4 and a first boost voltage, i.e., an output from the first boost means 3, is connected with the power supply terminals of the level conversion means 4 and the second boost means 5. Since a switch and an MOS transistor are substituted for a conventional diode, forward voltage drop does not take place in the diode and since the ON resistance can be lowered sufficiently during conduction, the loss is reduced and the efficiency is enhanced significantly. A high voltage can be obtained easily by connecting the pairs of level conversion means and boost means in cascade.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure and a driving method of a booster circuit for boosting a voltage of a power supply and generating a voltage higher than a power supply voltage in a load.

[0002]

2. Description of the Related Art As a conventional technique, for example, Japanese Patent Publication Sho 51
There is a portable digital electronic device disclosed in Japanese Patent No. 31170. FIG. 7 is a circuit diagram showing the configuration of the booster circuit disclosed in Japanese Patent Publication No. 51-31170.

A conventional booster circuit shown in FIG. 7 has a pulse input signal portion a, a complementary MOS transistor (hereinafter referred to as CMOS) inverter circuit b, and
It is composed of a Cockcroft type booster circuit c, which is connected in combination with a diode and a capacitor, and a load circuit d.

Next, the operation of the conventional booster circuit will be described. The CMOS inverter circuit b shown in FIG. 7 operates as a buffer circuit, and supplies a pulse signal of a high-level bias voltage to the Cockcroft type booster circuit c in the next stage.

That is, when the input of the CMOS inverter circuit b is "low", the output voltage becomes high level, the capacitor C5 is charged to high level through the diode D1, and the input of the CMOS inverter circuit b becomes "high". Then, the output voltage becomes low level, the capacitance C5 charges the capacitance C11 through the diode D2, and the capacitance C5,
The voltage between the terminals of C11 becomes 1/2 of the high level.

Further, the capacitor C11 charges the capacitor C6 through the diode D3, and the voltage becomes ¼ of the high level. Therefore, if the capacitor C5 is charged from the power source and kept at the high level at all times, the capacitors C5, C6, C7, C8, C9,
It is a booster circuit that charges C10 to a voltage near a high level and obtains a boosted output to the load d.

[0007]

However, in the booster circuit of the conventional example, the capacitance is charged at a low voltage due to the forward voltage drop of the diode, and the accumulated charge of the capacitance leaks due to the reverse current of the diode. Therefore, there is a problem that the output voltage can be obtained only 4.2 times although the capacitance is connected in six stages.

The object of the present invention is to solve these problems,
An object of the present invention is to provide an efficient booster circuit with reduced unnecessary loss and a driving method thereof.

[0009]

In order to achieve the above object, the structure of the booster circuit of the present invention and the driving method thereof adopt the following means.

The boosting circuit of the present invention has a power supply, an oscillating means, a first boosting means, a level converting means and a second boosting means, and the pulse output of the oscillating means is the first boosting means and the level converting means. Is connected to the pulse input of the first boosting means, the first boosted voltage that is the output of the first boosting means is connected to the power supply terminals of the level converting means and the second boosting means, and the pulse output of the level converting means is the second output. It is characterized in that it is connected to the pulse input of the boosting means.

Further, the booster circuit of the present invention has a power supply, an oscillating means, a first boosting means, a level converting means and a second boosting means, and the first boosting means and the second boosting means are different from each other. A first switch, a second switch, a third switch, a fourth switch, a first capacitor and a second capacitor, and one terminal of the first switch is connected to a high potential of a power source, The other terminal of the first switch is connected to one terminal of the fourth switch and the first terminal of the fourth switch.
Connected to one terminal of the second switch, the other terminal of the first capacitor is connected to one terminal of the second switch and one terminal of the third switch, and the other terminal of the second switch. Is connected to the other terminal of the fourth switch, one terminal of the second capacitor and the power supply terminal, the other terminal of the third switch is connected to the other terminal of the second capacitor, and The control terminals of the first switch, the third switch and the fourth switch constituting the boosting means are connected to the pulse output of the oscillating means, and the control terminal of the second switch is the inverted output of the pulse output of the oscillating means. The control terminals of the first switch, the third switch and the fourth switch which are connected to each other and constitute the second boosting means are connected to the pulse output of the level converting means, and the control terminal of the second switch is level converting. Characterized in that it is connected to the inverted output of the pulse output of the means. .

Further, the booster circuit of the present invention has a power supply, an oscillating means, a first boosting means, a level converting means and a second boosting means, and the level converting means is a fifth switch and a sixth switch. And a seventh switch, an eighth switch, a ninth switch, a tenth switch, a sixth inverter and a seventh inverter, and one terminal of the fifth switch and the sixth switch is a power source. Of the fifth switch, the other terminal of the fifth switch is connected to one terminal of the seventh switch and the control terminal of the eighth switch, and the other terminal of the sixth switch is connected to the eighth switch. One terminal, the control terminal of the seventh switch, and the input terminal of the sixth inverter, the other terminal of the seventh switch is connected to one terminal of the ninth switch, and the eighth switch The other terminal of is one end of the tenth switch Connected to the switch and tenth ninth
The other terminal of the switch is connected to the first boosted voltage output by the first boosting means, and the control terminals of the fifth switch and the ninth switch are connected to the pulse output output by the oscillating means, The control terminals of the sixth switch and the tenth switch are connected to the inverted output of the pulse output output by the oscillating means,
The output terminal of the sixth inverter is connected to the input terminal of the seventh inverter, and the outputs of the sixth inverter and the seventh inverter are pulse outputs for level-converting the pulse output of the oscillating means. And

A method of driving a booster circuit according to the present invention includes a power supply, an oscillating means, a first boosting means, a level converting means and a second boosting means, and a first boosting means and a second boosting means. Is the first switch, the second switch, the third switch, and the fourth switch.
Switch, the first capacitor and the second capacitor, one terminal of the first switch is connected to the high potential of the power source, and the other terminal of the first switch is one terminal of the fourth switch. And one terminal of the first switch, the other terminal of the first switch is connected to one terminal of the second switch and one terminal of the third switch, and The other terminal is connected to the other terminal of the fourth switch, one terminal of the second capacitor and the power supply terminal, and the other terminal of the third switch is connected to the other terminal of the second capacitor, The control terminals of the first switch, the third switch and the fourth switch constituting the first boosting means are connected to the pulse output of the oscillation means, and the control terminal of the second switch is connected to the pulse output of the oscillation means. The first switch and the third switch which are connected to the inverting output and constitute the second boosting means. The control terminals of the fourth switch and the fourth switch are connected to the pulse output of the level converting means, and the control terminal of the second switch is connected to the inverted output of the pulse output of the level converting means. The first switch and the second switch, which run and oscillate, and output an oscillation pulse to the first booster and the level converter to configure the first booster.
Of the power source voltage of the power source is accumulated in the first capacitor, and then the third switch and the fourth switch are electrically connected to transfer the charge of the first capacitor to the second capacitor. , Second
A low potential of the power source is connected to one terminal of the capacitance of the first capacitor, and a voltage twice the low potential of the power source is connected to the other terminal of the second capacitance.
Is output to the power supply terminals of the level converting means and the second boosting means, and then the first switch and the second switch forming the second boosting means are electrically connected to each other so that the first capacitor has the first voltage. Charge of the boosted voltage is accumulated, and then the third switch and the fourth switch
Of the first capacitor is transferred to the second capacitor, the first boosted voltage is connected to one terminal of the second capacitor, and the first terminal is connected to the other terminal of the second capacitor. It is characterized by generating an output voltage which is four times the low potential of the power supply which is twice the boosted voltage of the above.

[0014]

First, the pulse output output from the oscillating means controls the first switch and the second switch constituting the first boosting means to charge the first capacitance to the power supply voltage, and then the third switch. By controlling the switch and the fourth switch, the first capacitor and the second capacitor are connected in parallel to charge the second capacitor to the power supply voltage, and a boosted voltage twice the power supply voltage is generated at the output terminal. .

Next, the pulse output output from the oscillating means is electrically connected to the fifth switch and the tenth switch constituting the level converting means, and the eighth switch is electrically connected to the fifth switch by being electrically connected, The voltage of the output terminal of the sixth switch becomes the first boosted voltage of the first boosting means, and the output of the level converting means is a pulse obtained by level-converting the pulse output of the oscillating means to the first boosted voltage level. Generate output.

Next, the pulse output output from the level converting means is the first switch and the second switch constituting the second boosting means.
Of the first capacitor to charge the first capacitor to the power supply voltage, and then to control the third switch and the fourth switch to connect the first capacitor and the second capacitor in parallel to the second capacitor. The capacitor is charged to the first boosted voltage, and a boosted voltage that is four times the power supply voltage that is twice the first boosted voltage is generated at the output terminal.

[0017]

Embodiments of the present invention will be described below with reference to the drawings. 1 is a block diagram showing a circuit configuration of a booster circuit according to a first embodiment of the present invention.

First, the configuration of the booster circuit according to the first embodiment of the present invention will be described with reference to FIG. The booster circuit according to the first embodiment of the present invention shown in FIG. 1 comprises a power supply 1, an oscillating means 2, a first boosting means 3, a level converting means 4 and a second boosting means 5.

The high potential of the power supply 1 becomes the ground and is connected to the oscillating means 2, the first boosting means 3, the level converting means 4 and the second boosting means, and the low potential of the power supply 1 becomes the power supply voltage 10 and the oscillating means 2 And to the power supply terminal of the first boosting means 3.

The output of the first boosting means 3 is the first
The boosted voltage is connected to the power source terminals of the level converting means 4 and the second boosting means 5, and the output of the second boosting means 5 is connected to the boosting output means 47.

Further, the pulse output φ1 output by the oscillating means 2 and the inverted pulse output φ2 of the pulse output φ1 are input to the first boosting means 3 and the level converting means 4, and the pulse output from the level converting means 4 is inputted. The output φ3 and the inverted pulse output φ4 of the pulse output φ3 are input to the second boosting means 5.

The power source 1 is a thermoelectric generator that generates power by the temperature difference between the human body temperature and the atmosphere according to the Seebeck effect principle, and although not shown, a P-type semiconductor material and an N-type semiconductor material are connected in series. It is composed of a module in which a plurality of element pairs are combined, for example, the back side in contact with human skin is a heat electrode,
Use it with a temperature difference between both poles so that the front side in contact with the atmosphere is the cold pole.

FIG. 3 is a circuit diagram showing the internal structure of the oscillation means 2 shown in FIG. The configuration of the oscillation means will be described below with reference to FIG.

The oscillating means shown in FIG. 3 comprises a first inverter 11 and a second inverter 1 which are CMOS transistors.
2, the third inverter 13, the fourth inverter 14, the fifth inverter 15, the first resistor 16 and the second resistor 18
And a third capacitor 17 are included.

The output terminal of the first inverter 11 is connected to the input terminal of the second inverter 12, and the output terminal of the second inverter 12 is connected to one terminal of the third capacitor 17 and the input of the third inverter 13. The output terminal of the third inverter 13 is connected to one terminal of the first resistor 16.

The other terminal of the first resistor 16 is the third terminal.
Is connected to the other terminal of the capacitor 17 and one terminal of the second resistor 18, and the other terminal of the second resistor 18 is connected to the input terminal of the first inverter 11.

The high potentials of the first inverter 11, the second inverter 12, the third inverter 13, the fourth inverter 14, and the fifth inverter 15 are connected to the ground, and the low potentials are the power supply terminal 10. Connected to.

The output terminal of the third inverter is the fourth terminal.
The waveform is shaped through the inverter 14 and the fifth inverter 15, and the pulse output φ1 and the inverted pulse output φ2 are output.

FIG. 4 shows the first boosting means 3 and the second boosting means 3 shown in FIG.
3 is a circuit diagram showing an internal configuration of the boosting means 5 of FIG. The configuration of the booster will be described below with reference to FIG.

The boosting means shown in FIG. 4 includes a first switch 23, which is a P-channel MOS transistor, and an N-channel M.
The second switch 24, the third switch 25, the fourth switch 26, which are OS transistors, and the first capacitor 21.
And a second capacitor 22.

One terminal of the first switch 23 is connected to the ground, and the other terminal of the first switch 23 is connected to one terminal of the first capacitor 21 and one terminal of the fourth switch 26. The other terminal of the first capacitor 21 is connected to one terminal of the second switch 24 and the third switch 25.

The other terminal of the second switch 24 is connected to the other terminal of the fourth switch 26, one terminal of the second capacitor 22 and the power supply terminal 20, and the third switch 2 is connected.
The other terminal of 5 is connected to the other terminal of the second capacitor 22 and the boost output terminal 27.

The control terminals of the first switch 23, the third switch 25, and the fourth switch 26 are connected to the control input terminal 28, and the inverted pulse output φ2 of the oscillating means 2 is supplied to the second switch 24. The control terminal is connected to the control input terminal 29.

FIG. 5 is a circuit diagram showing the internal structure of the level converting means 4 shown in FIG. The configuration of the level converting means will be described below with reference to FIG.

The level converting means shown in FIG. 5 is a P channel M.
A fifth switch 31 and a sixth switch 32 which are OS transistors, a seventh switch 33, an eighth switch 34, a ninth switch 35, a tenth switch 36 which are N channel MOS transistors, and a sixth switch Inverter 3
7 and a seventh inverter 38.

Fifth switch 31 and sixth switch 32
One terminal of and is connected to the ground, and the fifth switch 3
The other terminal of 1 is connected to one terminal of the seventh switch 33 and the control terminal of the eighth switch 34.

The other terminal of the sixth switch 32 is connected to one terminal of the eighth switch 34 and the seventh switch 33.
Of the seventh switch 33, the other terminal of the seventh switch 33 is connected to one terminal of the ninth switch 35, and the other terminal of the eighth switch 34 is connected to the control terminal of the eighth switch 34. It is connected to one terminal of the tenth switch 36.

The other terminal of the ninth switch 35 is connected to the other terminal of the tenth switch 36 and the power supply terminal 30, and the control terminal of the fifth switch 31 is the control terminal of the ninth switch 35. And the pulse input terminal, and the control terminal of the sixth switch 32 is connected to the control terminal of the tenth switch 36 and the inverted pulse input terminal.

Further, the output terminal of the sixth inverter 37 is the input terminal of the seventh inverter 38 and the pulse output terminal 3
9 and the output terminal of the seventh inverter 38 is connected to the inverted pulse output terminal 40.

Next, a method of driving the booster circuit according to the first embodiment of the present invention will be described with reference to FIGS. 1, 3, 4, and 5.

Both electrodes of the power source 1 are set so as to have a temperature difference, and a power source voltage is generated in the power source 1. When a power supply voltage is generated in the power supply 1, the first inverter 1 that constitutes the oscillating means 2
The first and second inverters 12, the third inverter 13, the first resistor 16, the second resistor 18, and the third capacitor 17 start oscillation as a ring oscillator.

At this time, the oscillation cycle T of the oscillating means 2 is approximately T = 2.2R0C0 when the first resistor 16 is R0 and the third capacitor 17 is C0. The output of the third inverter 13 becomes a pulse output φ1 by the fourth inverter 14, and the pulse output φ1 is further output to the inverter 1
Inverted pulse output φ2 by 5 and pulse output φ1
And the inverted pulse output φ2 are input to the first booster 3 and the level converter 4.

As shown in FIG. 4, the first boosting means 3 outputs the pulse output φ1 of the oscillating means 2 to the first switch 23 and the third switch 23.
Connected to the control input terminal 28 connected to the control terminals of the switch 25 and the fourth switch 26, and the inverted pulse output φ2 of the oscillation means 2 is connected to the control input terminal 29 connected to the control terminal of the second switch 24. are doing.

First, when the pulse output φ1 is “low” and the inverted pulse output φ2 is “high”, the first switch 23 and the second switch 24 are electrically connected to each other, and the first capacitor 21 is connected to the power source 1
Accumulates charges up to the power supply voltage.

Next, when the pulse output φ1 becomes "high" and the inverted pulse output φ2 becomes "low", the first switch 2
3 and the second switch 24 are cut off, and the third switch 25 and the fourth switch 26 are electrically connected to each other so that the first switch
The capacitance 21 and the second capacitance 22 are connected in parallel.

Therefore, the charges accumulated in the first capacitor 21 are moved to the second capacitor 22, and the first capacitor 21 and the second capacitor 21 are discharged.
, And the voltage between the first capacitor 21 and the second capacitor 22 is almost half the power supply voltage of the power supply 1.

By repeating this cycle, the charging voltage of the first capacitor 21 and the second capacitor 22 becomes substantially the same value as the power source voltage of the power source 1.

Since one terminal of the second capacitor 22 is connected to the low-potential power source voltage of the power source 1, the first boosted voltage of the other terminal of the second capacitor 22 is the second capacitor. The charging voltage of 22 is added to obtain a voltage almost twice as high as the power source voltage of the power source 1, and the first boosted voltage is supplied to the power source terminals of the level converting means 4 and the second boosting means 5. It will be.

As shown in FIG. 5, the level converting means 4 outputs the pulse output φ1 of the oscillating means 2 to the fifth switch 31.
And the ninth switch 35 and the inverted pulse output φ2 of the oscillation means 2 are connected to the control terminals 41 of the sixth switch 32 and the tenth switch 36.

First, when the pulse output φ1 is "low" and the inverted pulse output φ2 is "high", the fifth switch 31 and the tenth switch 36 become conductive, and the fifth switch 31 becomes conductive. The control terminal of the eighth switch 34 becomes “high”, the eighth switch 34 also becomes conductive, and the input terminal of the sixth inverter 37 becomes the first boosted voltage.

Next, when the pulse output φ1 becomes "high" and the inverted pulse output φ2 becomes "low", the sixth switch 3
2 and the ninth switch 35 are electrically connected, and the sixth switch 3
When 2 becomes conductive, the control terminal of the ninth switch 35 becomes "
It becomes “high”, and the ninth switch 35 also becomes conductive. At that time, the input terminal of the sixth inverter 37 is the sixth switch 3
Since 2 is conducting, it serves as the ground, which is the high potential of the power supply 1.

As described above, as the output of the level converting means 4, the pulse output φ1 and the inverted pulse output φ2 of the oscillating means 2 are pulse outputs having the amplitude of the first boosted voltage which is almost twice the power source voltage of the power source 1. The φ3 and the inverted pulse output φ4 are output to the second boosting means 5.

The ON resistances of the seventh switch 33 and the eighth switch 34 are set high in order to reduce the transition current during transient operation.

As shown in FIGS. 1 and 4, the second boosting means 5 controls the pulse output φ3 of the level converting means 4 by the first switch 23, the third switch 25 and the fourth switch 26. Connected to the control input terminal 28 connected to the terminal, the inverted pulse output φ4 of the level conversion means 4 is the second switch 2
4 is connected to the control input terminal 29 connected to the control terminal 4.

First, when the pulse output φ3 is "low" and the inverted pulse output φ4 is "high", the first switch 23 and the second switch 24 are electrically connected to each other, and the first capacitor 21 is boosted to the first voltage. Stores charge up to voltage.

Next, when the pulse output φ3 becomes "high" and the inverted pulse output φ4 becomes "low", the first switch 2
3 and the second switch 24 are cut off, and the third switch 25 and the fourth switch 26 are electrically connected to each other so that the first switch
The capacitance 21 and the second capacitance 22 are connected in parallel.

Therefore, the charges accumulated in the first capacitor 21 are moved to the second capacitor 22, and the first capacitor 21 and the second capacitor 22 are charged.
The electric charge of the first capacitor 21 and the second capacitor 22 becomes almost half of the first boosted voltage.

By repeating this cycle, the charging voltage of the first capacitor 21 and the second capacitor 22 becomes substantially the same value as the first boosted voltage.

Further, one terminal of the second capacitor 22 has the first
Since the boosted voltage of the second capacitor 22 is connected, the charging voltage of the second capacitor 22 is added to the second boosted voltage of the other terminal of the second capacitor 22 to obtain a voltage which is almost twice the first boosted voltage. As a result, a power supply voltage that is almost four times that of the power supply 1 is boosted and output terminal 4
It will be output to 7.

Next, a second embodiment of the present invention will be described. FIG. 2 is a block diagram of a booster circuit according to the second embodiment of the present invention. As shown in FIG. 2, the second aspect of the present invention
The boosting circuit in this embodiment is obtained by connecting two pairs of level converting means and boosting means in cascade connection to the first embodiment of the present invention.

The second embodiment of the present invention shown in FIG. 2 is a power supply 1, an oscillating means 2, a first boosting means 3, a first level converting means 4, a second boosting means 5 and a second level. The converting means 6, the third boosting means 7, the third level converting means 8 and the fourth boosting means 9 are included.

The high potential of the power source 1 becomes the ground, the oscillating means 2, the first boosting means 3, the first level converting means 4 and the second level converting means.
Connected to the boosting means 5, the second level converting means 6, the third boosting means 7, the third level converting means 8 and the fourth boosting means 9, and the low potential of the power source 1 becomes the power source voltage 10 and oscillates. It is connected to the power supply terminals of the means 2 and the first boosting means 3.

The output of the first boosting means 3 is the first
Is connected to the power supply terminals of the first level converting means 4 and the second boosting means 5, and the second boosted voltage which is the output of the second boosting means 5 is connected to the second level converting means 6. It is connected to the power supply terminal of the third boosting means 7, and the third boosted voltage which is the output of the third boosting means 7 is connected to the power supply terminals of the third level converting means 8 and the fourth boosting means 9. The fourth boosted voltage, which is the output of the fourth boosting means 9, is connected to the boosted output terminal 47.

Further, the pulse output φ output from the oscillation means 2
1 and the inverted pulse output φ2 of the pulse output φ1 are input to the first booster 3 and the first level converter 4, and the pulse output φ3 and the pulse output φ3 which are the outputs of the first level converter 4 are output. The inverted pulse output φ4 is input to the second booster 5 and the second level converter 6.

The pulse output φ5 output by the second level converting means 6 and the inverted pulse output φ6 of the pulse output φ5.
Is a pulse output φ input to the third boosting means 7 and the third level converting means 8 and output from the third level converting means 8.
7 and the inverted pulse output φ8 of the pulse output φ7 are input to the fourth booster 9.

The power supply 1 is the thermoelectric generator described in the first embodiment of the present invention, the oscillation means 2 has the configuration shown in FIG. 3, and the first boosting means 3, the second boosting means 5 and the The third boosting means 7 and the fourth boosting means 9 are configured as shown in FIG. 4, and the first level converting means 4, the second level converting means 6 and the third level converting means
The level conversion means 8 has the configuration shown in FIG.

Therefore, the power source 1, the oscillating means 2, the first boosting means 3, the second boosting means 5, the third boosting means 7, the fourth boosting means 9, the first level converting means 4, and the second boosting means 4. The description of the configuration and driving method of the level converting means 6 and the third level converting means 8 will be omitted.

Next, the operation of the second embodiment of the present invention will be briefly described.

The two poles of the power source 1 are set to have a temperature difference, a power source voltage is generated in the power source 1, and the power source voltage is supplied to the oscillating means 2 and the first boosting means 3. When the power supply voltage is supplied, the oscillating means 2 starts oscillating and outputs the pulse output φ1 and the inverted pulse output φ2 to the first boosting means 3 and the first level converting means 4.

The first boosting means 3 uses the pulse output φ1 and the inverted pulse output φ2 to generate the first boosted voltage which is almost twice the power source voltage of the power source 1 as the first level converting means 4 and the second boosting means 5. And supply to.

The first level conversion means 4 outputs the pulse output φ1.
And the inverted pulse output φ2 are level-converted to the first boosted voltage, and the pulse output φ3 and the inverted pulse output φ4 are output to the second booster 5 and the second level converter 6.

The second boosting means 5 uses the pulse output φ3 and the inverted pulse output φ4 to generate the second boosted voltage which is almost four times the power source voltage of the power source 1 as the second level converting means 6 and the third boosting means 7. And supply to.

The second level converting means 6 outputs a pulse output φ3.
And the inverted pulse output φ4 are level-converted to the second boosted voltage, and the pulse output φ5 and the inverted pulse output φ6 are output to the third booster 7 and the third level converter 8.

The third boosting means 7 uses the pulse output φ5 and the inverted pulse output φ6 to generate the third boosted voltage which is about eight times the power source voltage of the power source 1 as the third level converting means 8 and the fourth boosting means 9. And supply to.

The third level converting means 8 outputs a pulse output φ5.
And the inverted pulse output φ6 are level-converted to the third boosted voltage, and the pulse output φ7 and the inverted pulse output φ8 are output to the fourth booster 5.

The fourth boosting means 9 outputs a fourth boosted voltage, which is approximately 16 times the power supply voltage of the power supply 1, to the boost output terminal 47 by the pulse output φ7 and the inverted pulse output φ8, and the load (not shown). Supply to.

As described above, a plurality of pairs of the level converting means and the boosting means are cascaded, the level of the input pulse is converted by the level converting means supplied with the output voltage of the boosting means, and the input of the next boosting means. With this, it is possible to easily obtain an arbitrary high voltage.

The first and second embodiments of the present invention described above
Although the boosting means of the booster circuit in the embodiment of the present invention generates a boosted voltage that is almost doubled, it is also possible to combine the capacitor and the switch to generate a boosted voltage that is doubled or more. Figure 6
FIG. 9 is a circuit diagram showing a configuration of boosting means for outputting a boosted voltage about three times in the third embodiment of the present invention.

The boosting means shown in FIG. 6 is a P-channel MOS transistor, which is a first switch 23, an eleventh switch 53, a thirteenth switch 55 and a fourteenth switch 56.
A second switch 24, a third switch 25, a fourth switch 26, a twelfth switch 54 which are N-channel MOS transistors, a first capacitor 21 and a second capacitor 2
It is composed of two, a fourth capacitor 51 and a fifth capacitor 52.

First switch 23 and eleventh switch 5
One terminal of the third switch 14 and the fourteenth switch 56 and the other terminal of the fifth capacitor 52 are connected to the ground.

The other terminal of the first switch 23 is connected to one terminal of the first capacitor 21 and one terminal of the fourth switch 26, and the other terminal of the first capacitor 21 is connected to the first terminal. It is connected to one terminal of the second switch 24 and the third switch 25.

The other terminal of the second switch 24 is connected to the other terminals of the fourth switch 12 and the twelfth switch 54, one terminal of the second capacitor 22 and the power supply terminal 20, The other terminal of the third switch 25 is connected to the other terminal of the second capacitor 22 and the first boost output terminal 27.

The other terminal of the eleventh switch 53 is connected to one terminal of the fourth capacitor 51 and the thirteenth switch 55.
, And the other terminal of the fourth capacitor 51 is connected to one terminal of the twelfth switch 54 and the other terminal of the fourteenth switch 56.

One terminal of the thirteenth switch 55 is connected to one terminal of the fifth capacitor 52 and the second boost output terminal 5
It is connected to 7.

Further, the pulse output φ1 is the same as the first switch 23, the third switch 25, the fourth switch 26, and the first switch 23.
It connects to the control input terminal 28 connected to the control terminals of the second switch 54, the thirteenth switch 55, and the fourteenth switch 56, and the inverted pulse output φ2 controls the second switch 24 and the eleventh switch 53. It is connected to the control input terminal 29 which is connected to the terminal.

The operation in which the boosted voltage which is almost twice the power supply voltage of the power supply 1 is output to the first boosted output terminal 27 is as follows.
Since it has been described in the first embodiment, the description thereof is omitted here, and an operation of outputting a power supply voltage that is the reverse of the power supply voltage of the power supply 1 to the second boost output terminal 57 will be described.

First, when the pulse output φ1 is "high" and the inverted pulse output φ2 is "low", the eleventh switch 53 and the twelfth switch 54 are conducted, and the fourth capacitor 51 is connected to the power supply voltage of the power supply 1. Accumulates charge up to.

Next, when the pulse output φ1 becomes "low" and the inverted pulse output φ2 becomes "high", the eleventh switch 53 and the twelfth switch 54 are shut off, and the thirteenth switch 55 and the fourteenth switch are cut off. The switch 56 is electrically connected to the fourth capacitor 51 and the fifth capacitor 52 are connected in parallel.

Therefore, the charges accumulated in the fourth capacitor 51 are moved to the fifth capacitor 52, and the charges are accumulated in the fourth capacitor 51 and the fifth capacitor 52.
The electric charge with the second capacitor 52 is halved, and the voltage between the fourth capacitor 51 and the fifth capacitor 52 is almost half the power source voltage of the power source 1.

By repeating this cycle, the charging voltages of the fourth capacitor 51 and the fifth capacitor 52 both become substantially the same as the power supply voltage of the power supply 1.

Since the other terminal of the fifth capacitor 52 is connected to the ground of the power supply 1, the second boost output terminal 57 of one terminal of the fifth capacitor 52 has the fifth capacitor 5 connected thereto.
The charging voltage of 2 is added to obtain a voltage obtained by inverting the power supply voltage of the power supply 1.

Therefore, the first boost output terminal 27 and the second boost output terminal 27
Therefore, the voltage between the boosted output terminal 57 and the boosted output terminal 57 is three times the power supply voltage of the power supply 1.

In the first and second embodiments of the present invention, the circuit configuration of the plus-ground booster circuit in which the high potential of the power supply voltage is used as the ground is shown. It is also possible to have a negative ground circuit configuration as the ground.

Further, although the thermoelectric generator is used as the power source in the first and second embodiments of the present invention, the configuration is such that the boosted voltage is stored using a solar cell or the like. It can also be used as a portable system.

[0095]

According to the booster circuit of the present invention, by using a MOS transistor as a switch instead of the conventional diode, the forward voltage of the diode does not drop and the on-resistance when conducting can be sufficiently lowered. For,
The loss is small and the efficiency is very high.

Further, the pulse converted by the level converting means is used as an input pulse of the next boosting means, and the switch M is used.
Since the OS transistor is controlled, the conduction / interruption operation is reliable, and the accumulated charge of the capacitor does not leak, so that the reliability is high.

Further, as in the second embodiment of the present invention, a high voltage can be easily obtained by cascading the pair of the level converting means and the boosting means, and the loss is small.
A large amount of output current can be taken.

[Brief description of drawings]

FIG. 1 is a block diagram showing a circuit configuration of a booster circuit according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a circuit configuration of a booster circuit according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing an internal configuration of an oscillating means in the first and second embodiments of the present invention.

FIG. 4 is a circuit diagram showing an internal configuration of boosting means in the first and second embodiments of the present invention.

FIG. 5 is a circuit diagram showing an internal configuration of level converting means in the first and second embodiments of the present invention.

FIG. 6 is a circuit diagram showing an internal configuration of boosting means in a third embodiment of the present invention.

FIG. 7 is a circuit diagram showing a configuration of a conventional booster circuit.

[Explanation of symbols]

 1 Power Supply 2 Oscillating Means 3 First Boosting Means 4 Level Converting Means 5 Second Boosting Means 10 Power Supply Voltage 47 Boosting Output Terminal

Claims (6)

[Claims] 1. A power supply, an oscillating means, a plurality of boosting means, and one level converting means less than the boosting means, the level converting means is disposed between the boosting means, and the pulse output of the oscillating means is of the first stage. Connected to the pulse input of the boosting means and the level converting means of the first stage, the pulse output of the level converting means of the first stage is connected to the pulse input of the boosting means of the next stage and the level converting means of the next stage, and the level conversion of the final stage. A booster circuit characterized in that the pulse output of the means is connected to the booster means at the final stage. 2. A power source, an oscillating means, a first boosting means, a level converting means, and a second boosting means, and a pulse output of the oscillating means is input to a pulse input to the first boosting means and the level converting means. The first boosted voltage, which is the output of the first boosting means, is connected to the power supply terminals of the level converting means and the second boosting means, and the pulse output of the level converting means is the pulse input of the second boosting means. A booster circuit characterized by being connected to. 3. A power source, an oscillating means, a first boosting means, a level converting means, and a second boosting means, wherein the first boosting means and the second boosting means are a first switch and a second switch. Switch, third switch, fourth switch, first capacitance, and second switch
And one of the terminals of the first switch is connected to the high potential of the power supply, and the other terminal of the first switch is connected to one terminal of the fourth switch and one terminal of the first capacitor. And the other terminal of the first capacitor is connected to one terminal of the second switch and one terminal of the third switch,
The other terminal of the switch is connected to the other terminal of the fourth switch, one terminal of the second capacitor and the power supply terminal, and the third terminal
The other terminal of the switch is connected to the other terminal of the second capacitor, and the first switch and the third switch forming the first boosting means.
The control terminals of the switch and the fourth switch are connected to the pulse output of the oscillating means, and the control terminal of the second switch is connected to the inverted output of the pulse output of the oscillating means to form the second boosting means. The control terminals of the first switch, the third switch and the fourth switch are connected to the pulse output of the level converting means, and the control terminal of the second switch is connected to the inverted output of the pulse output of the level converting means. Characteristic booster circuit. 4. A power supply, an oscillating means, a first boosting means, a level converting means and a second boosting means, and the level converting means includes a fifth switch, a sixth switch, a seventh switch and a fifth switch. An eighth switch, a ninth switch, a tenth switch, a sixth inverter and a seventh inverter are provided, and one terminal of the fifth switch and the sixth switch is connected to a high potential of a power source, The other terminal of the fifth switch is connected to one terminal of the seventh switch and the control terminal of the eighth switch, and the other terminal of the sixth switch is connected to one terminal of the eighth switch and the seventh terminal. Connected to the control terminal of the switch and the input terminal of the sixth inverter, the other terminal of the seventh switch is connected to one terminal of the ninth switch, and the other terminal of the eighth switch is connected to the tenth terminal. 9th switch connected to one terminal of the switch And the other terminals of the tenth switch are connected to the first boosted voltage output from the first boosting means,
The control terminals of the fifth switch and the ninth switch are connected to the pulse output output by the oscillating means, and the control terminals of the sixth switch and the tenth switch are inverted output of the pulse output output by the oscillating means. Connected, the output terminal of the sixth inverter is connected to the input terminal of the seventh inverter, and the outputs of the sixth inverter and the seventh inverter are pulse outputs for level converting the pulse output of the oscillating means. A booster circuit characterized by the above. 5. A power source, an oscillating means, a first boosting means, a level converting means, and a second boosting means, wherein the first boosting means and the second boosting means are a first switch and a second switch. Switch, third switch, fourth switch, first capacitance, and second switch
And one of the terminals of the first switch is connected to the high potential of the power supply, and the other terminal of the first switch is connected to one terminal of the fourth switch and one terminal of the first capacitor. And the other terminal of the first capacitor is connected to one terminal of the second switch and one terminal of the third switch,
The other terminal of the switch is connected to the other terminal of the fourth switch, one terminal of the second capacitor and the power supply terminal, and the third terminal
The other terminal of the switch is connected to the other terminal of the second capacitor, and the first switch and the third switch forming the first boosting means.
The control terminals of the switch and the fourth switch are connected to the pulse output of the oscillating means, and the control terminal of the second switch is connected to the inverted output of the pulse output of the oscillating means to form the second boosting means. The control terminals of the first switch, the third switch and the fourth switch are connected to the pulse output of the level converting means, and the control terminal of the second switch is connected to the inverted output of the pulse output of the level converting means. The oscillating means self-oscillates when the power is turned on, outputs an oscillation pulse to the first boosting means and the level converting means, and electrically connects the first switch and the second switch forming the first boosting means. The charge of the power supply voltage of the power supply is accumulated in the first capacitance, the third switch and the fourth switch are then conducted to transfer the charge of the first capacitance to the second capacitance, and one of the second capacitance Connect the low potential of the power supply to the terminal of The first boosted voltage, which is a voltage approximately twice the low potential of the power supply, is output to the other terminal of the capacitance of the power supply terminal to the power supply terminals of the level converting means and the second boosting means, and then the second boosting means is configured. The first switch and the second switch are electrically connected to each other to store the electric charge of the first boosted voltage in the first capacitor,
Next, the third switch and the fourth switch are electrically connected to each other and the second switch is connected.
Electric charge of the first capacitance is transferred to the first capacitance, the first boosted voltage is connected to one terminal of the second capacitance, and the second boosted voltage is twice the first boosted voltage to the other terminal of the second capacitance. A method of driving a booster circuit, which generates an output voltage that is approximately four times the low potential of a power supply. 6. A power supply, an oscillating means, a first boosting means, a level converting means and a second boosting means, and a pulse output of the oscillating means is input to a pulse input to the first boosting means and the level converting means. The first boosted voltage, which is the output of the first boosting means, is connected to the power supply terminals of the level converting means and the second boosting means, and the pulse output of the level converting means is the pulse input of the second boosting means. Is connected to the first boosting means and the second boosting means.
The boosting means of the first switch, the second switch, and the third switch.
Switch, fourth switch, eleventh switch and first switch
The second switch, the thirteenth switch, the fourteenth switch, the first capacitance, the second capacitance, the fourth capacitance, and the fifth capacitance, and the first switch, the eleventh switch, and the fourteenth switch. One terminal of the switch and the other terminal of the fifth capacitor are connected to the high potential of the power source, and the other terminal of the first switch is connected to one terminal of the fourth switch and one of the first capacitor. The other terminal of the first capacitor is connected to one terminal of the second switch and one terminal of the third switch,
The other terminal of the second switch is connected to the fourth switch and the twelfth switch.
Connected to the other terminal of the switch and one terminal of the second capacitor and the power supply terminal, and the other terminal of the third switch to the other terminal of the second capacitor and the first boost output terminal. The other terminal of the eleventh switch is connected to the other terminal of the thirteenth switch and one terminal of the fourth capacitor, and the other terminal of the fourth capacitor is connected to one terminal of the twelfth switch. The second capacitor is connected to the other terminal of the fourteenth switch, and one terminal of the thirteenth switch is connected to one terminal of the fifth capacitor and the second terminal of the fifth capacitor.
Connected to the boosted output terminal of the first switch, the third switch, the fourth switch, the twelfth switch, the thirteenth switch and the fourteenth switch are connected to the pulse output of the oscillating means. The booster circuit is characterized in that the control terminals of the second switch and the eleventh switch are connected to the inverted output of the pulse output of the oscillation means.