JPH081613B2 - Information processing device - Google Patents

Description

TECHNICAL FIELD The present invention relates to an information processing apparatus, and more particularly to a high-speed processing method of a store instruction in a pipeline processing type information processing apparatus.

Conventional Technology Conventionally, in a pipeline processing type information processing device,
Sweeping from the store buffer to the main memory was performed in word units of the store buffer.

Therefore, when two store instructions for the same address in the main memory are successively registered in the store buffer, two data are stored for the same address in the main memory to flush from the store buffer to the main memory. Needed to be accessed once.

In such a conventional pipeline processing type information processing apparatus, even when two consecutive store instructions in the store buffer are the same store instruction to the same address in the main memory, the main memory is accessed twice. This is necessary, and the signal access time between the central processing unit and the main memory is slower than the signal access time in the central processing unit, so that there is a disadvantage that the store instruction processing cannot be speeded up.

SUMMARY OF THE INVENTION The present invention has been made in order to eliminate the above-mentioned drawbacks of the conventional ones, and speeds up the store instruction processing when two consecutive store instructions are the same store instruction for the same address in the main memory. An object of the present invention is to provide an information processing device that can be realized.

The information processing apparatus according to the present invention is an information processing apparatus that temporarily holds data stored in a main storage device by a store instruction in a store buffer, and whether consecutive store instructions are the same store instruction for the same address. And the mask information of each of the consecutive store instructions before writing to the store buffer when the same store instruction for the same address is detected by the detector. It has a selecting means for selecting data to be stored and a writing means for writing the data selected by the selecting means in the store buffer.

Embodiment Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, a store address / request registration pointer (WA0) (hereinafter referred to as a registration pointer) 1 is a store address buffer 12 and a store request buffer 13
Address.

Therefore, in the store address buffer 12 and the store request buffer 13, the store address and the store request are registered at the address designated by the registration pointer 1.

A store buffer read pointer (RA) (hereinafter referred to as a read pointer) 2 is a store address buffer 12, a store request buffer 13, and a store mask buffer 17.
And a read address are supplied to the store data buffer 18, respectively.

As a result, the store address is specified by the read pointer 2 of the store address buffer 12, the store request is specified by the read pointer 2 of the store request buffer 13, and the store request is specified by the read pointer 2 of the store mask buffer 17. Store mask information is read from the designated address, and store data is read from the address designated by the read pointer 2 of the store data buffer 18, and sent to the main storage device 19.

The store address registration waiting register (WA) (hereinafter referred to as the registration waiting register) 3 has a store address buffer
The store address registered in 12 is temporarily held, and the store address is sent to the match detection comparator 8 and the store address buffer 12.

The store request registration waiting register (WQ) (hereinafter referred to as a registration waiting register) 4 temporarily stores the store request to be registered next in the store request buffer 13,
The store request is sent to the match detection comparator 9 and the store request buffer 13.

A store mask / data registration pointer (WA1) (hereinafter referred to as a registration pointer) 5 supplies an address to the store mask buffer 17 and the store data buffer 18.

Therefore, in the store mask buffer 17 and the store data buffer 18, the store mask information and the store data are registered at the address designated by the registration pointer 5.

The store mask registration waiting register (WM) (hereinafter referred to as a registration waiting register) 6 temporarily stores the store mask information registered in the store mask buffer 17, and sends the store mask information to the store mask control unit 10. .

The store data registration wait register (WD) (hereinafter referred to as a registration wait register) 7 temporarily stores the store data to be registered in the store data buffer 18, and sends the store data to the selector (WDX) 11.

The match detection comparator 8 compares the store address of the preceding store instruction held in the registration waiting register 3 with the store address of the following store instruction held next in the registration waiting register 3, and ANDs the comparison result.
Output to 14.

That is, the match detection comparator 8 detects whether the address of the preceding store instruction and the address of the subsequent store instruction are the same address.

The match detection comparator compares the store request of the preceding store instruction held in the registration wait register 4 with the store request of the following store instruction held next in the registration wait register 4, and the comparison result is AND gate 14 Output to.

That is, the match detection comparator 9 detects whether the request for the preceding store instruction and the request for the subsequent store instruction are the same request.

The store mask control unit 10 is held in the registration waiting register 6 in response to the store degeneration instruction from the AND gate 14 input via the store degeneration instruction delay flip-flops (hereinafter, store degeneration instruction FF) 15 and 16. According to the store mask information of the preceding store instruction and the store mask information of the following store instruction held next in the registration waiting register 6, the store data of the preceding store instruction held in the registration waiting register 7 and the registration waiting For each byte, it is determined which of the store data of the subsequent store instruction held in the register 7 is to be registered in the store data buffer 18.

That is, when the store degeneration instruction is given by the store degeneration instruction from the AND gate 14, the store mask control unit 10
Performs an OR operation of the store mask information of the preceding store instruction and the store mask information of the following store instruction, registers the operation result in the store mask buffer 17, and controls the selector 11 according to the operation result to advance the operation. The store data to be registered in the store data buffer 18 is selected from the store data of the store instruction to be executed and the store data of the subsequent store instruction.

FIG. 2 is a diagram showing the details of the store mask control unit 10 in FIG. In the figure, the store mask control unit 10 stores the store mask information of the preceding store instruction and the store mask information of the following store instruction when the store degeneration instruction from the AND gate 14 is "0", that is, when the store degeneration is not performed. Regardless of "0" or "1", it is determined that the store data of the preceding store instruction is registered in the store data buffer 18.

When the store degeneration instruction from the AND gate 14 is "1", that is, when the store degeneration is performed, the store mask control unit 10 sets the store mask information of the preceding store instruction to "0".
Then, if the store mask information of the subsequent store instruction is “0”, it is determined that the store data of the preceding store instruction is registered in the store data buffer 18.

If the store mask information of the preceding store instruction is "0" and the store mask information of the succeeding store instruction is "1", it is determined that the store data of the succeeding store instruction is registered in the store data buffer 18.

If the store mask information of the preceding store instruction is "1" and the store mask information of the succeeding store instruction is "0", it is determined to register the store data of the preceding store instruction in the store data buffer 18.

If the store mask information of the preceding store instruction is "1" and the store mask information of the succeeding store instruction is "1", it is determined that the store data of the succeeding store instruction is registered in the store data buffer 18.

FIG. 3 is a time chart showing the operation of one embodiment of the present invention, and FIG. 4 is a diagram showing an example of pipeline processing according to one embodiment of the present invention. Referring to FIG. 4, in pipeline processing according to an embodiment of the present invention, an instruction fetch (IF) stage for fetching an instruction from an instruction cache by an address from an address register (AIC), and an instruction fetched at this stage Operand address (AC) stage that generates a logical address in the address adder based on the operand of this instruction after storing in (IR), and the address after storing the logical address generated in this stage in the logical address register (LAR) An address translation (AT) stage that translates a logical address into a physical address in the translation buffer (TLB), and the physical address translated in this stage is stored in the physical address register (PAR) and then the operand cache is accessed with this physical address. Operand cache access (CA) stage, an operation execution (EX) stage in which the operand read in this stage is stored in the execution register (EXR), and then is calculated in the arithmetic unit, and the result calculated in this stage is read in the data register (RDR ) Is divided into seven stages: a store instruction degenerate (SS) stage for degenerating a store instruction and a result storing (ST) stage for storing the operation result in a registration wait register (WD).

The operation result stored in the registration waiting register is degenerated, stored in the store buffer, and swept from the store buffer to the main storage device.

The operation of the embodiment of the present invention will be described with reference to FIGS.

Processing of the STA1 instruction, which is a store instruction, starts at timing t1, and it is a store instruction at timing t2.
Processing of the STA2 instruction is started. The STA2 instruction is processed with a delay of 1T (timing) from the STA1 instruction from the instruction fetch stage to the result storage stage.

When the store address and store request of the STA1 instruction are held in the register wait register 3 and the register wait register 4 at the timing t4, the store address and store request of the STA2 instruction are registered in the address conversion stage.

Therefore, the match detection comparator 8 compares the store address of the STA1 instruction held in the registration waiting register 3 with the store address of the STA2 instruction in the address conversion stage, and detects whether or not the addresses match.

Further, the match detection comparator 9 has the registration waiting register 4
Comparing the store request of the STA1 instruction held in and the store request of the STA2 instruction of the address translation stage,
Detect if the requests match.

When “1” is output from each of the match detection comparators 8 and 9, it is determined that the STA1 instruction and the STA2 instruction are requests of the same type for the same address of the main storage device 19,
Store degeneration is instructed.

At timing t5, 2 of STA1 instruction and STA2 instruction
One instruction is registered as one STA3 instruction in the store address and the store request at the word position of the store address buffer 12 and the store request buffer 13 indicated by the registration pointer 1, respectively.

Normally, in the store instruction processing, the timing of registering an address and a request in the store buffer is different from the timing of registering data and mask information.

That is, the address and the request can be determined in the address translation stage, but the data and the mask information cannot be determined until the operation execution stage has passed.

Therefore, until the timing at which the store data of the STA2 instruction is output in the operation execution stage, the STA1 instruction and ST
Since the store degeneration instruction indicating that the A2 instruction is a store degeneration target request must be held, the store degeneration instructions (D1, D2) are held in the store degeneration instructions FF15 and 16 at timings t5 and t6, respectively. .

At the timing t6, the store data of the STA1 instruction is held in the registration wait register 7, and the ST is stored in the operation execution stage.
Stored data of A2 instruction is held.

At this time, since "1" is held in the store degeneration instruction FF16, the store data of the STA1 instruction and the store data of the STA2 instruction are merged at timing t6, and the merged store data is stored at timing t7. It is registered as the store data of the STA3 instruction at the word position indicated by the registration pointer 5 of the store data buffer 18.

The store mask control unit 10 stores either the store data from the registration waiting register 7 (store data of the STA1 instruction) or the store data from the operation execution stage (store data of the STA2 instruction) in the store data buffer when the store is degenerated. It is decided for each byte whether to register in 18 or not.

That is, the store data buffer 18 stores the store data masked by the store mask control unit 10 with the value obtained by logically adding the store mask information from the registration wait register 6 and the store mask information from the operation execution stage to STA3.
Registered as instruction store data.

Further, when the store is degenerated, the value obtained by the logical sum of the store mask information from the registration wait register 6 and the store mask information from the operation execution stage in the store mask control unit 10 is stored in the store mask buffer as the store mask information of the STA3 instruction. Registered in 17.

By the completion of the registration of the store data of the STA3 instruction, the store address of the STA3 instruction, the store request, the store mask information, and the store data are registered in the store buffer at the timing t7.
At, the store address, store request, store mask information, and store data of the STA3 instruction are swept from the store buffer to the main storage device 19.

Thus, two consecutive store instructions, namely ST
When it is detected by the match detection comparators 8 and 9 and the AND gate 14 that the A1 instruction and the STA2 instruction are the same store request to the same address of the main memory device 19, the store mask information of the STA1 instruction and the store of the STA2 instruction are stored. Stored data of STA1 instruction and STA2 by mask information
By merging the instruction with the store data and then registering it in the store buffer, it is possible to reduce the number of accesses to the main storage device 19 at the time of sweeping from the store buffer.

Therefore, when two consecutive store instructions are the same store instruction for the same address in the main storage device 19, the speed of the store instruction processing can be increased.

As described above, according to the present invention, when it is detected that consecutive store instructions are the same store instruction for the same address, the data validated by the mask information of each of the consecutive store instructions. Is written in the store buffer, the speed of the store instruction processing can be increased when two consecutive store instructions are the same store instruction for the same address in the main memory.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention, FIG. 2 is a diagram showing details of a store mask control unit of FIG. 1, and FIG. 3 is a time showing an operation of an embodiment of the present invention. chart,
FIG. 4 is a diagram showing an example of pipeline processing according to an embodiment of the present invention. Description of main part code 3 …… Store address registration wait register 4 …… Store request registration wait register 6 …… Store mask registration wait register 7 …… Store data registration wait register 8,9 …… Match detection comparator 10 …… Store Mask control unit 11 …… Selector 12 …… Store address buffer 13 …… Store request buffer 14 …… And gate 17 …… Store mask buffer 18 …… Store data buffer 19 …… Main memory

Claims (1)

[Claims] 1. An information processing device for temporarily holding data stored in a main storage device by a store instruction in a store buffer, and detecting means for detecting whether consecutive store instructions are the same store instruction for the same address. And a selection for selecting valid data in mask information of each of the successive store instructions before writing to the store buffer when the detecting means detects that the same store instruction is for the same address. An information processing apparatus comprising: means and writing means for writing the data selected by the selecting means into the store buffer.