JPH0817183A - Semiconductor circuit and mos-dram - Google Patents

Abstract

(57) [Summary] [Object] To provide a semiconductor circuit composed of a MOS-FET capable of achieving both high-speed switching characteristics and small subthreshold current characteristics. [Structure] In a semiconductor circuit having a logic circuit 1 composed of MOS-FETs Q1 and Q2, MOS-FE
Voltage supply means 15 for supplying voltages V _pp and V _bb different from the back gate bias voltages V _cc and V _{SS of} TQ1 and Q2,
And 13, MOS-FET Q1, Q2 of the back gate bias voltage, the voltage V _cc, V _SS voltage V _cc, the switching means switches to the voltage V _pp, V _bb that is different from the V _SS 10
It is configured with and.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to improvements in semiconductor circuits and MOS-DRAMs that use MOS-FETs.

[0002]

2. Description of the Related Art FIG. 23 is a circuit diagram showing a complementary MOS inverter used in a conventional semiconductor circuit. The power supply potential V _cc is applied to the source and back gate (substrate) of the pMOS FET Q1, and the nMOS FET Q2
The ground potential V _ss is applied to the source and the back gate of the FET, the gates of the FETQ1 and the FETQ2 are connected, the connection point is the input node IN, the drains are connected, and the connection point is The output node is OUT. The operation of such a complementary MOS inverter is
This will be described below. When a logic signal of H level (power supply potential V _cc ) is input from the input node IN, the FET Q1 is turned off and the FET Q2 is turned on, and a logic signal of L level (ground potential V _ss = 0 V) is output via the FET Q2. OU
It is output from T. On the other hand, when an L level (ground potential V _ss = 0V) logic signal is input from the input node IN,
FETQ1 turns on, FETQ2 turns off, and FETQ
A logic signal of H level (power supply potential V _CC ) is output from the output node OUT via 1.

By the way, the miniaturization of semiconductor circuits has progressed, and every time the size of the MOS-FET in the semiconductor circuit is scaled down, the MOS-FET has high performance. Specifically, the channel length is shortened, the gate oxide film is thinned, and the absolute value of the threshold potential is reduced to obtain a faster switching characteristic. However, MOS-FE
In order to obtain a high-speed switching characteristic of T, when the threshold value is lowered or the channel length is shortened, the drain depletion layer and the source depletion layer are connected to each other, so that the source- Punch-through in which a current flows between the drains is likely to occur, and there arises a problem that the subthreshold current in the weak inversion state that flows when the gate potential near the threshold potential does not reach the threshold increases.

FIG. 24 is a sectional structural view schematically showing an example of the structure of a conventional memory cell used in a MOS-DRAM. An nMOS FET 53 and a capacitor 50 are provided on the p well 52, the gate 54 of the FET 53 is provided with the word line WL, the drain 56 is provided with the bit line BL, and the source 5 is provided.
5, one electrode of the capacitor 50 is connected to the other electrode of the capacitor 50, and the cell plate 51 is connected to the other electrode of the capacitor 50. In the memory cell 57 having such a configuration, when the H level signal is applied from the word line WL to the gate 54 and the FET 53 becomes conductive, the charge of the capacitor 50 is transferred to the source 55,
Writing or refreshing / reading is performed by charging / discharging via the drain 56 and the bit line BL. By the way, in the memory cell 57, the electric charge of the capacitor 50 is constantly leaking, and this leak is caused by the subthreshold leak through the channel portion of the FET 53 indicated by the arrow 58 and the pn junction indicated by the arrow 59.
There is a junction leak at the junction. Among these, when the peripheral circuit and the bit line BL are in the standby state, the junction leak is the main, and when the peripheral circuit and the bit line BL are in the active state, the subthreshold leak is the main.

Further, in the MOS-DRAM, refreshing (rewriting) is performed to periodically update the stored content in order to compensate for the above-mentioned leakage loss of the memory cell 57. For this refreshing, peripheral circuits are used. There is a pause refresh when the bit line BL and the bit line BL are in the standby state and a disturb refresh when the peripheral circuit and the bit line BL are in the active state. I have to raise it. Therefore, in order to reduce the junction leak, when the absolute value of the back gate bias potential (p well potential), which is a normal negative potential of the FET 53, is reduced, the absolute value of the threshold potential of the FET 53 is reduced and the junction leak is reduced. But,
On the contrary, there arises a problem that the subthreshold leak increases.

[0006] "MT (M ulti- T hreshold) -CMOS: 1V high-speed CMOS digital circuit technology, Institute of Electronics, Information and Communication Engineers Spring Conference 1994, C-627,5-195" and "1V High-speed Digital
Circuit Technology with 0.5 μm Multi-Threshold (M
T) CMOS, (Proc. IEEE ASIC Conf., 1993, pp186-189) ”has pMOS, nMO having two kinds of high and low threshold voltages.
A CMOS circuit using an S FET is described. M
The CMOS circuit using the T-MOS is intended to reduce the subthreshold current flowing during standby and to speed up the operation during active, and is configured as follows. That is, the logic circuit has a low threshold voltage (0.3 to 0.4V) FE.
Composed of T. Then, the power supply line and the sub power supply line are connected via the high threshold voltage (0.7V) FET for blocking the leak path. In addition, the ground line and the sub-ground line are connected via a high threshold voltage (0.7V) FET. A logic circuit is connected between the sub power line and the sub ground line.

FIG. 25 is a circuit diagram showing a conventional CMOS circuit using an MT-MOS when the logic circuit is an inverter string. Inverter I ₅ pMOS FET Q ₅
The input node IN is the connection point of the gates of the 1, nMOS FET Q52, and the pMOS FET Q51, nMOS F
The connection point of the drain of ETQ52 is pM of the inverter I ₆ .
It is connected to the connection point of the gates of the FET Q53 of the OS and the FET Q54 of the nMOS. Similarly, pMOS FET Q53
And the drain of the nMOS FET Q54 is connected to the pMOS FET Q55 of the inverter I ₇ and the nMOS FE.
It is connected to the connection point of the gate of TQ56, and the connection point of the drains of the pMOS FET Q55 and the nMOS FET Q56 is the pMOS FET Q57 and nM of the inverter I _8.
It is connected to the connection point of the gate of the FET Q58 of the OS.
The connection point of the drains of the pMOS FET Q57 and the nMOS FET Q58 is an output node OUT.

PMOS FETs Q51, Q53, Q55, Q57
Source is connected to the sub power supply line V _cc1
Sources of FETs Q52, Q54, Q56, and Q58 are sub-ground line V
_It is connected to _ss1 . The sub power supply line V _cc1 is a pMOS _{FET Q} whose gate is _supplied with an inverted clock signal bar φ.
It is connected via 59 to the power supply line V _cc (power supply potential: V _cc ). The sub ground line V _ss1 is connected to the ground line V _ss (ground potential: V _ss ) via the nMOS FET Q60 whose gate is _supplied with the clock signal φ. FETQ59, 60 the threshold voltage of, FET Q51 constitute an inverter _{I 5, I 6, I 7} , I 8, Q52, Q53, Q54, Q55, Q56, Q57,
Higher than the threshold voltage of Q58.

In an inverter array using MT-MOS FETs, FETs Q59 and 60 are turned on when active. As a result, pMOS FETs Q51, Q53, Q55, Q
The source of 57 is _supplied with the power supply potential V _cc via the sub power supply line V _cc1 , and the source of the nMOS FETs Q52, Q54, Q56, Q58 is _supplied with the ground potential V _ss via the sub ground line V _ss1 .

In the standby mode, the FETs Q59 and 60 are turned off. As a result, the power source potential V _cc is applied to the sub power source line V _{cc 1.}
Is no longer applied, and the ground potential V _ss is _applied to the sub ground line V _{ss 1.}
Will not be given. Therefore, the current path between the power supply and ground is cut, and the subthreshold current is also reduced.

[0011] forming an inverter _{I 5, I 6, I 7} , I 8 FETQ51, Q52, Q53, Q54, Q55, Q56, Q5
Since the threshold voltage of Q58 is small, high speed operation is possible when active. However, when a subthreshold current flows in the inverter array during standby, the potential of the sub power supply line V _cc1 may drop or the potential of the sub ground line V _ss1 may rise. Then, when shifting from the standby state to the active state, a large delay occurs in switching due to the potential of the sub power supply line _{Vcc1 and} the potential of the sub ground line _Vss1 .
In the worst case, the logic may change. Such a phenomenon is remarkable when the active period is long.

FIG. 26 is a circuit diagram showing a conventional word driver. The word driver WD is a pMOS FET Q61, nMO between the power supply line V _pp connected to the step-up power supply and the ground.
S FET Q62 is connected in series, and pMOS F
The decoder signal X is input to the gate of the ETQ61, nMOS FET Q62, and the pMOS FET Q61, nMOS F
The word line WL is connected to the connection point of the drain of the ETQ62. The word drivers WD having such a configuration are arranged in the vertical direction in the number of n and the horizontal direction in the number of m rows (WD _{11 to} W).
D _mn ). Then, the decoder signal X ₁₁ is input to the selected word driver WD (for example, the word driver WD ₁₁ ) so that the word line WL becomes active.

In such a configuration, a subthreshold current flows in the word driver WD in the standby state, which is a problem in realizing low power consumption. Therefore, in Japanese Patent Laid-Open No. 5-210976, the word driver WD p
A word driver is disclosed which includes a switching means (FET) for switching the power supply potential supply to the FET Q61 of the MOS and prevents a subthreshold current from flowing.

Furthermore, "Subthreshold-Current Reduction
Circuits for Multi-Gigabit DRAM's, Symposium on VL
SI Circuit Dig. Of Tech. Papers, pp.45-46 ”describes switching means (FE) for switching the power supply potential supply of the FET Q61 of the pMOS of the word driver WD in column units.
A word driver having a hierarchical structure including T) between the switching means and the word driver is described. Figure
27 is a circuit diagram showing this word driver. Power line V
_pp is a pMOS FET connected to each word driver string B1, B2, ... Bm via a pMOS FET Q70.
It is connected to Q71, Q72, ... Q7m. FET Q71, Q
72, ~ Q7m gate, corresponding word driver row B
Column selection signals K1, K2, ... K which become L level only when 1, B2, ... Bm include the word driver WD to be selected.
m is given.

As a result, at the time of transition from the standby state where the source potential of the pMOS FET Q61 is slightly lowered to the active state, the pMOs of all word drivers WD are pMO.
Since it is not necessary to raise the source potential of the FET Q61 of S, and the source potential of the word driver row including the selected word driver may be raised, the current consumption at this time can be reduced.

In the word driver shown in FIG. 27, when the standby state is transitioned to the active state, the pMOSFE
Since it is necessary to raise the source potential of TQ61 from the slightly lowered potential to the power supply potential, there is a problem that the rising of the selected word line is delayed.

[0017]

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and in the first to fourth inventions, by providing means for switching the back gate bias potential of the MOS-FET, MO that can achieve both high-speed switching characteristics and small subthreshold current characteristics
It is an object to provide a semiconductor circuit composed of S-FETs.

In the sixth and seventh inventions, by providing means for switching the back gate bias potential of the MOS-FET, an M-FET composed of a MOS-FET capable of achieving both high-speed switching characteristics and small subthreshold current characteristics.
An object is to provide an OS-DRAM.

It is an object of the eighth and ninth inventions to provide a MOS-DRAM composed of memory cells with less leakage by providing means for switching the back gate bias potential of the MOS-FET forming the memory cell. To do.

In the tenth to thirteenth inventions, an MO having an SOI structure is used.
An object of the present invention is to provide a semiconductor circuit composed of a MOS-FET capable of achieving both high-speed switching characteristics and small subthreshold current characteristics by providing a means for switching the body bias potential of the S-FET.

In the fifteenth to eighteenth inventions, an MO having an SOI structure is used.
MOS-FE capable of achieving both high-speed switching characteristics and small subthreshold current characteristics when S-FET elements are isolated by the LOCOS method and / or the FS method.
An object is to provide a semiconductor circuit composed of T.

In the nineteenth and twentieth inventions, an SOI structure MO is provided.
An object of the present invention is to provide a MOS-DRAM including a MOS-FET capable of achieving both high-speed switching characteristics and small subthreshold current characteristics by providing a means for switching the body bias potential of the S-FET.

In the twenty-first and twenty-second inventions, by providing a means for switching the body bias potential of the SOI-structure MOS-FET forming the memory cell, it is possible to provide a MOS-DRAM composed of memory cells with less leakage. To aim.

In the twenty-third to twenty-eighth inventions, by providing means for switching the back gate bias potential or the body bias potential constituting the inverter train or the word driver, both high speed switching characteristics and small subthreshold current characteristics can be achieved. Semiconductor circuit or MOS-DR
The purpose is to provide AM.

[0025]

A semiconductor circuit according to a first aspect of the present invention is a MOS-FET in which a first potential or a second potential should be applied as a back gate bias potential.
And a switching means for selectively applying the first potential or the second potential to the MOS-FET.

A semiconductor circuit according to a second aspect of the present invention is a MOS-FET to which the first potential or the second potential is to be given as a back gate bias potential, and a first potential or a first potential according to an operation mode of the MOS-FET. The potential of 2 is MOS-F
And a switching means for selectively applying to ET.

In the semiconductor circuit according to the third aspect of the invention, a MOS-FET to which the first potential or the second potential should be given as a back gate bias potential, and a clock for generating a control clock signal for activating the MOS-FET. Signal generating means and according to the control clock signal,
And a switching means for selectively applying the first potential or the second potential to the MOS-FET.

The semiconductor circuit according to the fourth aspect of the present invention is the first, second,
Alternatively, in the third invention, the switching means outputs the signal for converting into the first potential or the second potential, and the first potential or the second potential according to the output signal from the level shift circuit. And a switch circuit for selectively applying a potential to the MOS-FET.

The semiconductor circuit according to the fifth aspect of the invention is
Alternatively, the third invention is characterized by having a logic circuit constituted by a MOS-FET.

A MOS-DRAM according to a sixth aspect of the present invention is the first aspect.
And a second potential are provided by a MOS-FET to be given as a back gate bias potential, and a logic circuit used for a row operation circuit and a column operation circuit, and an operation mode of the logic circuit, And a switching means for selectively applying the first potential or the second potential to the MOS-FET.

A MOS-DRAM according to a seventh invention is the first
Circuit or a second circuit, which is constituted by a MOS-FET to which the back gate bias potential is applied, and a logic circuit used for a row operation circuit and a column operation circuit, and a control for activating the logic circuit. A clock signal generating means for generating a clock signal; and a switching means for selectively applying a first potential or a second potential as a back gate bias potential to the MOS-FET according to the control clock signal. To do.

A MOS-DRAM according to an eighth invention is the first
Or a second potential as a back gate bias potential, and a memory cell configured by a MOS-FET to be given as a back gate bias potential, and the first potential or the second potential as a back gate bias potential according to the operation mode of the memory cell. And switching means for selectively applying to the MOS-FET.

A MOS-DRAM according to a ninth aspect of the present invention is the first aspect.
According to a signal for activating the memory cell and a memory cell configured by a MOS-FET to which the potential of 2) or the second potential is given as a back gate bias potential,
A switching means for selectively applying the first potential or the second potential as a back gate bias potential to the MOS-FET.

In the semiconductor circuit according to the tenth aspect of the invention, a MOS-FET to which the first potential or the second potential should be given as a body bias potential and a first potential or the second potential are selectively applied to the MOS-FET. And a switching means provided to the.

A semiconductor circuit according to an eleventh aspect of the present invention is a MOS-FET to which the first potential or the second potential should be applied as a body bias potential, and a first potential or a second potential according to the operating mode of the MOS-FET. Potential of MOS-FET
And a switching means for selectively applying to the switch.

A semiconductor circuit according to the twelfth aspect of the invention is a MOS-FET to which the first potential or the second potential is applied as a body bias potential, and a clock signal for generating a control clock signal for activating the MOS-FET. A first means according to the generating means and the control clock signal;
And a switching means for selectively applying the second potential or the second potential to the MOS-FET.

The semiconductor circuit according to the thirteenth invention is the tenth,
In the eleventh or twelfth invention, the switching means outputs a signal for converting into the first potential or the second potential and a first potential or a first potential according to an output signal from the level shift circuit. The potential of 2 is MOS-F
And a switch circuit for selectively giving to ET.

A semiconductor circuit according to a fourteenth invention is the tenth,
In the 11th or 12th invention, a MOS-F having an SOI structure
It is characterized by having a logic circuit constituted by ET.

The semiconductor circuit according to the fifteenth invention is the tenth,
In the 11, 12, or 13 invention, the MO of SOI structure
The S-FET is characterized in that elements are isolated by an isolation oxide film.

The semiconductor circuit according to the 16th aspect of the invention is
In the 11, 12, or 13 invention, the MO of SOI structure
The S-FETs are element-isolated by an FS isolation layer formed by partially channeling off the channel layer, and the FS isolation layer is connected to a switching means.

The semiconductor circuit according to the seventeenth invention is the tenth,
In the 11, 12, or 13 invention, the MO of SOI structure
The S-FETs are separated from each other by an FS isolation layer formed by partially channeling off the isolation oxide film and the channel layer, and the FS isolation layer is connected to a switching means. .

A semiconductor circuit according to the eighteenth invention is the tenth,
In the invention of 11, 12, or 13, the one conductivity type MOS-FET of the SOI structure is element-isolated by an FS separation layer formed by partially channeling off the channel layer. The FS separation layers on both sides of the MOS-FET are connected to the switching means, the FS separation layers on both sides of the other one conductivity type MOS-FET are connected to a predetermined potential, and the separation layers between the FS separation layers are other. Is applied.

A MOS-DRAM according to a nineteenth aspect of the invention is composed of a MOS-FET having an SOI structure to which the first potential or the second potential should be given as a body bias potential, and row-system operation circuits and column-system operations. A logic circuit used in the circuit and switching means for selectively applying the first potential or the second potential to the MOS-FET according to the operation mode of the logic circuit are provided.

A MOS-DRAM according to a twentieth aspect of the present invention is composed of a MOS-FET having an SOI structure to which the first potential or the second potential is applied as a body bias potential, and row-system operation circuits and column-system operations. A logic circuit used in the circuit, a clock signal generating means for generating a control clock signal for activating the logic circuit, and a first potential or a second potential selectively applied to the MOS-FET according to the control clock signal. And a switching means provided to the.

A MOS-DRAM according to a twenty-first aspect of the invention is a memory cell constituted by a MOS-FET having an SOI structure to which the first potential or the second potential should be given as a body bias potential, and an operating mode of the MOS-DRAM. And a switching means for selectively applying the first potential or the second potential to the MOS-FET.

A MOS-DRAM according to a twenty-second aspect of the present invention activates a memory cell composed of a MOS-FET having an SOI structure to which the first potential or the second potential is applied as a body bias potential, and the MOS-DRAM. The first potential or the second potential according to the signal
And a switching means for selectively applying to T.

A semiconductor circuit according to the twenty-third invention is the semiconductor circuit according to the fifth or fourteenth invention, wherein the logic circuit is a one conductivity type MOS-FE.
It is an inverter string in which inverters composed of T and other conductivity type MOS-FETs are connected in series, and a back gate of the MOS-FET which is turned off at the standby time is connected to the switching means.

A semiconductor circuit according to the twenty-fourth invention is the semiconductor circuit according to the fifth or fourteenth invention, wherein the logic circuit is one conductivity type MOS-FE.
An inverter array in which inverters composed of T and other conductivity type MOS-FETs are connected in series, and the inverter array is grounded via a sub power line connected to a power source via a switching element and a switching element. It is characterized in that it is arranged between the sub grounding line.

A semiconductor circuit according to the twenty-fifth invention is the semiconductor circuit according to the twenty-fourth invention, wherein the switching element has a threshold voltage higher than that of the MOS-FET forming the logic circuit.
It is T, and is characterized by turning on when active.

The semiconductor circuit according to the twenty-sixth invention is the semiconductor circuit according to the twenty-third or twenty-fifth invention, which constitutes an inverter array.
MOS-FET that turns on when active among FETs
The threshold voltage of the MOS-FET turns off when active
Is smaller than the threshold voltage of.

A MOS-DRAM according to the twenty-seventh invention is characterized in that, in the sixth, seventh, nineteenth or twentieth invention, the operation circuit is a word driver.

A MOS-DRAM according to the twenty-eighth invention is a MOS-DRAM according to the twenty-seventh invention, which constitutes a word driver.
The FET is characterized in that it is connected to the switching means in column units.

[0053]

In the semiconductor circuit according to the first aspect of the present invention, the switching means switches the back gate bias potential of the MOS-FET to the first potential or the second potential, and the MO
Since the absolute value of the threshold potential of the S-FET is switched, the switching characteristic and the subthreshold current characteristic can be switched.

In the semiconductor circuit according to the second invention, the MOS-
Depending on the mode of operation of the FET, the switching means may be MO
When the back-gate bias potential of the S-FET is switched to the first potential or the second potential and the MOS-FET operates, the absolute value of the threshold potential is reduced to reduce the MOS-FET.
If does not work, increase the absolute value of the threshold potential.

In the semiconductor circuit according to the third aspect of the invention, the back gate bias potential of the MOS-FET is switched to the first potential or the second potential according to the control clock signal generated by the clock signal generating means, and the MOS-FET is switched.
Is activated, the absolute value of the threshold potential is reduced and MO
When the S-FET does not operate, the absolute value of the threshold potential is increased.

In the semiconductor circuit according to the fourth aspect of the invention, the level shift circuit converts the potential of the logic level into the back gate bias potential of the MOS-FET constituting the logic circuit, and according to the output from the level shift circuit, Since the switch circuit switches the back gate bias potential of the MOS-FET forming the logic circuit to the first potential or the second potential, the switching means is the MOS-FET.
The back gate bias potential of 1 can be converted into the first potential or the second potential.

In the semiconductor circuit according to the fifth invention, the MOS-
Even if it has a logic circuit composed of FETs,
The effects of the second or third invention can be realized.

In the MOS-DRAM according to the sixth aspect of the present invention, the switching means has the back gate bias potential of the MOS-FET which constitutes each logic circuit used in the row-related operation circuit and the column-related operation circuit of the MOS-DRAM. Is switched to the first potential or the second potential according to the operation mode of each logic circuit, so that the absolute value of the threshold potential of the MOS-FET is reduced only when the logic circuit formed by the MOS-FET is active. You can

In the MOS-DRAM according to the seventh aspect of the present invention, the switching means has the back-gate bias potential of the MOS-FET which constitutes each logic circuit used in the row-related operation circuit and the column-related operation circuit of the MOS-DRAM. Is switched to the first potential or the second potential in accordance with a control clock signal for activating each logic circuit generated by the clock signal generating means. Therefore, only when the logic circuit constituted by the MOS-FET is active, the MOS- The absolute value of the threshold potential of the FET can be reduced.

In the MOS-DRAM according to the eighth invention, the switching means changes the back gate bias potential of the MOS-FET constituting the memory cell of the MOS-DRAM,
Since the potential is switched to the first potential or the second potential according to the operation mode of the MOS-DRAM, at the time of pause refresh of the memory cell, the absolute value of the threshold potential of the MOS-FET is reduced to reduce the junction leak and the memory cell. At the time of the disturb refresh, the absolute value of the threshold potential of the MOS-FET can be increased to reduce the subthreshold leak.

In the MOS-DRAM according to the ninth invention, the switching means changes the back gate bias potential of the MOS-FET constituting the memory cell of the MOS-DRAM to
Since the first potential or the second potential is switched according to the signal for activating the MOS-DRAM, at the time of pause refresh of the memory cell, the absolute value of the threshold potential of the MOS-FET is reduced to reduce the junction leak and At the time of disturb refresh of the memory cell, MOS-F
Sub-threshold leakage can be reduced by increasing the absolute value of the ET threshold potential.

In the semiconductor circuit according to the tenth aspect of the invention, the switching means switches the body bias potential of the MOS-FET having the SOI structure to the first potential or the second potential, and M
Since the absolute value of the threshold potential of the OS-FET is switched, the switching characteristic and the subthreshold current characteristic can be switched.

In the semiconductor circuit according to the eleventh invention, the switching means switches the body bias potential of the MOS-FET to the first potential or the second potential according to the operating mode of the MOS-FET having the SOI structure, and the MOS-FET is turned on. When the FET operates, the absolute value of the threshold potential is reduced and the MOS-
When the FET does not operate, the absolute value of the threshold potential is increased.

In the semiconductor circuit according to the twelfth aspect of the invention, the body bias potential of the SOI-structure MOS-FET is switched to the first potential or the second potential according to the control clock signal generated by the clock signal generating means, and the MOS-
The absolute value of the threshold potential is reduced when the FET operates, and the absolute value of the threshold potential is increased when the MOS-FET does not operate.

In the semiconductor circuit according to the thirteenth aspect of the invention, the level shift circuit converts the potential of the logic level into the body bias potential of the MOS-FET having the SOI structure which constitutes the logic circuit, and outputs from the level shift circuit. According to the switch circuit, the switch circuit forms a MOS-FE
Since the body bias potential of T is switched to the first potential or the second potential, the switching means is a MOS-FE.
The body bias potential of T can be converted into the first potential or the second potential.

The semiconductor circuit according to the fourteenth aspect of the invention can realize the action of the tenth, eleventh, or twelfth aspect of the invention even when the semiconductor circuit has a logic circuit formed of a MOS-FET of SOI structure.

The semiconductor circuit according to the fifteenth invention is the tenth,
The action in the 11, 12, or 13 invention is
Element MOS-FET with SOI structure isolated by the method
Can be realized in.

The semiconductor circuit according to the 16th aspect of the invention is
The effect of the 11, 12 or 13 invention can be realized in a MOS-FET having an SOI structure in which elements are isolated by the FS method.

The semiconductor circuit according to the seventeenth invention is the tenth,
The action in the 11, 12, or 13 invention is
Of SOI structure in which elements are separated by the FS method and the FS method
It can be realized in an S-FET.

The semiconductor circuit according to the 18th aspect of the invention is
11, 12, or 13 The effect of the invention is to provide a plurality of one-type MOS-Fs having an SOI structure which are element-isolated by the FS method.
Can be realized in ET.

In the MOS-DRAM according to the nineteenth aspect of the invention, the body of the SOI-structure MOS-FET in which the switching means constitutes each logic circuit used in the row-related operation circuit and the column-related operation circuit of the MOS-DRAM. The bias potential
Since the potential is switched to the first potential or the second potential according to the operation mode of each logic circuit, the absolute value of the threshold potential of the MOS-FET can be reduced only when the logic circuit formed by the MOS-FET is active. .

In the MOS-DRAM according to the twentieth aspect of the present invention, the body of the SOI-structure MOS-FET in which the switching means constitutes each logic circuit used in the row-related operation circuit and the column-related operation circuit of the MOS-DRAM. The bias potential
The potential is switched to the first potential or the second potential according to the control clock signal for activating each logic circuit generated by the clock signal generating means. Therefore, only when the logic circuit formed by the MOS-FET is active, the MOS-FET The absolute value of the threshold potential can be reduced.

In the MOS-DRAM according to the twenty-first invention, the switching means sets the body bias potential of the SOI-structure MOS-FET constituting the memory cell of the MOS-DRAM to the first potential according to the operation mode of the MOS-DRAM. Alternatively, since the potential is switched to the second potential, the absolute value of the threshold potential of the MOS-FET is reduced at the time of pause refresh of the memory cell to reduce the junction leak, and at the time of disturb refresh of the memory cell, the MOS-FE.
Subthreshold leakage can be reduced by increasing the absolute value of the threshold potential of T.

In the MOS-DRAM according to the twenty-second aspect of the present invention, the switching means changes the body bias potential of the SOI-structure MOS-FET forming the memory cell of the MOS-DRAM to a signal for activating the MOS-DRAM.
Since the potential is switched to the first potential or the second potential, the absolute value of the threshold potential of the MOS-FET is reduced at the time of pause refresh of the memory cell to reduce the junction leak, and at the time of disturb refresh of the memory cell, M
Sub-threshold leakage can be reduced by increasing the absolute value of the threshold potential of the OS-FET.

In the semiconductor circuit according to the twenty-third aspect of the invention, in addition to the action of the fifth or fourteenth aspect of the invention, when the MOS-FETs form an inverter train, the back-gate bias potential or body bias potential of all the MOS-FETs is set. The power required for switching is half that of the switching configuration.

In the semiconductor circuit according to the twenty-fourth and twenty-fifth inventions, in addition to the action of the fifth or fourteenth invention, the inverter array is a switching element (for example, MOS-FET having a high threshold voltage)
Is connected to the power supply via a switching element and grounded via a switching element (for example, a MOS-FET having a high threshold voltage). Therefore, if the switching element is turned off during standby, the current path between the power source and ground is cut off. be able to.

The semiconductor circuit according to the twenty-sixth aspect of the invention has, in addition to the operation of the twenty-fifth aspect of the invention, a MOS-F forming an inverter array.
Among the ETs, the threshold voltage of the MOS-FET which is turned on when active is set to be smaller than the threshold voltage of the MOS-FET which is turned off when active. Therefore, when shifting from the standby state to the active state, these MOS-FEs are
The current at T can be increased quickly. This improves the operating speed.

A MOS-DRAM according to the twenty-seventh invention is
In the word driver, the reduction of the subthreshold current and the high speed operation described in the operation of the sixth, seventh, nineteenth or twentieth invention can be realized.

A MOS-DRAM according to the twenty-eighth invention is
In addition to the operation of the twenty-seventh aspect of the invention, the back gate bias potential or the body bias potential of the MOS-FET forming the word driver is controlled on a column-by-column basis, so that the power required for switching can be reduced.

[0080]

The present invention will be described below with reference to the drawings showing the embodiments thereof.
I will explain. Example 1. FIG. 1 shows a semiconductor circuit according to the first to fourth inventions.
Complementary MOS circuit showing an example of a logic circuit to be formed
It is a circuit diagram of the inverter. Power source for the source of FET Q1
Rank V_ccIs applied, and the ground potential V is applied to the source of the FET Q2._ssTo
It is applying and each gate of FETQ1 and FETQ2
And connect that connection point to the input node IN,
Connect the rain and use the connection point as the output node OUT
There is. The back gate of the FET Q2 has a ground potential V
_ss(= 0V) and ground potential V_ssLower potential V _bb(<0
V) is connected to a switch circuit 10 for switching
The back gate of TQ1 has a power supply potential V_ccAnd power supply potential V_cc
Higher potential V_ppConnect to the switch circuit 11 that switches between
Has been continued.

Here, the FET Q1 and the FET Q2 have a sub-threshold of the same level as that of the conventional one when a potential V _pp higher than the power supply potential V _cc and a potential V _bb lower than the ground potential V _ss are applied to each back gate. So that it becomes a current. Then, when the power supply potential V _cc and the ground potential V _ss are applied to the respective back gates, the absolute value of the threshold potential becomes smaller than the conventional one, so that the subthreshold current increases but the switching speed becomes faster than the conventional one. be able to. Therefore, if the absolute value of the threshold potential is made small in this way when the complementary MOS inverter 1 operates, the complementary MO
The subthreshold current increases according to the ratio of the time that the S inverter 1 operates, but if the ratio of the operation time is not large, the switching speed can be made faster than before with only a slight increase in the current. it can.

FIG. 2 is a circuit diagram showing an example of the switch circuit 10 for switching between the ground potential V _ss and the potential V _bb shown in FIG. FETs Q3 and Q4 of pMOS, F of nMOS
The level shift circuit 10a is configured by the ETQ5, Q6 and the inverter 12, and the FETQ3 and the FETQ5
Are connected to each other, the drains of the FET Q4 and the FET Q6 are connected to each other, and the drains and gates of the FETs Q5 and Q6 are connected to each other. The input node of the level shift circuit 10a is provided at the gate of the FET Q3, is connected to the gate of the FET Q4 via the inverter 12, and receives the input signal bar φ from the clock signal generator 14. A power supply potential V _cc is applied to the sources and back gates of the FETs Q3 and Q4, and a potential V _bb lower than the ground potential V _ss supplied from the voltage supply means 13 is applied to the sources and back gates of the FETs Q5 and Q6. There is. The output nodes of the level shift circuit 10a are FET Q4 and F
It is provided at the connection point between the drains of the ETQ6, and this output node is connected to the input node of the changeover switch 10b.

The changeover switch 10b is an nMOS F
FET composed of ETQ7 and pMOS FET Q8
The gates of Q7 and FET Q8 are connected to each other to serve as an input node of the changeover switch 10b, and the drains thereof are connected to serve as an output node. The ground potential V supplied from the voltage supply means 13 is applied to the source and back gate of the FET Q7.
_The potential V _bb lower than _ss is applied, and the ground potential V _ss is applied to the source of the FET Q8.

FIG. 3 is a circuit diagram showing an example of the switch circuit 11 for switching between the power supply potential V _cc and the potential V _pp shown in FIG. The pMOS FETs Q9 and Q10, the nMOS FETs Q11 and Q12, and the inverter 14 constitute a level shift circuit 11a.
Drains of TQ11, FETQ10 and FETQ1
The two drains are connected to each other, and the drains and gates of the FETs Q11 and Q12 are connected to each other. Level shift circuit 1
The input node 1a is provided at the gate of the FET Q9, is connected to the gate of the FET Q10 through the inverter 12, and receives the input signal bar φ from the clock signal generator 14. A potential V _pp higher than the power source potential V _cc supplied from the voltage supply means 15 is applied to the sources and back gates of the FETs Q9 and Q10, and the FET Q
The ground potential V _ss is applied to the sources of 11 and Q12. The output node of the level shift circuit 11a is FETQ
9 and the drain of the FET Q11 are connected to each other, and this output node is connected to the input node of the changeover switch 11b.

The changeover switch 11b is a pMOS F
Comprised of ETQ13 and nMOS FETQ14,
The gates of the ETQ 13 and the FET Q14 are connected to each other to serve as an input node of the changeover switch 11b, and the drains thereof are connected to serve as an output node. A potential V _pp higher than the power supply potential V _cc supplied from the voltage supply means 15 is applied to the source and back gate of the FET Q13, and the FET Q1
The power source potential V _cc is applied to the source of No. 4.

FIG. 4 shows the complementary M shown in FIG.
3 is a cross-sectional structure diagram showing a well structure of the OS inverter 1. FIG. The n-well 19 for the power supply line is formed in the upper part of the p substrate 21.
And an n well 20 for the FET Q1 are formed.
A p-well 18 for the FET Q2 is formed in the upper part of the well 19 to form a triple well structure. Also, n
In the upper part of the well 20, impurity diffusion layers 11d, 25, 23 for the back gate, source and drain electrodes are formed.
However, in the upper portion of the p-well 18, the impurity diffusion layers 10d, 2 for the back gate, source and drain electrodes are formed.
4 and 22 are respectively formed, and the n well 20 and the p well 1 are formed.
The gates 17 and 16 are formed on the upper portion of 8 with an insulating layer (not shown) interposed therebetween. Switch circuit 10,
11 is formed in a well (not shown) whose potential is fixed.

Below, such a complementary MO
The operation of the S inverter 1 will be described. Complementary M
When the OS inverter 1 does not operate, the H level signal of the control clock signal bar φ is input from the clock signal generator 14 to the switch circuits 10 and 11.
From the switch circuit 10, a potential V _bb lower than the ground potential V _ss
(<0), a potential V _pp higher than the power source potential V _cc is output from the switch circuit 11, and the FET Q2 and the FET Q1 are output.
Applied to the back gate of. At this time, FET Q2,
The FET Q1 has a threshold potential with an absolute value larger than that when the ground potential V _ss and the power supply potential V _cc are applied to each back gate, and the subthreshold current is small.

When the complementary MOS inverter 1 operates, the L level signal of the control clock signal bar φ is input from the clock signal generator 14 to the switch circuits 10 and 11, and the ground potential V _ss is supplied from the switch circuit 10. From the switch circuit 11, the power supply potential V _cc
Is output and applied to the back gates of FETQ2 and FETQ1, respectively. At this time, FETQ2 and FETQ1
Is a potential V lower than the ground potential V _ss to each back gate.
_The threshold potential has a smaller absolute value than when the potential V _pp higher than _bb and the power supply potential V _cc is applied, and the subthreshold current increases, but the switching speed becomes faster.

When an H level (power supply potential V _cc ) logic signal is input from the input node IN, the FET Q1 is turned off and the FET Q2 is turned on, and the L level (ground potential V _ss = 0 V) logic signal is supplied via the FET Q2. Is the output node OU
It is output from T. On the other hand, when an L level (ground potential V _ss = 0V) logic signal is input from the input node IN,
FETQ1 turns on, FETQ2 turns off, and FETQ
A logic signal of H level (power supply potential V _cc ) is output from the output node OUT via 1.

The operation of the switch circuit 10 shown in FIG. 2 will be described below. As mentioned above, the complementary MO
When the S inverter 1 does not operate, the H level signal of the control clock signal bar φ is input from the clock signal generator 14. At this time, the FET Q4 is turned on, the FET Q5 is turned on, and the power supply potential V is turned on via the FET Q4. _cc is output from the level shift circuit 10a.
At this time, FETQ3 and FETQ6 are turned off, and F
There is no short circuit in ETQ5 and FETQ4. When the power supply potential V _cc is input from the level shift circuit 10a, in the changeover switch 10b, the FET Q7 is turned on and the FET Q8 is turned off, and the potential V _bb lower than the ground potential V _ss is output via the FET Q7.

On the other hand, as described above, the complementary M
When the OS inverter 1 operates, the L level signal of the control clock signal bar φ is input from the clock signal generator 14, and at this time, the FET Q3 is turned on and the FET Q6 is turned on, and the ground potential is supplied via the FET Q6. low potential V _bb than V _ss is output from the level shift circuit 10a. At this time, FET Q4 and FE
TQ5 is turned off, and FETQ6 and FETQ3 are not short-circuited. When the potential V _bb is input from the level shift circuit 10a, the changeover switch 10b
Then, FETQ8 is on, FETQ7 is off, and F
The output node becomes the ground potential V _ss via the ETQ8.

The operation of the switch circuit 11 shown in FIG. 3 will be described below. As mentioned above, the complementary MO
When the S inverter 1 does not operate, the H level signal of the control clock signal bar φ is input from the clock signal generator 14. At this time, the FET Q10 is turned on, the FET Q11 is turned on, and the level shift circuit is turned on via the FET Q11. The output node of 11a is the ground potential V _ss.
become. At this time, the FET Q9 and the FET Q12 are turned off, and the FET Q11 and the FET Q10 are not short-circuited. Ground potential V _ss is level shift circuit 1
When input from 1a, in the changeover switch 11b, the FET Q13 is turned on and the FET Q14 is turned off, so that the potential V _pp higher than the power source potential V _cc is output via the FET Q13.

On the other hand, as described above, the complementary M
When the OS inverter 1 operates, the L level signal of the control clock signal bar φ is input from the clock signal generator 14, and at this time, the FET Q9 is turned on, the FET Q12 is turned on, and the FET Q9 is turned on.
The potential V _pp higher than the power source potential V _cc is the level shift circuit 11
It is output from a. At this time, FETQ10 and FETQ
11 is turned off, and FETQ12 and FETQ9 are not short-circuited. The potential V _pp is the level shift circuit 11a
Is input from the F switch,
ETQ13 is off, FETQ14 is on and FET
The power supply potential V _cc is output via Q14.

In the above description, pMOS-
Although an example of a configuration in which the back gate bias can be switched for both FET and nMOS-FET is shown, pMOS-FET
It is also possible to have a configuration in which the back gate bias can be switched only by itself or only by the nMOS-FET. In that case,
Only the pMOS-FET is capable of switching the back gate bias, and has a p-type twin-well structure for the nMOS.
The configuration in which only the -FET can be switched can be realized by the twin well structure of the n substrate, and the triple well structure as shown in FIG. 4 is not required. Also, the voltage supply means 1
Reference numerals 3 and 15 do not have to be circuits provided inside the semiconductor circuit, and may be terminals that relay a potential given from outside the semiconductor circuit to the inside of the semiconductor circuit.

Example 2. 5 and 6 are block diagrams showing the configuration of an example of a MOS-DRAM according to the fifth and sixth inventions. The external row address signal is input to the input terminal ex. A _{0 to} e
x. The data is input from A _n to the input buffer 26, latched by the latch circuit 27, and then sent to the row decoder 29 via the buffer gate column 39. The row decoder 29 selects word lines WL _{0 to} WL _m and selects the selected word line WL _0.
..- WL _m are driven by the word driver 30, and the memory cell 57 on the word line in the memory cell array 33 is driven.
To access. The contents of the accessed memory cell 57 are transferred to the bit lines BL _{0 to} BL _k , and the sense amplifier S
At the same time as being amplified in A _{0 to} SA _k , the original memory cell 57 is rewritten.

On the other hand, an external column address signal input through an input terminal, an input buffer, a latch circuit, and a buffer gate column (not shown) is sent to the column decoder 31, and the column decoder 31 selects the sense amplifiers SA _{0 to} SA _k . Then, the outputs amplified in the above of the selected sense amplifiers SA _{0 to} SA _k are I / O gate 40 and I / O bus 4.
After passing 1, the signal is amplified by the preamplifier 34 and output from the output buffer 35.

Further, the row-related operation of the MOS-DRAM 42
Of the input buffer 26, the latch circuit 27, and the N stages
Buffer gate 39, row decoder 29, word driver
When 30 logic circuits operate, the logic circuits are configured.
The back gate bias potential of the pMOS-FET is
Control clock signal bar φ described₁Received
The switch circuit 43R allows the power supply from the voltage supply means 44R.
Rank V_ppTo power supply potential V _ccIs switched to. Similarly,
Back gate of nMOS-FET forming the logic circuit
Bias potential is control clock signal bar φ₁To
The switch circuit 45R receives the voltage supply means 46R.
Potential V from_bbTo ground potential V_ssIs switched to.

On the other hand, when the logic circuits of the I / O gate 40, the preamplifier 34, the column decoder 31, the M-stage buffer gate (not shown) and the output buffer 35, which are column-related operation circuits of the MOS-DRAM 42, operate. The back gate bias potential of the pMOS-FET constituting the logic circuit is switched from the potential V _pp from the voltage supply means 44C to the power source potential V _cc by the switch circuit 43C which receives the control clock signal φ ₂ described later. To be Similarly, the back gate bias potential of the nMOS-FET forming the logic circuit is switched from the potential V _bb from the voltage supply means 46C to the power source potential V _ss by the switch circuit 45C which receives the control clock signal bar φ _2. . The switch circuits 43R and 43C are similar to the switch circuit 11 shown in FIG. 3, and the switch circuits 45R and 45C are similar to the switch circuit 10 shown in FIG.

In the series of operations described above, the clock signal generator 49 causes the inverted signal bar WE of the enable signal and the external RA.
S (Row Address Strobe) signal (external row selection signal) inverted signal bar ex. Control clock signals output in response to RAS, etc., bar φ ₁ , bar φ ₂ , word driver 3
It is controlled by an activation signal φ _W of 0, an activation signal φ _{S of} the sense amplifiers SA _{0 to} SA _k , and the like.

FIG. 7 shows such a MOS-DRAM 42.
3 is a timing chart showing a breakdown of the transmission time of the external RAS signal in each internal part of FIG. In the figure, T0 is the potential of the TTL circuit in the input buffer 26
Conversion time to a circuit potential, T1 is an external row address latch time of the latch circuit 27, the row decoder setup time in Td1 row decoder 29 and the word driver 30 of blocks 28, TS, Tb sense amplifier SA ₀ -SA _k And block 3 consisting of preamplifier 34
2, the memory cell selection time and the sense time, Td2 is the delay time from the preamplifier 34 to the output buffer 35.

Here, the back-gate of the MOS-FET forming the logic circuit of the input buffer 26, the latch circuit 27, the N-stage buffer gate 39, the row decoder 29, and the word driver 30 which are the row-related operation circuits of the MOS-DRAM 42. A control clock signal for switching the gate bias potential is φ ₁ , and a preamplifier 3 which is a column operation circuit.
4. MOS-F forming the logic circuit of the output buffer 35
The control clock signal for switching the back gate bias potential of ET is represented by bar φ ₂ . In this case, for example, in the clock signal generator 49, the control clock signal bar φ ₁ is the inverted signal bar ex. It is created by the fall of RAS and the rise of the activation signal φ _W of the word driver 30, and the control clock signal bar φ ₂ has the sense amplifiers SA _{0 to} SA _k.
Rising edge of the activation signal φ _S of the external RAS signal and the inverted signal bar ex. Created with the rise of RAS.

FIGS. 8A to 8C show a MOS-DRAM.
42, the control clock signal bar φ ₁ , the bar φ ₂ and the inverted signal bar ex. 6 is a timing chart showing the relationship of RAS. The time T0, T1, Td1 consumed in the input buffer 26, the latch circuit 27, the N-stage buffer gate 39, the row decoder 29, and the word driver 30, which is the row-related operation circuit of the MOS-DRAM 42, that is, the input buffer 26, During the time T0, T1, Td1 when the latch circuit 27, the N-stage buffer gate 39, the row decoder 29, and the word driver 30 operate (FIG. 8A), the L level signal of the control clock signal bar φ ₁ is switched. Input to the circuit 43R and the switch circuit 45R (see FIG. 8).
(B)). On the other hand, the times Tb and Td2 consumed in the preamplifier 34 and the output buffer 35, which are column-type operation circuits of the MOS-DRAM 42, that is, during the operating times Tb and Td2 of the preamplifier 34 and the output buffer 35 (see FIG. 8).
In (a), the L level signal of the control clock signal bar φ ₂ is input to the switch circuit 43C and the switch circuit 45C (FIG. 8C).

Therefore, when the input buffer 26, the latch circuit 27, the N-stage buffer gate 39, the row decoder 29, and the word driver 30, which are row-related operation circuits of the MOS-DRAM 42, operate, the switch circuit 43R and the switch circuit 45R. From the power supply potential V _cc and the ground potential V _ss
Is output, and each pMOS-FET of the above-mentioned operation circuit is output.
Is applied to the back gate of each nMOS-FET. At this time, each pMOS-FET and each nMOS-FET
Is a potential V higher than the power source potential V _cc to each back gate.
_The threshold potential has a smaller absolute value than that when the potential V _bb lower than _pp and the ground potential V _ss is applied, and the subthreshold current increases, but the switching speed becomes faster.

On the other hand, the input buffer 26 and the latch circuit 2
7. When the N-stage buffer gate 39, the row decoder 29, and the word driver 30 do not operate, the switch circuit 4
A potential V _pp higher than the power source potential V _cc and a potential V _bb lower than the ground potential V _ss are output from the 3R and the switch circuit 45R, and each pMOS-FET and each n of the above-mentioned operation circuit are output.
It is applied to the back gate of the MOS-FET. At this time, each pMOS-FET and each nMOS-FET have a threshold potential having an absolute value larger than that when the power supply potential V _cc and the ground potential V _ss are applied to each back gate, and the sub-threshold is obtained. The current is getting smaller.

Similarly, when the preamplifier 34 and the output buffer 35, which are column-type operation circuits of the MOS-DRAM 42, operate, the switch circuit 43C and the switch circuit 4 are operated.
The power source potential V _cc and the ground potential V _ss are output from 5C,
Each pMOS-FET and each nMO of the above-mentioned operation circuit
It is applied to the back gate of the S-FET. At this time, each pMOS-FET and each nMOS-FET have a potential V _pp higher than the power source potential V _cc and a potential V _bb lower than the ground potential V _ss applied to their back gates.
The threshold potential has a small absolute value, and the subthreshold current increases, but the switching speed becomes faster.

On the other hand, when the output buffer 35 does not operate, the switch circuit 43C and the switch circuit 45C output the potential V _pp higher than the power source potential V _cc and the potential V _bb lower than the ground potential V _ss , respectively, and the above-mentioned operation circuits. Each pMO
It is applied to the S-FET and the back gate of each nMOS-FET. At this time, each pMOS-FET and each nMO
The S-FET has a threshold potential with a larger absolute value than when the power supply potential V _cc and the ground potential V _ss are applied to each back gate, and the subthreshold current is small.

Example 3. FIG. 9 shows the M according to the seventh and eighth inventions.
It is a block diagram showing the composition of one example of the memory cell which constitutes OS-DRAM. The nMOS FET 37 and the capacitor 50 are connected by the source of the FET 37 and one electrode of the capacitor 50, the word line WL is connected to the gate of the FET 37, the bit line BL is connected to the drain, and the capacitor 50 is connected to the capacitor 50.
The cell plates 51 are connected to the other electrodes of the cells. The back gate of the FET 37 has a voltage supply means 48.
A switch circuit 36 for switching to the back gate bias potential V _bb2 from b or the potential V _bb1 from the voltage supply means 48a (V _bb1 <V _bb2 ) is connected.

FIG. 10 is a circuit diagram showing a configuration example of the switch circuit 36, which is substantially the same as the circuit diagram of the switch circuit 10 shown in FIG. The voltage supply means 13, the ground potential V _SS , the clock signal generator 14, the control clock signal bar φ, the level shift circuit 10a, and the changeover switch 10b in FIG.
8a, the output potential V _bb2 of the voltage supply means 48b, the clock signal generator 49, the external RAS (Row Address Strobe) signal (external row selection signal) ex. It corresponds to the RAS, the level shift circuit 36a, and the changeover switch 36b, and a voltage supply means 48b is added to FIG. In the switch circuit 36, the external RAS signal ex. When the H level signal of RAS is input from the clock signal generator 49, the potential V _bb1 is output, and the external RAS signal ex. R
When the AS L level signal is input, the potential V _bb2 is output. The other operations are similar to those of the switch circuit 10 shown in FIG.

The structure of one embodiment of the MOS-DRAM using the memory cell 38 having such a structure is the MOS-DRA of the semiconductor circuit according to the fifth and sixth inventions shown in FIGS.
It is substantially the same as the block diagram showing the configuration of M. The seventh and eighth inventions have a configuration in which a switch circuit 36, a voltage supply means 48a, and a voltage supply means 48b are added in addition to the configurations of the above-described fifth and sixth inventions. In the MOS-DRAM 42 having such a configuration, the inverted signal bar ex. After the L level signal of RAS is input to the input buffer 26, the row decoder 29 causes the word lines WL _{0 to} WL _m.
Is selected. When an H level signal is given to the selected word lines WL _{0 to} WL _m by the word driver 30 and the FET 37 on the word lines WL _{0 to} WL _m becomes conductive,
Writing or refreshing / reading is performed by charging / discharging the charge of the capacitor 50 via the bit line BL.

On the other hand, the inverted signal bar e of the external RAS signal
x. When the L level signal of RAS is input to the clock signal generator 49, the clock signal generator 49 is
S signal ex. The RAS H level signal is applied to the switch circuit 36.
Output to. The switch circuit 36 uses the external RAS signal ex. When the H level signal of RAS is input, the output is changed from the potential V _bb2 (V _bb2 <0) to a potential V _bb1 lower than that.
To all memory cells 38 of the memory cell array 33.
The back gate bias potential of the FET 37 constituting the _above is switched from the potential V _bb2 (V _bb2 <0) to the lower potential V _bb1 . At this time, F constituting all the memory cells 38
The absolute value of the threshold potential of _ET37 becomes larger than when the potential V _bb2 is applied to the back gate, and the subthreshold leak is reduced. Therefore, when the DRAM 42 is in the active state and the peripheral circuit and the bit line BL are in the active state, the subthreshold leak, which is the main leak at that time, can be reduced, so that the disturb refresh cycle is lengthened. The frequency can be reduced.

To the DRAM 42, an inverted signal bar ex. Of an external RAS signal (external row selection signal) is added. When the H level signal of RAS is input to the input buffer 26, the DRAM 42 becomes inactive. On the other hand, an inverted signal bar e of the external RAS signal
x. When the H-level signal of RAS is input to the clock signal generator 49, the clock signal generator 49 uses the external RA
S signal ex. The switch circuit 36 outputs the L level signal of RAS.
Output to. The switch circuit 36 uses the external RAS signal ex. When RAS at L-level signal is input, the output from the potential V _bb1 switched to the potential V _bb2, the FET37 back gate bias potential of constituting all the memory cells 38 in the memory cell array 33 from the potential V _bb1 to potential V _{bb 2} Switch.

At this time, F constituting all memory cells 38
The absolute value of the threshold potential of ET37 is smaller than when a lower potential V _bb1 than the potential V _bb2 is applied to the back gate, junction leakage is reduced. Therefore, the DRAM 42
Is inactive and the peripheral circuit and the bit line BL are in the standby state, it is possible to reduce the junction leak, which is the main leak at that time. Can be lowered.

In the case of a DRAM using a self-refresh type memory cell that can be refreshed in the memory cell, the self-refreshing is in the same state as the pause refresh.
The self-refresh cycle can be extended. Further, the voltage supply means in the MOS-DRAM according to the above fifth to eighth inventions does not need to be a circuit provided inside the MOS-DRAM, and a potential given from the outside of the MOS-DRAM can be applied to the MOS-DRAM. -It may be a terminal for relaying inside the DRAM.

Example 4. FIG. 11 is a sectional structural view showing another embodiment of the logic circuit constituting the semiconductor circuit according to the present invention and corresponds to FIG. FIG. 12 is a plan view of this. In this embodiment, an nMO of SOI structure is formed on a Si substrate.
The case where S and pMOS-FETs are arranged in parallel is shown. The SiO ₂ layer 62 is formed on the Si substrate 61. pMOS-F
In the source / drain region of ETQ21, p ⁺ layers 63 and 64 are formed, and an n ⁻ channel layer 65 is formed between them. pMOS-FETQ21, nMOS-FETQ22
A SiO ₂ layer 71 is formed between the _two , and elements are separated by the LOCOS method. Source of nMOS-FET Q22
N ⁺ layers 66 and 67 are formed in the drain region, and a p ⁻ channel layer 68 is formed between them. pMOS-
The power supply potential V _cc is applied to the source of the FET Q21, and nM
The ground potential V _ss is applied to the source of the OS-FET Q22.

As shown in FIG. 12, the gate electrode 69 is used for sawing.
N separated from the drain^-The channel layer 65 is illustrated
1, connected to a switch circuit 11 similar to that shown in FIG.
From the switch circuit 11 to the body bias potential Vbody.
-n is applied. The switch circuit 11 has a body bias
Power source potential V_ccOr boosted potential V_ppSwitch to
Can be In addition, the source and
P separated from rain ^-The channel layer 68 is shown in FIGS.
Connected to a switch circuit 10 similar to that shown in
The body bias potential Vbody-p is applied from the switch circuit 10.
Is done. The switch circuit 10 has a body bias potential Vbody.
-p to ground potential V_ssOr negative potential V_bbCan be switched to
Wear.

Further, p formed on the n ⁻ channel layer 65
Gate electrode 69 and p ^- channel layer of MOS-FET Q21
Gate electrode 70 of nMOS-FET Q22 formed on 68
An input signal is supplied to. And p
Drain of MOS-FET Q21 and nMOS-FET Q
An output signal is output from the drain of 22.

The operation of the logic circuit having the above configuration will be described. When this logic circuit does not operate, the H level signal of the inverted control clock signal bar φ is input from the clock signal generator 14 to the switch circuits 10 and 11, and the switch circuit 10 outputs a potential V lower than the ground potential V _{ss. bb} (<0), but a potential V _pp higher than the power source potential V _cc is output from the switch circuit 11, and each is nMOS-FE.
Body bias potential V of TQ22, pMOS-FET Q21
Body-p and body bias potential Vbody-n. At this time, nMOS-FETQ22, pMOS-FETQ21
Is a threshold potential having a larger absolute value than when the ground potential V _ss and the power supply potential V _cc are applied to each channel layer, and the subthreshold current is small.

On the contrary, when the logic circuit operates, the L level signal of the inverted control clock signal bar φ is input from the clock signal generator 14 to the switch circuits 10 and 11, and the ground potential V _ss is output from the switch circuit 10. , The switch circuit 11 outputs the power supply potential V _cc , each of which is n
The body bias potential Vbody-p and the body bias potential Vbody-n of the MOS-FET Q22 and the pMOS-FET Q21 are set. At this time, nMOS-FET Q22 and pMO
The S-FET Q21 has a threshold potential whose absolute value is smaller than that when the potential V _bb lower than the ground potential V _ss and the potential V _pp higher than the power supply potential V _cc are applied to each channel layer, The threshold current is increased but the switching speed is faster.

When an H-level (power supply potential V _cc ) logic signal is input from the input node IN, the pMOS-FET
Q21 turns off, nMOS-FET Q22 turns on, and nM
L level (ground potential V _ss = 0 through OS-FET Q22
V) logic signal is output from the output node OUT. On the other hand, from the input node IN to L level (ground potential V _ss = 0V)
PMOS-FETQ21 is turned on and nMOS-FETQ22 is turned off when the logic signal of
A logic signal of H level (power supply potential V _cc ) is output from the output node OUT via the FET Q21.

As described above, in this embodiment, both the high speed switching characteristic and the small subthreshold current characteristic can be achieved. Further, in the device configuration shown in FIG. 4, since the bias voltage of the well of bulk structure having a relatively large capacitance is changed, the switching time is relatively long and the charge / discharge current accompanying it is relatively large. However, in the device configuration shown in FIG. 11, the capacities of the n ⁻ channel layer 65 and the p ⁻ channel layer 68 are smaller than the capacity of the well described above, so that the switching time can be shortened and the charge / discharge current accompanying it can be made relatively small. be able to. Furthermore, fixing the body voltage eliminates kinks in the SOI transistor, improving the withstand voltage.

Example 5. FIG. 13 is a sectional structural view showing still another embodiment of the logic circuit constituting the semiconductor circuit according to the present invention. In this embodiment, pMOS-FET Q21, n
The element isolation between the MOS-FET Q22 is performed by the field shield (FS) method instead of the LOCOS method. That is, FS layers 74 and 74 made of polysilicon are formed on both outer sides of the p ⁺ layers 63 and 64 of the pMOS-FET Q21, and 0 V is applied to turn off the channel to form n ⁻ layers 72 and 73. ing. In addition, the n ⁺ layer 66 of the nMOS-FET Q22,
On both outer sides of 67, FS layers 74 and 74 are formed and a negative bias is applied to turn off the channel to p ^- layers 75 and 76.
Are formed. p ⁺ layer 77 between n ⁻ layer 73 and p ⁻ layer 75
Are formed.

The body bias potential Vbody-n is applied from the switch circuit 11 to the n ^- channel layer 65 and the n ^- layers 72 and 73. P ⁺ layer 77, p ^- channel layer
The body bias potential Vbody-p is applied from the switch circuit 10 to the 68 and p ⁻ layers 75 and 76. pM
The power supply potential V _cc is applied to the FS layers 74 and 74 of the OS-FET Q21, and the ground potential V _ss is applied to the FS layers 74 and 74 of the nMOS-FET Q22. Other configurations are the same as those shown in FIG. 11, and the same reference numerals are given to omit the description.

Also in this embodiment, the same effect as that of the above-mentioned embodiment can be obtained. Further, in this embodiment, the layout for the body bias potential as shown in FIG. 12 is not required, and the FS layer 74
The potential can be fixed in the n ⁻ layers 72 and 73 or the p ⁻ layers 75 and 76 below. An n ⁺ layer may be formed between the n ⁻ layer 73 and the p ⁻ layer 75, and the body bias potential Vbody-n may be applied to the n ⁺ layer.

Example 6. FIG. 14 is a sectional structural view showing still another embodiment of the logic circuit constituting the semiconductor circuit according to the present invention. In this embodiment, element isolation is performed by the FS method and the LOCOS method. That is, the SiO ₂ layer 71 is formed instead of the p ⁺ layer 77 shown in FIG. The body bias potential Vbody-n is applied from the switch circuit 11 to the n ^- channel layer 65 and the n ^- layers 72 and 73. The p ^- channel layer 68 and the p ^- the switch circuit into the layer 75, 76
From 10 the body bias potential Vbody-p is applied. Other configurations are the same as those shown in FIG. 13, and therefore the same reference numerals are given and the description thereof is omitted. The present invention can be applied to the case where the element isolation is performed by the FS method and the LOCOS method as described above, and the same effect as that of the above-described embodiment can be obtained.

Example 7. FIG. 15 is a sectional structural view showing still another embodiment of the logic circuit constituting the semiconductor circuit according to the present invention. In this embodiment, an nMOS-FE having the same configuration as the nMOS-FET Q22 is used instead of the pMOS-FET Q21.
It shows a case where TQ23 is formed and nMOS-FETs are arranged in parallel. n ⁺ layer between nMOS-FET Q22 and Q23
78 is formed. FS of nMOS-FET Q22, Q23
Layers 74, 74, 74, 74 and p ^- layer 75 of the nMOS-FET Q22,
The ground potential V _ss is applied to the 76 and p ⁻ channel layers 68, and the power supply potential V _cc is applied to the n ⁺ layers 78. p of nMOS-FET Q23 ^- layer 75, 76 and p ^-
The switch circuit 10 is connected to the channel layer 68. Other configurations are the same as those shown in FIG. 13, and therefore the same reference numerals are given and the description thereof is omitted. The present invention provides such an nMOS-
It can also be applied to the case where FETs are arranged side by side, and the same effect as the above-mentioned embodiment can be obtained.

In each of the above embodiments, the power supply potential V _cc <potential V _pp , the potential V _bb <ground potential V _ss , the potential V
_Although described as _bb1 <potential V _bb2 , they are relative ones, and the same _{applies to} power source potential V _cc > potential V _pp , potential V _bb > ground potential V _ss , and potential V _bb1 > potential V _bb2. Can be described.

Example 8. FIG. 16 shows the present invention (23rd invention).
FIG. 9 is a circuit diagram showing an eighth embodiment of the semiconductor circuit according to the present invention. Fig. 16
2 shows a case where three inverters I ₁₁ , I ₁₂ , and I ₁₃ each composed of a bulk-structured FET having a well are connected in series. The inverter I ₁₁ has a power supply line V _cc (power supply potential: V _cc ) and a ground line V _ss (ground potential:
V _ss ) pMOS FET Q81 and nMOS FET
Q82 is connected in series. Similarly, the inverter I ₁₂
(I ₁₃ ) is a pMOS F between the power supply line V _cc and the ground line V _ss.
The ETQ83 (Q85) and the nMOS FET Q84 (Q86) are connected in series.

The pMOS FET Q81 and the nMOS
Is connected to the gate of the FET Q82, and this connection point is used as the input node IN. Also, pMOS FET Q81,
The drain of the nMOS FET Q82 is connected, and the connection point is the pMOS FET Q83 and nM of the inverter I _12.
It is connected to the connection point of the gate of the FET Q84 of the OS.
Similarly, pMOS FET Q83 and nMOS FET Q84
The connection point of the drain of is the FMOS of the pMOS of the inverter I _13.
The output node OUT is connected to the connection point of the gates of the ETQ85 and the FET Q86 of the nMOS, and the connection point of the drains of the FET Q85 of the pMOS and the FET Q86 of the nMOS.

The back gates of the pMOS FETs Q81 and Q85 are connected to the switch circuit 11 that switches between the power supply potential V _cc and the potential V _pp, and the back gate of the FET Q83 is connected to the same power supply line V _cc as the source. . The back gates of the nMOS FETs Q82 and Q86 are connected to the same ground line V _ss as the sources, and the back gate of the FET Q84 is
Switch circuit 10 for switching between ground potential V _ss and potential V _bb
Connected with.

In this embodiment, at the time of standby, the input node I
A clock signal of H level is input to N. pM
The potential V _pp is applied from the switch circuit 11 to the back gates of the FETs Q81 and Q85 of the OS, and the power source potential V _cc is applied to the back gates of the FET Q83. FE of nMOS
The ground potential V _ss is applied to the back gates of TQ82 and Q86, and the potential V _bb is applied from the switch circuit 10 to the back gate of the FET Q84.

On the other hand, when active, the input node IN
An L level clock signal is input. FET Q8
Power supply from switch circuit 11 to the back gate of Q85.
Rank V_ccIs applied to the back gate of FET Q83.
Power supply potential V_ccIs applied. Also FETQ
The ground potential same as the source potential is applied to the back gate of 82 and Q86.
V_ssIs applied to the back gate of FET Q84.
H circuit 10 to ground potential V _ssIs applied.

By controlling the potential applied to the back gate in this way, the pM that is off during standby is
The threshold voltage of the FETs Q81 and Q85 of the OS becomes higher than the threshold voltage of the active time, and the threshold voltage of the FET Q84 of the nMOS turned off at the standby time becomes higher than the threshold voltage of the active time. Therefore, it is possible to reduce the subthreshold current flowing in the FET that is off during standby. High-speed operation in the inverter train can be realized by performing threshold scaling on the low-voltage circuit as well.

Example 9. FIG. 17 shows the present invention (23rd invention).
FIG. 10 is a circuit diagram showing a ninth embodiment of the semiconductor circuit according to the present invention. Figure 17
₄ shows a case where _four inverters I ₁ , I ₂ , I ₃ , and I ₄ each composed of an SOI structure FET are connected in series. The inverter I ₁ has a pM between the power supply line V _cc (power supply potential: V _cc ) and the ground line V _ss (ground potential: V _ss ).
The FET Q31 of OS and the FET Q32 of nMOS are connected in series. Similarly, the inverter I ₂ (I ₃ , I ₄ )
Is a pMOS FET Q33 between the power supply line V _cc and the ground line V _ss.
(Q35, Q37) and nMOS FET Q34 (Q36, Q3
8) and are connected in series.

Then, the pMOS FET Q31 and the nMOS
The gate of the FET Q32 is connected, and this connection point is used as the input node IN. Also, pMOS FET Q31,
The drain of the nMOS FET Q32 is connected, and the connection point is the pMOS FET Q33 and nM of the inverter I _2.
It is connected to the connection point of the gate of the FET Q34 of the OS.
Similarly, pMOS FET Q33 and nMOS FET Q34
The connection point of the drain of is the pMOS F of the inverter I _3.
The ETQ35 and the gate of the nMOS FET Q36 are connected to each other, and the drain of the pMOS FET Q35 and the nMOS FET Q36 is connected to the p of the inverter I ₄ .
It is connected to the connection point of the gates of the MOS FET Q37 and the nMOS FET Q38. The connection point of the drains of the pMOS FET Q37 and the nMOS FET Q38 is the output node O.
It is made as UT.

The bodies of the pMOS FETs Q31 and Q35 (including the channel layer and the channel-off layer below the FS layer) are connected to the same power supply line V _cc as the source, and the nMOS FETs are connected.
The bodies of Q34 and Q38 are connected to the same ground line V _ss as the source. The bodies of the pMOS FETs Q33 and Q37 are connected to a switch circuit 81 that selectively _applies the potential V _pp1 or the potential V _pp2 (V _pp1 > V _pp2 ), and nMO
The bodies of the FETs Q32 and Q36 of S are connected to a switch circuit 82 which selectively _{applies the} potential _Vbb1 or the potential _Vbb2 ( _Vbb1 < _Vbb2 ).

The switch circuit 81 is supplied with the potential V _pp1 by the voltage supply means 83, the potential V _pp2 by the voltage supply means 84, and the inverted clock signal bar φ from the clock signal generation circuit 85. Has become. The potential V _bb1 is applied to the switch circuit 82 by the voltage supply means 86, and the potential V _bb1 is applied by the voltage supply means 87.
_bb2 is given, and further the inverted clock signal bar φ is given from the clock signal generating circuit 85.
Above, switch circuits 81, 82, voltage supply means 83, 84, 86, 87
A circuit including the clock signal generating circuit 85 and a substrate (body) bias switching circuit 88 is used.

The switch circuit 82 is an external RAS shown in FIG.
Signal ex. This is the same as the case where the RAS is the clock signal (φ or bar φ) generated by the clock signal generation circuit 85. The output side of the changeover switch (36b) is connected to the bodies of the nMOS FETs Q34 and Q38.
Note that either the potential V _bb1 or the potential V _bb2 is the ground potential V
_If the potential V _bb2 is _set to the ground potential V _ss , the configuration is similar to that shown in FIG. At this time, V _bb1 <V
_Must be _bb2 .

The switch circuit 81 is supplied with the voltage shown in FIG.
The supply means 15 is replaced with the voltage supply means 83 and the potential V_ppPotential V
_pp1And the power supply potential V_ccIs obtained from the voltage supply means 84
Potential V _pp2do it. Still the potential V_pp1Or potential V
_pp2Power source potential V_ccCan be the potential
V_pp2Is the power supply potential V_ccIf so, similar to the configuration shown in FIG.
Become. At this time V_pp1> V_pp2Must.

The operation of the semiconductor circuit configured as described above will be described. The input signal input from the input node IN during standby is at L level, and the body bias potentials of the FETs Q31, Q34, Q35, and Q38 that are on during standby are the same as the source potential. Further, the body bias potentials of the nMOS FETs Q32 and Q36 which are turned off during standby are the potential _Vbb1 , and the pMOS FETQ33,
The body bias potential of Q37 is the potential V _pp1 .

When active, the input signal input from the input node IN becomes H level, and the FETs Q32, Q33, Q
36, Q37 turns on. At this time, nMOS FET Q32,
The potential _Vbb2 is applied to the body of Q36 by the substrate (body) bias switching circuit 88, and the pMOS FETs Q33 and Q37 are applied.
A potential V _pp2 is applied to the body of the substrate by a substrate bias switching circuit 88. FET Q31, which is off again,
The body bias potentials of Q34, Q35 and Q38 are the same as the source potential.

As in the first embodiment, nM is set in the standby mode.
The body bias potential of the FET of OS is made lower than that at the active time, and the body bias potential of the FET of pMOS is made higher than that at the active time to increase the threshold voltage. This makes it possible to reduce the subthreshold current. Further, since the threshold voltage is made small during the active state, the switching speed of the inverter train can be increased.

In this embodiment, instead of controlling the body bias potentials of all the FETs forming the inverter,
FETs turned off during standby Q32, Q33, Q36, Q37
Only the substrate (body) bias switching circuit 88 is connected to control the body bias potential. Therefore, the consumption current required for switching the body bias potential is half that in the case of controlling the body bias potentials of all the FETs. Also, the switching speed of the body bias potential is high.

When the inverter array is manufactured in a bulk structure having wells as shown in FIG. 4, the substrate potential is 4%.
Since there are several types, 4 wells are required. In this case, there are problems that the layout area becomes large due to separation between wells and the charge and discharge with respect to the parasitic capacitance of the well is large. However, M of SOI structure as shown in FIG.
Such a problem does not occur when the inverter array is made of OSFET. Therefore, the present embodiment is based on the SOI structure MOSF.
Good effects can be obtained when applied to an inverter train composed of ET. From the above, it is possible to realize a logic circuit which has a low threshold voltage, a small standby current (subthreshold current), and is capable of high-speed operation.

Example 10. FIG. 18 shows the present invention (23rd, 26th).
FIG. 11 is a circuit diagram showing a tenth embodiment of a semiconductor circuit according to the invention). In this embodiment, the pMOS FETQ in the ninth embodiment is used.
FE of pMOS whose threshold voltage is smaller than these (eg 0.3 to 0.4V) instead of 31, Q35 (eg threshold voltage: 0.7V)
I am using TQ41 and Q45. N in Example 9
In place of the MOS FETs Q34 and Q38 (for example, threshold voltage: 0.7V), the threshold voltage is smaller than these (for example, 0.3 to 0.4).
V) nMOS FETs Q44 and Q48 are used. Other configurations are the same as the configurations shown in FIG. 17, and are denoted by the same reference numerals, and description thereof will be omitted. A bulk structure FET may be used.

In this embodiment, since the threshold voltages of the FETs Q41, Q44, Q45, Q48 which are turned on at the time of active state are made small, current instantaneously flows at the time of transition from the standby state to the active state. Therefore, a faster switching operation than that of the ninth embodiment is possible.

Embodiment 11 FIG. 19 shows the present invention (24th and 25th embodiments).
FIG. 13 is a circuit diagram showing Embodiment 11 of the semiconductor circuit according to the invention). In this embodiment, four inverters I ₅ , I ₆ , I ₇ , and I ₈ using the MT-MOS structure are shown. The input node IN is the connection point of the gates of the pMOS FET Q51 and the nMOS FET Q52 of the inverter I ₅ , and the connection point of the pMOS FET Q51 and the drain of the nMOS FET Q52 is the pMOS FET Q53 and nMO of the inverter I _6.
It is connected to the connection point of the gate of the FET Q54 of S. Similarly, the connection point between the drains of the pMOS FET Q53 and the nMOS FET Q54 is the pMOS FE of the inverter I _7.
It is connected to the connection point of the gates of TQ55 and nMOS FET Q56, and is connected to the pMOS FET Q55 and nMOS F
The connection point of the drain of ETQ56 is pM of the inverter I ₈ .
It is connected to the connection point of the gates of the FET Q57 of the OS and the FET Q58 of the nMOS. pMOS FET Q57 and n
The drain node of the MOS FET Q58 is the output node OU.
It is called T.

PMOS FETs Q51, Q53, Q55, Q57
Source is connected to the sub power supply line V _cc1
Sources of FETs Q52, Q54, Q56, and Q58 are sub-ground line V
_It is connected to _ss1 . The sub power supply line _Vcc1 is a _{pMOS FET Q59} in which the inverted clock signal bar φ is applied to the gate and the power supply potential _Vcc is applied to the body (back gate).
_Is connected to the power supply line _Vcc via. Sub ground line V _ss1
Is supplied with the clock signal φ at its gate, and the ground potential V _ss
NMOS FE in which is given to the body (back gate)
It is connected to the ground line V _ss via TQ60. FETQ
The threshold voltages of 59, Q60 are inverters I ₅ , I ₆ , I ₇ ,
FETs Q51, Q52, Q53, Q54, Q55, which form I ₈
It is larger than the threshold voltage of Q56, Q57, Q58.

PMOS FETs Q51, Q53, Q55, Q57
The body (back gate) of is connected to the switch circuit (81) of the substrate (body) bias switching circuit 88.
The bodies (back gates) of the FETs Q52, Q54, Q56, Q58 of the OS are connected to the switch circuit (82) of the substrate (body) bias switching circuit 88.

In the semiconductor circuit having the above structure, the FETs Q59 and 60 are turned off during standby. As a result, the power supply potential V _cc is not _applied to the sub power supply line V _cc1 , and the ground potential V _ss is not _applied to the sub ground line V _ss1 . Further, the potential V _pp1 is applied to the body (back gate) of the pMOS FETs Q51, Q53, Q55, Q57,
The potential V _bb1 is applied to the bodies (back gates) of the FETs Q52, Q54, Q56, Q58 of.

When active, the FETs Q59 and 60 are turned on.
To As a result, pMOS FETs Q51, Q53, Q
55, Q57 source is the sub power line V_cc1Power supply potential through
V_ccIs given, and nMOS FETs Q52, Q54, Q56,
The source of Q58 is the sub ground line V _ss1Through the ground potential V_ss
Is given. Furthermore, pMOS FETs Q51, Q53, Q5
5, The potential V is applied to the body (back gate) of Q57_pp2Mark
The nMOS FETs Q52, Q54, Q56, Q58
Di (back gate) potential V_bb2Is applied.

In the present invention, even if a current flows in the inverter train and the potential of the sub power supply line V _{cc1 and} the potential of the sub ground line V _{ss 1} are _settled , the threshold voltage in the standby mode is set to be high.
Since the body (back gate) bias potential of ET is controlled, it is possible to prevent delay in switching and change in logic.

Embodiment 12. FIG. 20 shows the present invention (Nos. 23 and 2).
13 is a circuit diagram showing a twelfth embodiment of the semiconductor circuit according to 5).
In this embodiment, the body (back gate) of the pMOS FETs Q51 and Q55 shown in FIG. 19 is connected to the power supply line V _cc , and the pMO
The body (back gate) of only the S FETs Q53 and Q57 is connected to the substrate (body) bias switching circuit 88. Further, the bodies (back gates) of the nMOS FETs Q54 and Q58 shown in FIG. 19 are connected to the ground line V _ss , and the nMOS FETs
The body (back gate) of only Q52 and Q56 is connected to the substrate (body) bias switching circuit 88. The other configurations are the same as those shown in FIG. 19, and the same reference numerals are given and the description thereof is omitted.

In this embodiment, F turned off during standby
The substrate bias potential of only ETQ52, Q53, Q56, Q57 is variable. As a result, the number of FETs for changing the substrate bias potential by the substrate (body) bias switching circuit 88 becomes half that in the eleventh embodiment, so that the power consumption required for switching the substrate bias potential can be reduced to 1/2. It can be switched at high speed.

Embodiment 13 FIG. 21 shows the present invention (the 27th invention).
26 is a circuit diagram showing Example 13 of the semiconductor circuit according to FIG.
The case where the present invention is applied to the word driver shown in FIG.
The word driver WD has a power line V connected to a boost power source.
pMOS FET Q6 between _pp2 (potential: V _pp2 ) and ground
1, nMOS FET Q62 is connected in series, and p
The decoder signal X is input to the gates of the MOS FET Q61 and nMOS FET Q62, and the pMOS FET Q61, n is input.
The word line WL is connected to the drain connection point of the MOS FET Q62.
Is connected. Word driver W having such a configuration
N Ds are arranged in the vertical direction and m rows are arranged in the horizontal direction (WD
_11- WD _mn ). And the pMOS of each word driver WD
The body (back gate) of the FET Q61 is connected to the switch circuit 81 similar to that in the above-described embodiment.

In the semiconductor circuit having such a configuration,
The body (back gate) bias potential of the pMOS FET Q61 is set to the potential V during standby by the switch circuit 81.
_pp1 Then, when active, the potential V _pp2 (V
_pp1 > _Vpp2 ) and the selected word driver WD
The word line WL becomes active by inputting the decoder signal X ₁ to (for example, the word driver WD ₁₁ ). Also in this embodiment, the DRA in which the standby current (subthreshold current) that flows during standby is small
M can be realized.

Embodiment 14 FIG. 22 shows the present invention (the 28th invention).
14 is a circuit diagram showing Embodiment 14 of the semiconductor circuit according to the present invention, showing a case where a word driver having a hierarchical structure is realized by using the present invention. FIG. The word drivers WD arranged in the vertical direction shown in FIG. 21 are defined as word driver columns B1, B2, ... Bm in column units. Body of pMOS FET Q61 (back gate)
Are connected to the switch circuit 81 for each word driver column B. Potentials V _pp1 and V _pp2 are applied to the switch circuits 81 from the voltage supply means 83 and 84. Further, a NOR circuit N which receives as input the clock signal φ which becomes L level when active and the column selection signal K for selecting the word driver column B
The output signals of 1, N2, ..., Nm are applied to each switch circuit 81. Other configurations are the same as those shown in FIG. 21, and the same reference numerals are given and the description thereof is omitted.

In the semiconductor circuit having such a configuration,
During standby, clock signal φ and column selection signal K1
, K2, ... Km is at H level, and pMOS FET
The potential V _pp1 is applied to the body (back gate) of Q61. As a result, the threshold voltage of the pMOS FET Q61 becomes high and almost no subthreshold current flows.

When active, the clock signal becomes L level, and the switch circuit 81 connected to the selected word driver WD (eg, word driver WD ₁₁ ).
The column selection signal K1 applied to the signal goes low. The other column selection signals K2, ... Km are at the H level. And p
The word line WL rises when the decoder signal X ₁ is input to the MOS FET Q61. FET Q61 of pMOS of word driver WD selected when active
Since the threshold voltage of is decreased, the word line WL rises at a high speed.

In the present embodiment, it is only necessary to raise the source potential of only the word driver row B including the selected word driver WD. Therefore, the rise time of the word line WL can be shortened as compared with the twelfth embodiment. .

Examples 10 to 14 may be applied to either the bulk structure or the SOI structure. However, in the case of a bulk structure, the potential to be controlled is the back gate bias potential, and the SOI
In the case of the structure, the body bias potential is used.

[0161]

According to the semiconductor circuit of the first aspect of the present invention, the absolute value of the threshold potential of the MOS-FET can be switched to make the switching characteristic and the subthreshold current characteristic of the MOS-FET variable. Therefore, it is possible to realize a semiconductor circuit composed of a MOS-FET capable of achieving both high-speed switching characteristics and small subthreshold current characteristics.

According to the semiconductor circuit of the second aspect of the present invention, the MOS-forming the logic circuit according to the operation mode of the logic circuit.
Since the absolute value of the threshold potential of the FET is switched, the MOS-
When the FET does not operate, the MOS-FET can have a small subthreshold current characteristic, and when the MOS-FET operates, the MOS-FET can have a high-speed switching characteristic.

According to the semiconductor circuit of the third and fourth inventions,
When the MOS-FET operates, the absolute value of the threshold potential is reduced, and when the MOS-FET does not operate, the absolute value of the threshold potential is increased, so that both high-speed switching characteristics and small subthreshold current characteristics are compatible. Possible MOS
It is possible to realize a semiconductor circuit composed of -FET.

According to the MOS-DRAMs of the sixth and seventh inventions, when the MOS-FET operates, the absolute value of the threshold potential is reduced, and when the MOS-FET does not operate,
Since the absolute value of the threshold potential is increased, it is possible to realize a MOS-DRAM composed of MOS-FETs that can achieve both high-speed switching characteristics and small subthreshold current characteristics.

According to the MOS-DRAMs of the eighth and ninth aspects of the invention, at the time of pause refresh of the memory cell, the absolute value of the threshold potential of the MOS-FET forming the memory cell is reduced to reduce the junction leak and the memory. At the time of disturb refresh of the cell, since the absolute value of the threshold potential of the MOS-FET forming the memory cell can be increased to reduce the subthreshold leak,
OS-DRAM composed of memory cells with little leakage
Can be realized. Along with this, it is possible to realize a MOS-DRAM composed of memory cells having long periods of pause refresh and disturb refresh.

According to the semiconductor circuit of the tenth invention, S
Since the absolute value of the threshold potential of the MOS-FET having the OI structure can be switched to make the switching characteristic and the subthreshold current characteristic of the MOS-FET variable, both the high-speed switching characteristic and the small subthreshold current characteristic are compatible. A semiconductor circuit composed of possible MOS-FETs can be realized.

According to the semiconductor circuit of the eleventh invention, an SOI forming a logic circuit according to the operation mode of the logic circuit.
Since the absolute value of the threshold potential of the MOS-FET of the structure is switched, when the MOS-FET does not operate, the MOS-F
ET is a small subthreshold current characteristic, and MOS-F
When the ET operates, the MOS-FET can have a high speed switching characteristic.

According to the semiconductor circuit of the twelfth and thirteenth inventions, the absolute value of the threshold potential is reduced when the MOS-FET having the SOI structure operates, and the absolute value of the threshold potential is reduced when the MOS-FET does not operate. Since the value is increased, it is possible to realize a semiconductor circuit composed of MOS-FETs that can achieve both high-speed switching characteristics and small subthreshold current characteristics.

According to the semiconductor circuit of the fifteenth to eighteenth inventions, a high speed switching characteristic and a small subthreshold current characteristic can be realized in a SOI-structure MOS-FET which is element-isolated by the LOCOS method and / or the FS method. You can

MOS-DRAM according to the nineteenth and twentieth inventions
According to the above, when the SOI-structure MOS-FET operates, the absolute value of the threshold potential is reduced, and when the MOS-FET does not operate, the absolute value of the threshold potential is increased.
A MOS-FET composed of a MOS-FET capable of achieving both high-speed switching characteristics and small subthreshold current characteristics.
A DRAM can be realized.

MOS-DRAMs according to the 21st and 22nd inventions
According to this, at the time of pause refresh of the memory cell, the absolute value of the threshold potential of the MOS-FET of the SOI structure forming the memory cell is reduced to reduce the junction leak, and at the time of disturb refresh of the memory cell, the memory cell is configured. Since it is possible to increase the absolute value of the threshold potential of the MOS-FET to reduce the subthreshold leakage, it is possible to realize an OS-DRAM including memory cells with less leakage. Along with this, a MOS composed of memory cells with long periods of pause refresh and disturb refresh, respectively.
-A DRAM can be realized.

According to the semiconductor circuit of the twenty-third invention, M
When OS-FETs form an inverter array, both high-speed switching characteristics and small subthreshold current characteristics can be achieved with half the power compared to the configuration that switches the back gate bias potential or body bias potential of all MOS-FETs. Is.

According to the semiconductor circuit of the twenty-fourth and twenty-fifth inventions, the inverter array is connected to the power source through the switching element, for example, the MOS-FET having a high threshold voltage, and the switching element (for example, the MOS-FET having a high threshold voltage is connected. )
Since it is grounded via, the current path between the power supply and ground can be cut off by turning off the switching element during standby. Reduction of the subthreshold current is realized.

According to the semiconductor circuit of the twenty-sixth aspect, among the MOS-FETs forming the inverter train, the threshold voltage of the MOS-FET turned on in the standby mode is not smaller than the threshold voltage of the MOS-FET turned on in the standby mode. Therefore, when the standby state is changed to the active state, the current in these MOS-FETs can be increased quickly, and the switching characteristics are improved.

MOS-DRA according to the 27th and 28th inventions
According to M, the subthreshold current can be reduced and the high-speed operation can be realized in the word driver, and if the back gate bias potential or the body bias potential is controlled in column units, the power required for switching can be reduced. The present invention has excellent effects such as the above.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a complementary MOS inverter showing an example of a logic circuit constituting a semiconductor circuit according to first to fourth aspects of the invention.

FIG. 2 is a circuit diagram showing an example of a switch circuit shown in FIG.

FIG. 3 is a circuit diagram showing an example of a switch circuit shown in FIG.

4 is a sectional structural view showing a well structure of the complementary MOS inverter shown in FIG.

FIG. 5 is a block diagram showing a configuration of an example of a MOS-DRAM according to fifth and sixth inventions.

FIG. 6 is a block diagram showing a configuration of an example of a MOS-DRAM according to fifth and sixth inventions.

7 is a timing chart showing a breakdown of a transmission time of an external RAS signal in each internal portion of the MOS-DRAM shown in FIGS. 5 and 6. FIG.

FIG. 8 is a timing chart showing a relationship between a control clock signal and an external RAS signal in the MOS-DRAM.

FIG. 9 is a block diagram showing the configuration of one embodiment of a memory cell constituting a MOS-DRAM according to the seventh and eighth inventions.

10 is a circuit diagram showing a configuration example of a switch circuit shown in FIG.

FIG. 11 is a sectional structural view showing another embodiment of the logic circuit constituting the semiconductor circuit according to the present invention.

12 is a diagram showing a layout of a main part of the semiconductor circuit shown in FIG.

FIG. 13 is a sectional structural view showing still another embodiment of the logic circuit constituting the semiconductor circuit according to the present invention.

FIG. 14 is a sectional structural view showing still another embodiment of the logic circuit constituting the semiconductor circuit according to the present invention.

FIG. 15 is a sectional structural view showing still another embodiment of the logic circuit constituting the semiconductor circuit according to the present invention.

FIG. 16 is a circuit diagram showing a semiconductor circuit according to a twenty-third invention.

FIG. 17 is a circuit diagram showing another embodiment of the semiconductor circuit according to the 23rd invention.

FIG. 18 is a circuit diagram showing a semiconductor circuit according to a twenty-sixth invention.

FIG. 19 is a circuit diagram showing a semiconductor circuit according to a twenty-fourth invention.

FIG. 20 is a circuit diagram showing a semiconductor circuit according to the twenty-third and twenty-fourth inventions.

FIG. 21 is a circuit diagram showing a semiconductor circuit according to the twenty-seventh invention.

FIG. 22 is a circuit diagram showing a semiconductor circuit according to a twenty-eighth invention.

FIG. 23 is a circuit diagram showing a complementary MOS inverter used in a conventional semiconductor circuit.

FIG. 24 is a sectional structural view schematically showing a structural example of a conventional memory cell used in a DRAM.

FIG. 25 shows MT when the logic circuit is an inverter train.
FIG. 9 is a circuit diagram showing a conventional CMOS circuit using a MOS.

FIG. 26 is a circuit diagram showing a conventional word driver.

FIG. 27 is a circuit diagram showing a conventional hierarchical word driver.

[Explanation of symbols]

1 Complementary MOS inverters 10, 11,
36, 43C, 43R, 45C, 45R, 81, 82
Switch circuit, 10a, 11a level shift circuit, 1
0b, 11b changeover switch, 13, 15, 44
C, 44R, 46C, 46R, 48a, 48b, 83,
84, 86, 87 voltage supply means, 14 clock signal generator, 57 memory cells, 42 MOS-DRAM,
85 clock signal generation circuit, 88 substrate bias switching circuit, φ, φ ₁ , φ ₂ control clock signal, V
_cc power supply potential (normal back gate bias potential), V
_ss ground potential (normal back gate bias potential), V
_pp , V _bb , V _bb1 , V _bb2 potentials from the voltage supply means,
ex. RAS external row selection signal, I ₁ , I ₂ , I ₃ , I
₄ , I ₅ , I ₆ , I ₇ , I ₈ , I ₁₁ , I ₁₂ , I ₁₃ inverter, WD word driver, B word driver array.

Continuation of the front page (51) Int.Cl. ⁶ Identification number Reference number within the agency FI Technical indication location H03K 17/04 E 9184-5K 17/30 K 9184-5K 17/687 19/094 9184-5K H03K 17/687 F 19/094 D

Claims (28)

[Claims] 1. In a semiconductor circuit having a MOS-FET, a MOS-FET to which a first potential or a second potential is to be given as a back gate bias potential, and a back gate for the first potential or the second potential. A semiconductor circuit comprising: switching means for selectively applying a bias potential to the MOS-FET. 2. In a semiconductor circuit having a MOS-FET, a MOS-FET to which the first potential or the second potential should be given as a back gate bias potential, and the MO-FET.
According to the operation mode of the S-FET, the first potential or the second potential is used as the back gate bias potential, and the MOS-F
A semiconductor circuit, comprising: a switching means for selectively applying to ET. 3. In a semiconductor circuit having a MOS-FET, a MOS-FET to which the first potential or the second potential should be given as a back gate bias potential, and the MO-FET.
Clock signal generating means for generating a control clock signal for activating the S-FET, and switching for selectively applying the first potential or the second potential as a back gate bias potential to the MOS-FET according to the control clock signal. And a semiconductor circuit. 4. The switching means, according to an output signal from the level shift circuit for outputting a signal for converting into the first potential or the second potential, the output signal from the level shift circuit,
4. The semiconductor circuit according to claim 1, further comprising: a switch circuit that selectively applies the first potential or the second potential as a back gate bias potential to the MOS-FET. 5. The semiconductor circuit according to claim 1, further comprising a logic circuit composed of a MOS-FET. 6. A logic circuit which is composed of a MOS-FET to which the first potential or the second potential is to be given as a back gate bias potential and which is used in a row-related operation circuit and a column-related operation circuit, and According to the operation mode of the logic circuit,
A MOS-DRAM comprising: switching means for selectively applying a first potential or a second potential as a back gate bias potential to the MOS-FET. 7. A logic circuit which is composed of a MOS-FET to which the first potential or the second potential is to be given as a back gate bias potential, and which is used for a row operation circuit and a column operation circuit, and Clock signal generating means for generating a control clock signal for activating the logic circuit,
According to the control clock signal, the first potential or the second potential is used as the back gate bias potential and the MO
A MOS-DRAM comprising a switching means for selectively applying to the S-FET. 8. A memory cell composed of a MOS-FET to which the first potential or the second potential is applied as a back gate bias potential, and the first potential or the second potential according to the operation mode of the memory cell. And a switching means for selectively applying a potential as a back gate bias potential to the MOS-FET.
DRAM. 9. A first potential or a first potential according to a signal for activating the memory cell, which is constituted by a MOS-FET to which the first potential or the second potential is to be given as a back gate bias potential. 2. A MOS-DRAM comprising: switching means for selectively applying the potential of 2 as a back gate bias potential to the MOS-FET. 10. A semiconductor circuit having a MOS-FET having an SOI structure, wherein the first potential or the second potential should be applied as a body bias potential.
And a switching means for selectively applying the first potential or the second potential as a body bias potential to the MOS-FET. 11. A semiconductor circuit having a MOS-FET having an SOI structure, wherein the first potential or the second potential is to be applied as a body bias potential.
According to the operation mode of the MOS-FET, the first potential or the second potential is used as a body bias potential and the MOS
-A semiconductor circuit comprising switching means for selectively applying to the FET. 12. A semiconductor circuit having a MOS-FET having an SOI structure, wherein the first potential or the second potential is to be applied as a body bias potential.
And a clock signal generating means for generating a control clock signal for activating the MOS-FET, and, according to the control clock signal, selectively using the first potential or the second potential as a body bias potential to the MOS-FET. A semiconductor circuit comprising: switching means for applying the semiconductor circuit. 13. The switching means outputs a signal for converting into a first potential or a second potential, and a first potential or a second potential according to an output signal from the level shift circuit. 11. A switch circuit for selectively applying a potential as a body bias potential to the MOS-FET.
2. The semiconductor circuit according to 2. 14. A logic circuit formed by a MOS-FET having an SOI structure.
The semiconductor circuit according to 0, 11, or 12. 15. A semiconductor device having a plurality of SOI-structured MOS-FETs, wherein the MOS-FETs are isolated by an isolation oxide film.
12. The semiconductor circuit according to 12 or 13. 16. A plurality of MOS-FETs having an SOI structure are provided, and elements between these MOS-FETs are isolated by an FS isolation layer formed by partially channeling off a channel layer. The FS separation layer is connected to a switching means.
2. The semiconductor circuit according to 2, or 13. 17. An FS having a plurality of SOI-structured MOS-FETs, wherein an isolation oxide film and a channel layer are partially channeled off between the MOS-FETs.
The element is separated by a separation layer, and the FS separation layer is connected to a switching means.
The semiconductor circuit according to 0, 11, 12, or 13. 18. One conductivity type MOS-FET having an SOI structure
A plurality of MOS transistors, each of which is separated by a FS separation layer formed by partially channeling off the channel layer between the one conductivity type MOS-FET.
The FS separation layers on both sides of the OS-FET are connected to the switching means, the FS separation layers on both sides of the other one conductivity type MOS-FET are connected to a predetermined potential, and the separation layers between the FS separation layers are other. 14. The semiconductor circuit according to claim 10, 11, 12, or 13, characterized in that the predetermined potential is applied. 19. A MOS-structure having an SOI structure in which the first potential or the second potential is to be applied as a body bias potential.
A logic circuit which is composed of an FET and is used for a row-related operation circuit and a column-related operation circuit, and the MOS-FET with the first potential or the second potential as a body bias potential according to the operation mode of the logic circuit. And a switching means for selectively applying to the MOS-DRA
M. 20. A MOS-structure having an SOI structure in which the first potential or the second potential is to be applied as a body bias potential.
A logic circuit which is composed of FETs and is used in a row-related operation circuit and a column-related operation circuit, a clock signal generating means for generating a control clock signal for activating the logic circuit, and a first control circuit according to the control clock signal. The first potential or the second potential as the body bias potential
A MOS-DRAM comprising a switching means for selectively applying to the OS-FET. 21. A MOS-structure having an SOI structure, to which the first potential or the second potential is to be applied as a body bias potential.
Memory cell composed of FET and MOS-DRA
According to the operation mode of M, there is provided switching means for selectively applying the first potential or the second potential as a body bias potential to the MOS-FET.
OS-DRAM. 22. An SOI-structure MOS-to which the first potential or the second potential is to be applied as a body bias potential.
Memory cell composed of FET and MOS-DRA
A MOS-DRAM comprising: switching means for selectively applying a first potential or a second potential as a body bias potential to the MOS-FET according to a signal for activating M. 23. A logic circuit is a one conductivity type MOS-FET.
And a back-gate of the MOS-FET which is turned off during standby is connected to the switching means. 5
Alternatively, the semiconductor circuit according to item 14. 24. A logic circuit is a one conductivity type MOS-FET.
And an inverter row composed of other conductivity type MOS-FETs are connected in series, and the inverter row is grounded via a switching element and a sub power line connected to a power source via a switching element. 15. The semiconductor circuit according to claim 5, wherein the semiconductor circuit is arranged between the sub-ground line and the sub-ground line. 25. A switching element is a MOS- whose threshold voltage is higher than that of a MOS-FET forming the logic circuit.
25. The semiconductor circuit according to claim 24, which is a FET and is turned on when active. 26. A MOS-FE forming an inverter train.
26. The threshold voltage of a MOS-FET that is turned on when active in T is smaller than the threshold voltage of a MOS-FET that is turned off when active.
The semiconductor circuit according to any one of 1. 27. The MOS-DRAM according to claim 6, 7, 19, or 20, wherein the operation circuit is a word driver. 28. MOS-F constituting a word driver
28. The MOS-DRAM according to claim 27, wherein the ET is connected to the switching means in column units.