JPH0817191A - Memory management area control method - Google Patents

Abstract

(57) [Abstract] [Purpose] Even if a power failure occurs during the erase operation of the flash memory INDEX area, the last written data address can be surely preserved, and the last data address can be saved when the power is turned on. Provided is a memory management area control method capable of accurately acquiring a data address written in a memory and obtaining a next writable address. [Structure] The divided end INDEX area search means 11 detects a divided INDEX area with an end code,
The last flag after that area is detected by the last flag search means 12, and the data address written immediately before the detected flag is detected in the data area 4 of the flash memory 40.
A memory which is obtained as the address finally written in 2 and writes a data address in the divided INDEX area, and when the area becomes full, an end code is added to the area and the previous area is erased by the erase means 33. This is a management control method.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory management area control method for preserving a data address at the end of a flash memory, and particularly at the end of a flash memory even when a failure such as a power stop occurs while erasing the memory management area. The present invention relates to a memory management area control method capable of reliably preserving the data address of the memory.

[0002]

2. Description of the Related Art Conventionally, a flash memory has been known as a rewritable memory, and a data address at which data at the end of the flash memory is written is managed in a memory management area. A memory management area control method in the flash memory will be described with reference to FIG. FIG. 5 is a schematic explanatory view for explaining a memory management area (INDEX area) control method of a conventional flash memory.

As shown in FIG. 5, the conventional flash memory is divided into a plurality of blocks, in which, for example, block 1 is assigned to the INDEX area and blocks 2 to N are assigned to the data area. It was being done.

Here, the INDEX area of the block 1 is an area for storing an address (data address) where the data is written in the data areas of the blocks 2 to N, and in particular, the data is written at the time of the previous end. The data address is referred to when the power is turned on, and the next accessible (data can be written) data address is acquired. Also, block 2
The data area of the block N is an area where data is read and written.

Next, a conventional INDEX area control method will be described with reference to FIG. FIG. 6 shows a conventional IND.
It is a flowchart figure which shows the control method of an EX area.
As shown in FIG. 6, when the control process is started, the accessed data address in the INDEX area of the block 1 is searched and the next accessible data address is acquired (101). Then, the access process in the data area in block 2 to block N is executed (1
02), an attempt is made to write the last data address in which data has been written to the INDEX area (103).

In process 103, it is judged whether the data address can be written when the INDEX area is full (104), and if not, the data address is written in the INDEX area (105), process 1
Returning to 02, if it is full, erase processing of the INDEX area is performed (106). Then, it is judged whether or not the erase is completed (107), and if the erase is not completed, the process returns to step 106, and if the erase is completed, the data address is written at the head of the erased INDEX area (108), Return to processing 102.

Here, the erase process means that when data addresses are sequentially written in the INDEX area,
This is a process in which when the X area is full, the last data address in which data has been written is left in the data area and other data addresses are erased.

Specifically, when the data address of the last accessed (written) data is written in the INDEX area, it is determined whether the INDEX area is full,
If it is full, the process of first erasing (erasing) the INDEX area and then writing the data address at the beginning of the erased INDEX area is performed.

Further, in the conventional flash memory, at the time of normal power-on, in searching the last accessed data address from the INDEX area, a portion where the data address is not yet written is searched and written immediately before that. It reads the data address that has been written and obtains the address to be written next.

Specifically, since the location where the data address is not yet written is all 1, the first 2 bytes of the data address 4 bytes (32 bits) are set.
The e (16 bits) searches the all 1 (FFH) in the INDEX area, reads the data address immediately before the found FFH, and acquires the address that can be accessed (written) next.

[0011]

However, in the above-mentioned conventional INDEX area (management area) control method in the flash memory, when data such as power interruption occurs during the erase operation of the INDEX area, data in the INDEX area is lost. All addresses are erased or become unstable, and the data address is lost when the power is turned on after that, so it is not possible to access the FLA memory, and even if it is possible, the data can be read. However, there is a problem that the reliability of the flash memory is deteriorated due to the malfunction.

Further, in the above-mentioned conventional INDEX area control method, at the time of normal power-on, the F in the INDEX area is
Since it is designed to search for FH, if there is an address including FFH as a data address,
There is a problem that the FFH is mistaken for a portion that has not been written yet, the address at which writing can be performed next cannot be normally acquired, and the reliability of the flash memory is also lowered.

The present invention has been made in view of the above circumstances, and is an INDEX area (management area) of a flash memory.
Even if a power failure occurs during the erase operation of the device, the last written data address can be surely preserved, and the last written data address can be acquired accurately at the power-on and the next writing can be performed. It is an object of the present invention to provide a memory management area control method capable of obtaining an available address.

[0014]

The invention according to claim 1 for solving the problems of the conventional example is a method of controlling a memory management area divided into a plurality of blocks, wherein the memory management area is terminated. At the time of writing the data address at the time, an attempt is made to add a specific flag immediately after the data address, and if there is room to add the specific flag in the written block, the specific flag is added and If there is no room to add the specific flag to, the data address is written at the beginning of the next block, the specific flag is added immediately after the data address, and at the end of the block where the data address is first written. A special feature is that an end code is added to erase the block immediately before the block in which the data address is first written. It is set to.

A second aspect of the present invention for solving the above-mentioned problems of the conventional example is a method for controlling a memory management area to which a specific flag is added by the memory management area control method according to the first aspect. Search for the end code at startup, and further search for the specific flag from the end code,
The data address to be accessed next is obtained from the data address written immediately before the specific flag.

[0016]

According to the invention described in claim 1, the memory management area is divided into a plurality of blocks, and after the end data address is written in the memory management area, a specific flag is added immediately after the data address. However, if there is no room to write the specific flag to the block where the data address was written, write the data address at the beginning of the next block to add the specific flag, and the end of the block where the data address was written first. Because the memory management area control method is to erase the block immediately before the block in which the data address was first written, an error such as power stop occurs when erasing the block in the memory management area. However, the data address at the end can be preserved.

According to the second aspect of the present invention, regarding the memory having the memory management area processed by the memory management area control method according to the first aspect, when the power is turned on, first the end code is searched, and the end code is further searched. The memory management area control method is to retrieve the specific flag from the specified address and obtain the data address to be accessed next from the data address written immediately before the specific flag. The data address can be easily obtained.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a schematic explanatory diagram for explaining a memory management area (INDEX area) control method of a flash memory according to an embodiment of the present invention. As shown in FIG. 1, the flash memory of this embodiment is divided into a plurality of blocks as in the conventional case. Then, as a characteristic part of this embodiment, the INDEX area is divided into a plurality of areas, and the divided INDEX areas (hereinafter, the divided INDEX areas are divided.
An X area) is provided at the beginning of each block (block 1 to block N).

Here, the INDEX area is an address (data address) at the time when data writing is completed in the data area in the flash memory, as in the conventional case.
Is an area for storing data, and in particular, it refers to the data address at the end of the previous data writing at power-on and acquires the next accessible (data can be written) data address. . The divided INDEX areas provided at the beginning of each block will be referred to as INDEX area 1 to INDEX area N. Also,
The INDEX area is initialized to all "1" in the initial state.

Then, in the control method of the INDEX area of the present embodiment, the control method after the data writing process to the data area is to store the data address at the end of the data writing in the INDEX area, and then to the control method of the present embodiment. The last flag, which is a characteristic part, is added immediately after the data address. Then, when the writing of the data to the data area is finished next, the next data address is overwritten at the position where the last flag is written in the INDEX area last time,
Then, the last flag is added.

Here, the tail flag is a flag indicating the tail of data addresses sequentially written in the INDEX area, except for all bits "1" having a predetermined arbitrary length of 1 to 8 bits. It is an arbitrary bit string. The reason for excluding all bits “1” is to prevent that the initial state and erase completion state of the INDEX area are all bits “1” and the last flag cannot be detected in the subsequent processing.

Then, the above process is repeated to obtain a certain IND.
When the EX area (i) becomes full, the INDEX area (i + 1) of the next block is a characteristic process of this embodiment.
Move the write position to and write the data address and the last flag, then write the end code at the end of the INDEX area (i) and the INDEX of the previous block.
Area (i-1) is erased.

Here, the end code is a code indicating that the data address has been written in the INDEX area to be full, and the writing has ended, and all bits "1" having a predetermined length of 1 byte are set. Except for any bit string. The reason for excluding all bits "1" is INDE
All bits in the initial state and erased state of the X area "
This is to prevent the end code from becoming undetectable in the subsequent processing.

Further, at the time of normal power-on, in order to start writing the present data from the address position where the data was last written in the previous data area, first, the data address where the last data was written in the data area was started. Is searched from the divided INDEX area, the next data write address is specified, the data write processing to the data area is performed, and subsequently, as a control method after the data write processing to the data area is finished, The data address is written in the INDEX area, and then the last flag is added.

Here, in the search of the data address in which the last data is written, specifically, the divided INDEX area in which the end code is stored is searched, and the tail flag is sequentially set from the searched divided INDEX area. When a search is performed and the data address stored immediately before the last flag is read, this is the data address at which the last data was written in the data area.

On the other hand, when the power of the apparatus is turned off illegally during the erase processing of the INDEX area and the power is restarted from a state where the erase processing is not normally completed, the above normal power restart is performed. There is a possibility that the last flag cannot be searched during processing. In that case, it is determined that the memory is in an undefined state, and erase is performed on all the divided INDEX areas for which erase processing has not been completed, and the entire memory is erased. After the initial state, the writing of data to the data area and the writing of the data address to the INDEX area are performed.

Next, means for realizing the memory management method of this embodiment will be described with reference to FIG. FIG. 2 is a functional configuration block diagram of means for implementing the memory management method of this embodiment. As shown in FIG. 2, the means for realizing the memory management method of this embodiment is, as shown in FIG. 2, a final data address search means 10 for searching the last data address in the data area and a data area writing means for writing data in the data area. 20 and a data address writing control means 3 for controlling writing of the last written data address in the data area to the INDEX area.
0, a flash memory 40, a data address area 51 for storing a data write address in the data area, and an IN for storing a data address write address (INDEX address) in the INDEX area.
It is composed of a DEX address area 52.

The final data address search means 1
The inside of 0 is an end divided INDEX area search means 11 for searching a divided INDEX area for which writing has been completed.
A last flag search means 12 for searching the last flag, an erase means 13 for erasing the divided INDEX area, and an end divided INDEX area number stock area 14 for stocking the number of the divided INDEX area for which writing has been completed. Has been done.

Further, the data address write control means 3
In the inside of 0, the data address writing means 31 for actually writing a data address in the INDEX area and a certain divided INDEX area becomes full, and the next divided INDEX is formed.
Divided INDEX area switching means 3 for switching to the X area
2 and an erasing means 33 for erasing an unnecessary divided INDEX area immediately before.

Next, the configuration of each part will be specifically described. The flash memory 40 is divided into a plurality of blocks (block 1 to block N), and each block stores a data area 42 and an INDEX area for storing an address (data address) in which data in the data area 42 is written. It is divided into 41.

The data address area 51 is an area for storing an address to write data in the data area 42 of the flash memory 40. Also, INDEX
The address area 52 is the IND of the flash memory 40.
This is an area for storing an address (INDEX address) for writing a data address in the EX area 41.

The end divided INDEX area number stock area 14 is an area for stocking the numbers of the divided INDEX areas for which writing has been completed. Specifically, the end divided INDEX area search means 11 puts an end code at the end of the divided INDEX area. The divided INDEX area number to be held is searched and stored.

End division INDEX area search means 11
Is a means for searching the divided INDEX area in which the data address has been written and is full and the writing has been completed, and further determines whether the flash memory 40 is in the initial state.

Specifically, first, the divided INDEX area 1
From the last divided INDEX area to the divided IND
It is checked whether the end code is held at the end of the EX area, and the number of the divided INDEX area holding the end code is set to the end divided INDEX area number stock area 1
It will be stocked in 4. Here, the end divided INDEX area search means 11 is provided with a counter for searching a divided INDEX area for which writing has been completed (holding an end code), and uses a variable i as described later in FIG. is there.

Then, the next judgment as to whether the flash memory 40 is in the initial state is made. If no number is stored in the end divided INDEX area number stock area 14,
When the first address data of the first divided INDEX area is in the initial state, that is, all "1", it is determined that the flash memory 40 is in the initial state, and the process of the next data area writing means 20 is performed. It is like this.

The tail flag search means 12 is means for searching the tail flag, and specifically, a divided INDEX area for holding an end code, that is, an end divided IND.
EX area number stock area The number of stocks stored in the area 14 is searched sequentially from the divided INDEX area, and if the tail flag is detected, the data address stored immediately before the tail flag is read to read the data address. It is stored in the area 51.

Here, the last flag search means 12 is
In order from the divided INDEX area that holds the end code,
A counter is provided for searching the tail flag, and the variable j is used as described later with reference to FIG.

The search for the last flag means division I
Data address 4 bytes in order from the beginning of the NDEX area
This is a process for determining whether the first 1 to 8 bits of e (32 bits) match the predetermined bit string of the last flag. By sequentially setting the access address in the INDEX area 41 to the INDEX address area 52 and searching the tail flag, the value of the INDEX address area 52 at the time of detecting the tail flag is changed to the next address data writing in the INDEX area 41. It becomes an address.

On the other hand, a divided INDE holding an end code
The tail flag is searched in order from the X area, and when the tail flag is not detected in any of the divided INDEX areas, the erase means 13 determines the number of stocks stored in the end divided INDEX area number stock area 14. Erase the divided INDEX area. In other words, the fact that the tail flag could not be detected despite the existence of the divided INDEX area holding the end code means that the flash memory 4 has some trouble.
Since 0 is considered to be in an indefinite state, the divided INDEX area holding the end code is erased to initialize the entire flash memory, and then the processing of the next data area writing means 20 is started.

When the flash memory 40 is determined to be in an indeterminate state by the tail flag search means 12, the erase means 13 ends the division IN of the number divided in the INDEX area number stock area 14.
This is a means for performing erase processing on the DEX area.
Here, the erase process is the target divided INDEX.
This is a process of storing "1" in all bits in the area and setting it to the initial state.

The data area writing means 20
Is a means for writing data in the data area. Specifically, for example, 4 (byte) is added to the value of the data address area 51 as a memory access unit, and data is added from the address of the added value in the data area 42. I am trying to write.

Further, the data address writing means 31
When the data writing to the data area 42 is completed, the INDEX area 41 uses the address last written in the data address area 51 as a data address.
In the INDEX area 41.
Is a means to write. Specifically, the data address is read from the data address area 51 and the value is IN
When writing from the address position stored in the DEX address area 52 and then trying to write the last flag, and the last INDEX area being written is full and the last flag cannot be written, the divided INDEX area switching means 32 is activated. It is supposed to do.

If a data address is written in the INDEX area 41 by the data address writing means 31, 4 (byte) is added to the value of the INDEX address area 52 as a memory access unit,
The INDEX address area 52 indicates the address where the address data is written next.

The divided INDEX area switching means 3
2 is activated in the data address writing means 31 when the divided INDEX area being written is full and the last flag cannot be written, and the next divided INDEX is started.
Specifically, the value of the INDEX address area 52 is switched to the address of the next divided INDEX area, the data address is read from the data address area 51, and the value is stored in the INDEX address area 52. Write from address location,
Subsequently, the last flag is written, and the end code is written at the end of the full divided INDEX area.

The erase means 33 is means for performing erase processing on the divided INDEX area immediately before the divided INDEX area which is found to be full by the data address writing means 31.

Next, a method of controlling the INDEX area of this embodiment will be described with reference to FIGS. FIG. 3 is a flow chart showing the first half of the INDEX area control method of this embodiment, and FIG. 4 is the INDEX of this embodiment.
It is a flowchart figure which shows the latter half part of the control method of X area, (A) of FIG. 3 and (A) of FIG. 4 continue. In FIG. 3, the variable i is a variable indicating the divided INDEX number for searching the end code, and the variable j
Is a variable indicating the divided INDEX number for searching the tail flag.

As shown in FIG. 3, when the control processing is started, 0 is substituted into the variable i as the operation of the end division INDEX area search means 11 (200), and then the variable i.
Is incremented by 1 (202), it is determined whether the value of the variable i is larger than N, that is, whether the search has been performed up to the last divided INDEX area (204). If the value of i is not larger than N, the i-th It is determined whether the end of the divided INDEX area is the end code (206). If the end code is not the end code, the process returns to step 202 to search for the next divided INDEX area.

On the other hand, in process 206, the i-th division I
If the end of the NDEX area is the end code, split IN
Stock the DEX area number in the end division INDEX area number stock area 14 (208), and process 202
Then, the search for the end code in the next divided INDEX area is performed. Here, the division INDEX of the process 208
Area number stock is the end division IN of the value of variable i
It is to be stored in the DEX number stock area 14.

If the value of i is larger than N in the process 204, the search for the end code in all the divided INDEX areas is completed, so that the process jumps to the process 210 to judge whether the flash memory 40 is in the initial state ( 21
0), in the case of the initial state, jump to (A) and move to the processing of FIG. Here, it is determined whether the flash memory 40 is in the initial state by the end division INDEX area search means 11
The decision is made in step 1. Specifically, the end division IND
If no number is stored in the EX area number stock area 14 and the first address data of the first divided INDEX area is in the initial state, that is, all "1", the flash memory 40 determines the initial state. It is a thing.

In process 210, the flash memory 4
If 0 is not in the initial state, it is judged whether or not a number is stored in the end divided INDEX area number stock area 14 (212), and if the number is not stored, the tail flag is set in the first divided INDEX area. Search (21
4), it is determined whether there is a tail flag (216), and if there is no tail flag, it is determined that the flash memory is in an indeterminate state, the first divided INDEX area is erased (218), and (A) is set. The process jumps to the process shown in FIG.

On the other hand, in the processing 216, if there is a tail flag, the data address immediately before the tail flag is stored in the data address area 51 (228).
It jumps to (A) and moves to the process of FIG.

Further, in the process 212, the end division IN
When the number is stored in the DEX area number stock area 14, the first number stored in the end divided INDEX area number stock area 14 is substituted into the variable j (22
0), the tail flag is searched in the jth divided INDEX area (222), and it is judged whether there is the tail flag (2).
24) If there is a tail flag, the process jumps to processing 228.

On the other hand, if there is no tail flag in the process 224, it is judged whether or not the tail flag search for all the divided INDEX areas is completed (230).
If the search for the tail flag has not been completed, the variable j is set to the next divided INDEX area number (232), and the process 222 is returned to. Here, the process of setting the variable j of the process 232 to the next divided INDEX area number is 1 for the variable j.
Is added and, as a result, the value of the variable j becomes larger than the maximum value N of the divided INDEX area numbers, 1 is set. In addition, all the divisions I in process 230
The determination as to whether the end flag search for the NDEX area has ended is made when the value of the variable j reaches a value obtained by dividing 1 from the divided INDEX area number that started the end flag search. ing.

Further, in processing 230, all division IN
If you have finished searching the last flag in the DEX area,
It is assumed that the flash memory 40 is in an indefinite state, and the divided INDEX area having the number stored in the end divided INDEX area number stock area 14 is erased (23
4), jump to (A) and move to the process of FIG.

Next, as shown in FIG. 4, (A) of FIG.
Then, as the operation of the data area writing means 20, the data writing processing to the data area 42 is performed (240), and then the data address writing means 31 writes the data address to the INDEX area 41 (250). ), And then it tries to write the last flag to the INDEX area 41 (252), and judges whether the last INDEX area could not be written because the divided INDEX area to be written was full (254). Return.

On the other hand, in process 254, if the divided INDEX area to be written is full, the divided I
As the operation of the NDEX area switching means 32, INDEX
The start address of the next divided INDEX area is set in the address area 52, and the data address is set to the next divided IND.
EX area writing (260), followed by writing the last flag (262), full divided INDEX
An end code is written at the end of the area (264), and as the operation of the erase means 33, the full division IN
The divided INDEX area immediately before the DEX area is erased (270) and the process 240 is returned to.

In the memory management area control method of this embodiment, the tail flag is searched in order from the divided INDEX area holding the end code, but the divided INDEX area holding the end code is searched. It is also conceivable to start the search of the tail flag from the next divided INDEX area of. In this case, the next division IN of the division INDEX area holding the end code
Since the probability that the tail flag exists in the DEX area is high, the tail flag can be searched efficiently.

According to the INDEX area control method of this embodiment, the INDEX area 41 is divided into a plurality of divided INDEX areas, and after writing the data address at the end of data writing in the data area 42 to the INDEX area 41, The process of adding the tail flag is performed, but if there is no room to write the tail flag in the divided INDEX area in which the data address has been written, the data address is written at the beginning of the next divided INDEX area, the tail flag is added, and Since the end code is added to the end of the divided INDEX area in which the data address is written first, and the divided INDEX area immediately before the divided INDEX area in which the data address is written first is erased, the divided INDEX area 41 is divided.
Even if a failure such as a power supply stop occurs at the time of erasing the X area, the data address at the end can be preserved.

Further, according to the INDEX area control method of the present embodiment, when the power is turned on, first, the end code is searched, the divided INDEX areas holding the end code are specified, and the specified divided INDEX areas are sequentially searched. Since the tail end flag is searched and the data address to be accessed next in the data area 42 is acquired from the data address written immediately before the tail end flag, the data address that was preserved at power-on The data address to be accessed can be easily obtained.

[0060]

According to the invention of claim 1, the memory management area is divided into a plurality of blocks, and after writing the data address at the end to the memory management area,
The specific flag is added immediately after the data address, but if there is no room to write the specific flag in the block in which the data address was written, write the data address at the beginning of the next block to add the specific flag, and An end code is added to the end of the block in which the address is written first, and the memory management area control method that erases the block immediately before the block in which the data address is first written is used. Even if a failure such as a power stop occurs during erase, the data address at the end can be preserved.

According to the second aspect of the present invention, regarding the memory having the memory management area processed by the memory management area control method according to the first aspect, when the power is turned on, the end code is searched first, and the end code is further searched. The memory management area control method is to retrieve the specific flag from the specified address and obtain the data address to be accessed next from the data address written immediately before the specific flag. The data address can be easily obtained.

[Brief description of drawings]

FIG. 1 is a schematic explanatory diagram for explaining a memory management area (INDEX area) control method of a flash memory according to an embodiment of the present invention.

FIG. 2 is a functional configuration block diagram of means for implementing the memory management method of the present embodiment.

FIG. 3 is a flow chart showing the first half of the control method of the INDEX area of the present embodiment.

FIG. 4 is a flowchart showing the latter half of the method of controlling the INDEX area according to the present embodiment.

FIG. 5 is a memory management area (I
FIG. 6 is a schematic explanatory diagram for explaining an NDEX area) control method.

FIG. 6 is a flowchart showing a conventional method of controlling an INDEX area.

[Explanation of symbols]

10 ... Final data address search means, 11 ... End division INDEX area search means, 12 ... End flag search means, 13 ... Erase means, 14 ... End division INDEX area number stock area, 20 ... Data area writing means, 30 ... Data Address writing control means, 31 ... Data address writing means, 3
2 ... Divided INDEX area switching means, 33 ... Erase means, 40 ... FLASH memory, 41 ... INDEX area, 42 ... Data area, 51 ... Data address area, 52 ... INDEX address area

Claims (2)

[Claims] 1. A method of controlling a memory management area divided into a plurality of blocks, wherein an attempt is made to add a specific flag immediately after the data address when the end data address is written in the memory management area. If there is room to add the specific flag in the written block, the specific flag is added, and if there is no room to add the specific flag in the block, the data address is written at the beginning of the next block, Further, the specific flag is added immediately after the data address, an end code is added at the end of the block in which the data address is first written, and the block immediately before the block in which the data address is first written is added. A memory management area control method characterized by erasing. 2. A method of controlling a memory management area to which a specific flag is added by the method of controlling a memory management area according to claim 1, wherein an end code is searched at power-on,
Furthermore, the memory management area control method is characterized in that the specific flag is searched from the end code, and the data address to be accessed next is acquired from the data address written immediately before the specific flag.