JPH08180010A - Circuit and method for input/output control of data for computer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To apply plural input/output devices to a computer without limitation by adding plural input/output pots to one data input/output control circuit and incorporating the data input/output control circuit in one to plural computers. SOLUTION: A decoder 51 decodes board ID values inputted from the address terminals SA0-SA11 of an extension slot 40, the signals are inputted to a latch circuit 54 as enable signals and the board ID values inputted from data terminals SD0-SD7 are latched. When the latched board ID value matches with the board ID value set in a board ID value setting part 55, the board ID value is outputted to a CPU. Thereafter, since a pot ID value is inputted from the CPU, the decoder 61 decodes the pot ID value, input/output pot circuits 621 -62N are selected and a transmission route is formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer data input / output (I / O) control circuit and an input / output control method. More specifically, one data input / output control circuit includes a plurality of input / output pots. The present invention relates to a data input / output control circuit and an input / output control method for a computer in which a single or a plurality of the data input / output control circuits can be additionally installed.

[0002]

2. Description of the Related Art Recently, application devices of the post computer PC have been increased in accordance with widespread use of the post computer PC, and a data input / output board as a data input / output control circuit for interfacing the post computer PC and the application devices. Has been developed in various ways.

In a conventional data input / output board as a data input / output control circuit for a computer, as shown in FIG. 4, a pot for inputting data from an expansion slot 10 connected to the side of the data input / output board 20. A decoder 21 for decoding an address, a buffer 22 for buffering transmission data which is enabled by an output signal of the decoder 21, and a transmission data from the buffer 22 for the data input / output board 2
An input / output (I / O) pot 23 for outputting to each input / output device 30 on the side of 0 or outputting input data from the output device 30 to the buffer 22 was provided.

In the operation of the conventional data input / output board for a computer thus constructed, the address of the input / output pot 23 for accessing the data input / output board 20 is output from the CPU of the computer to the expansion slot 10. , The address of the input / output pot 23 from the expansion slot 10 is the address terminal (SA0-S0).
A11) to be output to the decoder 21, where the addresses are decoded by the decoder 21 and output as the chip selection signal CS.
And the input / output pot 23 are enabled respectively. Next, the data terminals SD1 to SD1 of the expansion slot 10
Data is output from SD7, the data is transmitted to the input / output device 30 through the buffer 22 and the input / output pot 23, and the data from the input / output device is output to the expansion slot 10 conversely. Computer C
Input to PU.

[0005]

However, in the data input / output board as the conventional data input / output circuit for a computer having such a structure, only a buffer and an input / output pot are provided and mapped to the main memory of the computer. Moreover, since the area of the input / output address cannot be covered, there is a disadvantage that it is impossible to connect a large number of input / output devices and expand the utilization of the computer.

The present invention has been made in view of the above conventional problems, and a computer data input / output control circuit and an input / output control for connecting a large number of input / output devices to expand the utilization of the computer. The purpose is to provide a method.

[0007]

Therefore, in the circuit according to the invention of claim 1, between the expansion slot connected to the CPU of the computer and the plurality of input / output devices for applying the data of the computer. An input / output control circuit for one or a plurality of computer data connected to the CPU, which stores and retains a board ID value for designating a board from the CPU through an expansion slot. Then, the stored board ID value is compared with a preset board ID value, and when the stored board ID value and the set board ID value match, a board ID value comparison means for outputting a match signal, When the coincidence signal is output from the board ID value comparison means, the board ID value stored and held is expanded to make the CPU confirm that the corresponding circuit exists. Board ID value output means for outputting to the CPU through a slot, and a pot ID value for input / output device selection input from the CPU through the expansion slot after it is confirmed by the CPU that the corresponding circuit exists. Utilizing the input / output pot selection means for selecting a corresponding pot from a plurality of input / output pots for inputting / outputting data to / from each input / output device, and the corresponding pot is selected by the input / output pot selecting means. And a transmission path forming means for forming a data transmission path between the expansion slot and the corresponding input / output device when selected.

According to this structure, when a plurality of data input / output control circuits having a plurality of input / output pots are built in the main body board of the computer, the board ID values obtained by the board ID comparison means and the board ID output means are changed. Based on the selected data input / output control circuit, the corresponding data input / output control circuit is selected, the corresponding input / output pot is selected from the selected circuits based on the pot ID value for input / output pot selection, and then, A data transmission path is formed between the selected input / output pot and the expansion slot to transmit data. As described above, since the transmission path is formed between the expansion slot and the plurality of input / output devices that apply the data of the computer based on the board ID value and the pot ID value, the CPU of the computer It becomes possible to connect a large number of input / output devices, and the use of computers can be expanded.

In the circuit according to the invention of claim 2, the board ID value comparing means preliminarily sets the board ID value of the circuit, and the board input from the address terminal of the expansion slot. A first decoder for decoding an ID value and a first AND for calculating a logical product of a decoding signal of a board ID value output from the first decoder and a write signal input from an expansion slot A gate and the first AN
It is set by the first latch means for storing and holding the board ID value output from the data terminal of the expansion slot and the board ID value setting means, which is enabled by the output signal of the D gate in the high state and becomes the memory holding state. The set board ID value and the board ID value stored and held by the first latch means are compared, and as a result of the comparison,
And a comparator for outputting a coincidence signal to the board ID value output means and the input / output pot selection means when the set board ID value and the stored and held board ID value match.

According to such a configuration, the input board I
The D value is decoded, and the first latch means is enabled by the decoding signal to enable storage and storage, and the storage and storage is performed in the first latch means. The stored board ID value is the set board I
It is compared with the D value, and it is determined whether or not the input board ID value matches the set board ID value.

In the circuit according to the present invention, the board ID value output means, when the board ID value is input from the CPU through the expansion slot, the read signal and the board ID value input from the expansion slot. The second AND gate for calculating the logical product of the coincidence signal output from the comparison means and the output signal in the high state of the second AND gate enable the memory hold state, and the input board ID value Second latch means for storing and holding
A buffer for buffering and outputting the board ID value stored and held by the second latch means.

According to this structure, the input board I is input.
When the D value matches the set board ID value, the board ID value is output to the CPU.
It is output to U and the presence of the corresponding circuit is confirmed by the CPU. In the circuit according to the invention of claim 4,
The input / output pot selection means includes a second decoder for decoding the pot ID value input from the address terminal of the expansion slot, and a decoding signal for the pot ID value output from the second decoder. A third AND gate for calculating the logical product of the write signal input from the expansion slot and the output signal in the high state of the third AND gate enables the storage and the storage becomes possible, and the data terminal of the expansion slot Third latch means for storing and holding the inputted pot ID value, the output signal of the second decoder and the board I
A third decoder for decoding the pot ID value which is enabled by the coincidence signal output from the D value comparison means to be in a decoding enabled state and stored and held by the third latch means.

According to such a configuration, the pot ID value input from the CPU is decoded, and the third AND
A high-state signal is output from the gate. This signal enables the third latch means to enable storage and storage, and the storage and storage by the third latch means. The output signal of the second decoder and the coincidence signal output from the board ID value comparison means enable the third decoder to enable decoding, and the pot ID stored and held by the third latch means. The value is decoded. In this way, the input / output pot is selected.

According to a fifth aspect of the present invention, there are provided one or a plurality of expansion slots connected to the CPU of the computer and a plurality of input / output devices for applying the data of the computer. A method for controlling input / output of computer data executed by a data input / output control circuit, wherein when a board ID value for designating a board is input from the CPU through an expansion slot, the board ID value is stored and held, The board ID value stored and held is compared with the preset board ID value, and when the stored board ID value and the set board ID value match, the board ID value that outputs a match signal When a match signal is output in the comparing step and the board ID value comparing step, it is confirmed that the corresponding circuit exists.
The board ID value output step of outputting the stored board ID value to the CPU through the expansion slot for confirmation by U, and the board ID value output in the board ID value output step. After it is confirmed that the input / output device selection pot ID value input from the CPU through the expansion slot is used, a plurality of data is input / output to / from each input / output device. An input / output pot selecting step of selecting a corresponding pot from the input / output pots, and a transmission path forming step of forming a data transmission route between the expansion slot and the corresponding input / output device when the corresponding pot is selected And, are included.

According to this method, in the board ID value comparison step, when the board ID value is input from the CPU through the expansion slot, the board ID value is stored and held, and the board ID value stored and held is preset. The set board ID value that has been set is compared, and as a result of the comparison, if the stored board ID value and the set board ID value match, a match signal is output.

In the board ID value output step, the board I
When the coincidence signal is output in the D value comparison step, the stored board ID value is output to the CPU through the expansion slot in order to make the CPU confirm that the corresponding circuit exists. As a result, in the input / output pot selection step, the pot ID value is input from the CPU after it is confirmed by the CPU that the corresponding circuit is present. To be selected.

When the corresponding pot is selected, in the transmission path forming step, a data transmission path is formed between the expansion slot and the corresponding input / output device. 7. The method according to claim 6, wherein the board ID value comparing step includes a board ID value decoding step of decoding a board ID value input from the CPU through an address terminal of an expansion slot, and the decoding. A board ID value storing and holding step for storing and holding the input board ID value based on the signal and the write signal input from the CPU through the expansion slot, and the stored and held board ID value and set board ID value And a coincidence signal output step of outputting a coincidence signal when they coincide with each other.

According to this method, the board ID value input from the CPU is decoded, and the board ID value input based on the decoding signal and the write signal input from the CPU through the expansion slot. Is stored and held, the board ID value stored and held is compared with the set board ID value, and when they match, a match signal is output.

According to a seventh aspect of the present invention, in the step of outputting the board ID value, the board ID value is the CPU.
When input through the expansion slot from, based on the match signal and the read signal input from the expansion slot,
This is a step of outputting the stored and held board ID value to the CPU through the expansion slot. According to this method, when the board ID value is input from the CPU, the stored and held board ID value is output to the CPU through the expansion slot based on the match signal and the read signal input from the expansion slot.

In the method according to the present invention, in the step of selecting the input / output pot, after the CPU confirms that the corresponding circuit is present, the pot ID is passed from the CPU through the address terminal of the expansion slot. Based on the pot ID value decoding step of decoding the pot ID value when the value is input, the decoding signal of the pot ID value and the write signal input from the CPU through the expansion slot, the CPU
The pot ID value stored and held based on the pot ID value storing and holding step of storing and holding the pot ID value input from the data terminal of the expansion slot through the pot, and the decoding signal and the coincidence signal of the pot ID value. And an input / output pot selection step of selecting a corresponding input / output pot based on the decoding signal of the pot ID value.

According to this method, after it is confirmed by the CPU that the corresponding circuit exists, the pot I is passed from the CPU through the address terminal of the expansion slot.
When the D value is input, the pot ID value is decoded, and the decoding signal of the pot ID value and C
The pot ID value input from the CPU is stored and held based on the write signal input from the PU through the expansion slot, and stored and held based on the decoding signal and the coincidence signal of the pot ID value. The pot ID value is decoded, and the corresponding input / output pot is selected based on the decoding signal of the pot ID value.

[0022]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to FIG.
~ It demonstrates based on FIG. Referring to FIG. 1 showing the present embodiment, one or a plurality of computer data input / output control circuits (hereinafter abbreviated as control circuits) 50 according to the present invention are incorporated in a computer main board. a it shall, are respectively connected to a plurality of input and output devices 70 ₁ to 70 _N to be used in applications of the expansion slots 40 and the computer to expand the functions of the computer.

The control circuit 50 decodes a board ID value for designating a board and a pot ID value for selecting an input / output device output from the address terminals (SA0 to SA11) of the expansion slot 40.
And the data terminal (SD0-SD0) of the expansion slot 40
SD7), and a buffer 52 for buffering a board ID value, a pot ID value and data respectively, and an AND gate 53 for performing a logical product operation of the output signal CS3 of the decoder 51 and the write signal IDWR of the expansion slot 40, A latch circuit 54 for latching the input board ID value from the buffer 52 by receiving an enable signal from the AND gate 53 and a board ID value setting section 55 for setting a board value from the outside.
And the board ID latched by the latch circuit 55
A comparator 56 that compares the value with the board ID value set by the board ID value setting unit 55, an output signal of the comparator 56, an output signal CS3 of the decoder 51, and the expansion slot 4
An AND gate 57 for calculating the logical product of the read signal IDRD of 0 and the board ID which is enabled by the AND gate 57 and latched by the latch circuit 54.
A latch circuit 58 that outputs a value to the data terminal (SD0 to SD7) of the expansion slot 40 through the buffer 52, and an AND gate that calculates the logical product of the output signal CS2 of the decoder 51 and the write signal IDWR of the expansion slot 40. 59, a latch circuit 60 that is enabled by the AND gate 59 and latches the pot ID value output from the buffer 52, and the latch circuit 60 that is enabled by the output signal CS1 of the decoder 51 and the output signal of the comparator 56. Decoder 6 for decoding the pot ID value input from the circuit 60
1 and a plurality of input / output pots 62 _{1 to} 62 _{N which} are connected to the plurality of input / output devices 70 ₁ to 70 _N and select corresponding pots according to output signals from output terminals CE 1 to CEN of the decoder 61. _{It has N} and.

Here, the board ID value comparing means includes a board ID value setting section 55 as a board ID value setting means for setting the board ID value of the circuit in advance, and a decoder 51 which is a first decoder. The AND gate 53 is a first AND gate, the latch circuit 54 is a first latch means, and a comparator 56. The board ID value output means is an AND gate 57 which is a second AND gate. And a latch circuit 58 as a second latch means.
And a buffer 52, and the input / output pot selection means includes a decoder 51 which is a second decoder and an AND gate 59 which is a third AND gate.
And a latch circuit 60 which is a third latch means, and a decoder 61 which is a third decoder.

[0025] In the case of multiple use of such control circuit 50, as shown in FIG. 3, the control circuit 50 _1-5
0 _N is connected to each expansion slot 40 ₁ to 40 _N and used. In this case, the CPU of the computer (hereinafter C
It is abbreviated as PU. ) Is output board ID value to select the control circuit of the appropriate in the control circuit 50 ₁ to 50 _N, and select the input and output pots appropriate in a plurality of input and output pots of the selected control circuit, the transmission of data I do.

Next, the operation will be described. In CPU, pot ID value of the board ID value and each input pots for accessing the respective control circuit 50, in advance, the control circuit 50 is set to the input and output device 70 every ₁ to 70 _N. Then the CPU
Output the board ID value of an arbitrary control circuit 50 to the expansion slot 40, and the board ID value is output to the expansion slot 40.
Is input to the decoder 51 through the address terminals SA0 to SA11. Further, this board ID value is decoded by the decoder 51 and the output signal CS3 in the high state is output.

Then, the output signal CS3 is input to the AND gate 53 together with the write signal IDWR in the high state output from the expansion slot 40, and the AND gate 53.
Outputs a high-state signal to the latch circuit 54, and the latch circuit 54 is enabled and becomes latchable.
When the enable signal is input to the latch circuit 54, CP
The board ID value output from U is transmitted to and latched by the latch circuit 54 through the data terminals SD0 to SD7 of the expansion slot 40 and the buffer 52.

Next, the board ID value latched by the latch circuit 54 is applied to one side input terminal PA of the comparator 56. The board ID value set from the outside through the board ID value setting unit 55 is applied to the other-power-side input terminal PB of the comparator 56. Next, in the comparator 56, both board ID values applied to the input / output terminals PA and PB are compared. As a result of the comparison, when both board ID values match, a high state signal is output from the output terminal (A = B), and when they do not match, a low state signal is output.

Next, it is confirmed whether or not there is an input board corresponding to the board ID value output from the CPU through the expansion slot 40. That is, the board ID value output from the spreading slot 40 is decoded by the decoder 51, and the decoding signal in the high state is output. Then, the AND gate 57 is connected to the recorder 51.
Decoding signal CS3, the read signal IDRD of the expansion slot 40, and the output terminal (A =
And the output signal of B) are input, and the logical product of these signals is calculated.

When the board ID value input from the CPU through the expansion slot 40 does not match the board ID value set by the board ID setting section 55 and the output signal of the comparator 56 is in the low state, A signal in the low state is output from the AND gate 57. At this time, the next operation is stopped. However, when the board ID value input from the CPU through the expansion slot 40 and the board ID value set by the board ID value setting unit 55 match, the comparator 56 outputs a high-level match signal. The AND gate 57 outputs a high-state signal to the latch circuit 58, and the latch circuit 58 is enabled.

When the latch circuit 58 is enabled, the board ID value latched by the latch circuit 54 is output to the data terminals SD0 to SD7 of the expansion slot 40 through the latch circuit 58 and the buffer 52, respectively.
It is transmitted to the CPU. In the CPU, the board ID value read by the latch circuit 54 was previously stored in the expansion slot 4
When it matches the board ID value output to 0, it is determined that the corresponding control circuit 50 exists.

When it is determined that the corresponding control circuit 50 exists, the CPU controls the input / output pots 62 _{1 to} 62 _N.
The pot ID value for selecting the corresponding input / output pot is output to the expansion slot 40. This pot ID value is transferred from the expansion slot 40 to the address terminals SA0 to SA1.
It is input to the decoder 51 through 1 and the pot ID value is decoded in the decoder 51, and the high-state signals CS1 and CS2 are output.

Then, in the AND gate 59, the output signal CS2 in the high state and the write signal IDWR in the high state output from the expansion slot 40 are logically ANDed, and the signal in the high state is output. The high level signal enables the latch circuit 60. When the latch circuit 60 is enabled, the pot ID value output from the data terminals SD0 to SD7 of the expansion slot 40 is transmitted to the latch circuit 60 through the buffer 52 and latched.

Next, the decoder 61 outputs the output signal CS1 of the decoder 51 and the output terminal of the comparator 56 (A =
The pot ID value output from the latch circuit 60 is decoded by the high level signal output from B) and is decoded. Accordingly, the decoder 61 turns on the corresponding terminal among the output terminals CE1 to CEN according to the decoded pot ID value and enables the corresponding input / output pot among the plurality of input / output pots 62 _{1 to} 62 _N. It

When a corresponding input / output pot is selected from the plurality of input / output pots 62 _{1 to} 62 _N through the above process, a data transmission path is formed between the selected pot and the buffer 52. To be done. When this path is formed,
Data from the CPU passes through the expansion slot 40, the buffer 52, and the selected input / output pot, and then the input / output device 7
0 ₁ to 70 _N is selected is transmitted to the output device from among, and, conversely, data from the selected output device is transmitted to the expansion slot 40.

According to this structure, there is an effect that a plurality of input / output devices can be widely applied to a computer without limitation, and a large number of input / output devices can be connected to expand the utilization of the computer. . Incidentally, such processing can be realized by software.
That is, in the computer data input / output control method according to the present invention having such a configuration, the board ID value input from the computer through the expansion slot 40 is stored and held, and the stored board ID value is stored outside. Board ID value comparison step of comparing the board ID value set from the
When the values match, the stored and held board ID value is output to the CPU through the expansion slot 40, and it is confirmed that the corresponding data input / output control circuit exists among the plurality of data input / output control circuits. When the pot ID value is input from the CPU through the expansion slot 40 as a result of the board ID value output step for confirmation and the confirmation result, the corresponding input / output pot is selected from the plurality of input / output pots to set the data transmission path. The step of selecting an input / output pot to be formed is sequentially performed.

In the board ID value comparing step, a board ID value decoding step for decoding a board ID value inputted from the CPU through the address terminal of the expansion slot 40, and the decoding signal and the CPU are expanded. A board ID value storing and storing step of storing and holding a board ID value input through the data terminal of the expansion slot by a write signal output through the slot, and the stored and stored board ID value and external setting If the result of the comparison is a match, a match signal is output for the board ID value output step and the input / output pot selection step. The comparison step and the comparison step are sequentially performed.

In the board ID value output step,
The board ID stored and held in the board ID value storing and holding step by the signal decoded in the board ID value decoding step, the output signal from the coincidence signal outputting step, and the read signal input from the expansion slot Value through expansion slot 40 to C
It is designed to output to PU.

Further, in the input / output pot selection step, after it is confirmed by the CPU that the corresponding data input / output control circuit exists in the board ID value output step, the data is output from the CPU through the address terminal of the expansion slot 40. Is output through the data terminal of the expansion slot 40 by the pot ID value decoding step for decoding the pot ID value and the decoded pot ID value and the write signal output through the expansion slot. A step of storing and holding a pot ID value, and a step of storing and holding the pot ID value;
The pot ID value stored and held in the D value storing and holding step is decoded by the signal decoded in the pot ID value decoding step and the signal output from the coincidence signal output step to select the corresponding input / output pot. The selection step and the selection step are sequentially performed.

This process will be specifically described with reference to the flowchart of FIG. In step (denoted as "S" in the drawing, the same applies hereinafter) 1, a board ID value for the CPU to access the control circuit 50 is input from the address terminals (SA0 to SA11) of the expansion slot 40. . In step 2, the input board ID value is latched.

In step 3, the latched board I
The D value is compared with the board ID value set from the outside, and the latched board ID value is the board I set from the outside.
If it matches the D value, go to step 4. In step 4, since the same board ID value as the latched board ID value is output from the CPU, the control circuit 50 causes the CP
This board ID value is output to the CPU to confirm that the circuit is designated by U.

In step 5, after the CPU confirms the board ID value, the CPU outputs the input / output pot ID value. Therefore, this input / output pot ID value is input. In step 6, this input / output pot ID value is latched. In step 7, the latched input / output pot ID value is decoded. In step 8, this input / output pot ID
A corresponding input / output pot is selected from a plurality of input / output pots based on the value decoding signal to form a data transmission path.

In step 9, data transmission is performed via the formed transmission path.

[0044]

As described above, according to the circuit of the first aspect of the present invention, a plurality of input / output pots are added to one data input / output control circuit, and one or more data input / output control circuits are provided. Since it is built in each computer, there is an effect that a plurality of input / output devices can be widely applied to the computer without limitation.

According to the circuit of the invention of claim 2, it is possible to determine whether or not the input board ID value matches the set board ID value. According to the circuit of the third aspect of the present invention, when the input board ID value matches the set board ID value, the board ID value is output to the CPU to check that the corresponding circuit exists. C
It can be checked by the PU.

According to the circuit of the invention of claim 4, the input / output pot can be selected. According to the method of the invention of claim 5, a large number of input / output devices can be connected to the CPU of the computer, and the utilization of the computer can be expanded. According to the method of the sixth aspect of the present invention, it is possible to determine whether or not the input board ID value matches the set board ID value.

According to the seventh aspect of the present invention, when the input board ID value matches the set board ID value, the board ID value is output to the CPU and the corresponding circuit exists. It is possible to make the CPU confirm that there is. According to the method of the invention of claim 8, the input / output pot can be selected.

[Brief description of drawings]

FIG. 1 is a connection state display diagram of a block of a data input / output control circuit for a computer according to the present invention and parts of an association device.

FIG. 2 is a flowchart showing the operation of a data input / output control circuit for a computer according to the present invention.

FIG. 3 is an explanatory diagram of the addition state of the computer data input / output control circuit according to the present invention.

FIG. 4 is a block diagram of a conventional data input / output board for a computer and a connection state display diagram with parts of an association device.

[Explanation of symbols]

10, 40 Expansion slot 20 Data input / output board 50 (Data input / output) control circuit 21, 51, 61 Decoder 22, 52 Buffer 53, 57, 59 AND gate 54, 58, 60 Latch circuit 55 Board ID value setting unit 56 Comparator 62 _{1 to} 62 _{N I} / O pot 70 ₁ to 70 _{N I} / O device

Claims (8)

[Claims] 1. An input / output control of one or a plurality of computer data connected between an expansion slot connected to a CPU of a computer and a plurality of input / output devices for applying the data of the computer. A circuit, wherein when a board ID value for designating a board is input from the CPU through an expansion slot, the board ID value is stored and held, and the stored board ID value is stored as a preset board ID value. When the board ID value stored and held matches the set board ID value, the board ID value comparing means for outputting a match signal and the board ID value comparing means for outputting the match signal A board ID value output means for outputting the stored board ID value to the CPU through the expansion slot in order to confirm to the CPU that the circuit exists; Using the pot ID value for selecting the input / output device that is input from the CPU through the expansion slot after it is confirmed by U that the corresponding circuit exists, data is exchanged with each input / output device. Input / output pot selection means for selecting a corresponding pot from a plurality of input / output pots for input / output, and an expansion slot and a corresponding input / output device when the corresponding pot is selected by the input / output pot selection means. An input / output control circuit for computer data, comprising: a transmission path forming means for forming a data transmission path between the two. 2. The board ID value comparing means previously sets board ID value setting means for setting the board ID value of the circuit, and first decoding the board ID value input from the address terminal of the expansion slot. And a first AND gate for calculating the logical product of the decoding signal of the board ID value output from the first decoder and the write signal input from the expansion slot, and the first AND gate. It is set by the first latch means for storing and holding the board ID value outputted from the data terminal of the expansion slot, which is enabled by the output signal in the high state of the gate, and is set in the memory hold state, and the board ID value setting means. The set board ID value and the board ID value stored and held by the first latch means are compared and compared. Fruit, setting board ID
3. A comparator for outputting a coincidence signal to the board ID value output means and the input / output pot selection means when the value and the stored and held board ID value match each other. The data input / output control circuit for the computer described in. 3. The board ID value output means, when a board ID value is input from the CPU through an expansion slot, a read signal input from the expansion slot and a match signal output from the board ID value comparison means. A second AND gate for calculating the logical product of the second AND gate and a second latch for enabling the memory hold state by being enabled by the output signal of the second AND gate in the high state, and storing and holding the input board ID value. 2. An input / output control circuit for computer data according to claim 1, further comprising: a means and a buffer for buffering and outputting the board ID value stored and held by the second latch means. 4. The input / output pot selection means includes a second decoder for decoding the pot ID value input from the address terminal of the expansion slot, and a pot ID value output from the second decoder. And a write signal inputted from the expansion slot, and a third AND gate, which is enabled by the output signal of the third AND gate in the high state, becomes a memory-holdable state and is expanded. Third latch means for storing and holding the pot ID value inputted from the data terminal of the slot, and decoding enabled by the output signal of the second decoder and the coincidence signal outputted from the board ID value comparing means. The pot ID value stored and held by the third latch means is set in the ready state. The computer data input / output control circuit according to claim 1, further comprising a third decoder for reading. 5. One or a plurality of data input / output control circuits connected between an expansion slot connected to a CPU of a computer and a plurality of input / output devices that apply data of the computer. A method for controlling input / output of computer data, wherein when a board ID value for designating a board is input from the CPU through an expansion slot, the board ID value is stored and held, and the stored board ID value and the stored board ID value are stored in advance. The set board ID value that has been set is compared, and as a result of the comparison, when the stored and held board ID value and the set board ID value match, a board ID value comparison step of outputting a match signal, and the board ID value When the coincidence signal is output in the comparison step, the stored board ID value is expanded in order to make the CPU confirm that the corresponding circuit exists. The board ID value output step of outputting to the CPU through the slot, and the board ID value output step of the board ID value output step, after the CPU confirms that the corresponding circuit exists, the CPU passes through the expansion slot. Input / output for selecting a corresponding pot from a plurality of input / output pots for inputting / outputting data to / from each input / output device by using the pot ID value for input / output device selection input The data input for the computer is characterized by including a pot selecting step and a transmission path forming step of forming a data transmission path between the expansion slot and the corresponding input / output device when the corresponding pot is selected. Output control method. 6. The board ID value comparing step includes a board ID value decoding step of decoding a board ID value inputted from the CPU through an address terminal of an expansion slot, and the decoding signal and expansion from the CPU. A board ID value storing and holding step of storing and holding the input board ID value based on the write signal input through the slot, and comparing the stored and held board ID value with the set board ID value, 6. The computer data input / output control method according to claim 5, further comprising a coincidence signal output step of outputting a coincidence signal when they coincide with each other. 7. The board ID value output step is stored and held based on a match signal and a read signal input from the expansion slot when the board ID value is input from the CPU through the expansion slot. 6. The computer data input / output control method according to claim 5, further comprising the step of outputting the board ID value to the CPU through an expansion slot. 8. The input / output pot selection step, when a pot ID value is input from the CPU through an address terminal of an expansion slot after it is confirmed by the CPU that the corresponding circuit is present, Pot I
Based on the pot ID value decoding step of decoding the D value, and the write signal input from the CPU through the expansion slot through the decoding signal of the pot ID value and through the data terminal of the expansion slot. Based on the pot ID value storage and holding step of storing and holding the input pot ID value, the stored and held pot ID value is decoded based on the decoding signal and the coincidence signal of the pot ID value. 6. The method for controlling input / output of computer data according to claim 5, further comprising: an input / output pot selection step of selecting a corresponding input / output pot based on a decoding signal.