JPH0818036A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce noise and fully improve transconductance and frequency characteristics. CONSTITUTION:A source electrode 1, a drain electrode 2, and a gate electrode 3 are provided, a number of thin wires 13 are aligned at the lower part of the gate electrode 3, the source electrode 1, the drain electrode 2, and the thin wires 13 are separated, and n-type AlGaAs layer 5 with a sheet resistance of 50OMEGA/each is formed among the source electrode 1, the drain electrode 2, and the gate electrode 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a source electrode, a drain electrode and a gate electrode, and a plurality of thin wires arranged in parallel under the gate electrode.

[0002]

2. Description of the Related Art Recently, in electric conduction in a one-dimensional thin wire using an AlGaAs / GaAs heterojunction semiconductor, since backscattering due to ionized impurity scattering is suppressed, the electron mobility is 2DEG (two-dimensional electron gas 2 Dimentional El
It was reported that it would be larger than that of ectron gas (Japanese Journal of Apllied Phys
ics 1980 L735)). As a result of this, vigorous research was conducted on the behavior of electrons in thin wires both theoretically and experimentally (for example, IE Electron).
Device Letter (Dejan Jovanovic et al. IEEE ELEC
TRON DEVICE LETTER Vol. 14 7 1993)). One of them is a saturation phenomenon at a low voltage of current in a current-voltage (IV) characteristic of a thin wire. This means that the current saturates at a small voltage value that is the sum of the energy due to heat and the difference in Fermi energy between terminals (H.Tsuchiya IEEE TRANSACTIO).
NS ON ELECTRON DEVICES VOL. 39 2465 1992). Also,
Many attempts have been made to apply a thin wire to a channel (active layer) of a field effect transistor (FET), and some results of actually fabricating and evaluating the device have been reported (K. Onda (K. Onda)). IEDM 125 1989), Applied Physics Letter (K. Ismail Applied Ph.
ysics Letter 54 1130 1989)).

FIG. 12 is a plan view showing a conventional field effect transistor using a thin wire for an active layer, that is, a quantum wire field effect transistor. As shown in the figure, the source electrode 1
The mesa etching region 4 is provided between the drain electrode 2 and the drain electrode 2, a large number of thin wires (channels) 13 are arranged in parallel between the source electrode 1 and the drain electrode 2, and the gate electrode 3 is formed on the thin wire 13. ing.

In this quantum wire field effect transistor, the transconductance gm, which is the amount of change in the current Ids between the source electrode 1 and the drain electrode 2 when the voltage of the gate electrode 3 is changed, is improved, and the noise is reduced. And higher characteristics in a high frequency range can be achieved. Furthermore, when the quantum wire field-effect transistor is used as a switching element due to the saturation phenomenon at the low voltage described above, there is an advantage that the number of inputs can be increased because the ON resistance becomes small. .

[0005]

However, in such a quantum wire field effect transistor, since the thin wire 13 is in contact with the source electrode 1, the source electrode resistance Rs is very large. That is, the source electrode resistance Rs consists of a contact resistance Rsc when forming the source electrode 1 and an active layer resistance Rsg from the source electrode 1 to the gate electrode 3,
The contact resistance Rsc is not so different from the value of the 2DEG field effect transistor, whereas the active layer resistance Rsg is much larger. The reason for this is that, as shown in FIG. 12, all the active layers from the source electrode 1 to the drain electrode 2 are thin lines 13.
Because it is made of. That is, when the active layer is composed of the thin wire 13, the electric conductivity is increased due to the quantum effect, but the side wall fluctuation of the thin wire 13, the reduction of the carrier concentration due to the effects of defects, damage, etc., and the ratio of the length to the width of the thin wire. With the increase, the absolute value of the resistance of the thin wire 13 itself increases. Therefore, if there is the thin wire 13 between the source electrode 1 and the gate electrode 3, the active layer resistance Rsg becomes much larger than that in the 2DEG field effect transistor, and the source electrode resistance Rs becomes large. Further, the influence of the carrier concentration decrease is very large, and it cannot be avoided by the fine line 13 formed by mesa etching. For this reason, it is not possible to sufficiently reduce the noise and improve the transconductance gm and the frequency characteristic, and there are few experimental reports showing excellent characteristics with respect to a field effect transistor using a one-dimensional thin wire.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor device capable of sufficiently reducing noise and improving transconductance and frequency characteristics.

[0007]

In order to achieve this object, in the present invention, a semiconductor device having a source electrode, a drain electrode and a gate electrode, in which a number of thin wires are arranged in parallel under the gate electrode, The source electrode and the thin wire are separated from each other.

In this case, a semiconductor cap layer having a sheet resistance of 100 Ω / □ or less is formed between the source electrode and the gate electrode.

Further, the length of the thin wire is shorter than the length of the gate electrode, and the thin wire exists only under the gate electrode.

Further, the length of the thin wire is equal to or longer than the length of the gate electrode.

[0011]

In this semiconductor device, the source electrode resistance is small.

Further, when the semiconductor cap layer having a sheet resistance of 100 Ω / □ or less is formed between the source electrode and the gate electrode, the source electrode resistance is very small.

When the length of the thin wire is shorter than the length of the gate electrode and the thin wire exists only under the gate electrode, the source electrode resistance is very small.

[0014]

【Example】

(Embodiment 1) FIG. 1 shows a HEMT (High Electron Mobility Transisto) using a double heterojunction according to the present invention.
r) A diagram showing a quantum wire field effect transistor having a structure, FIG. 2 is a sectional view taken along line AA of FIG. 1, and FIG. 3 is a sectional view taken along line BB of FIG. As shown in the figure, an undoped GaAs layer 10 of a buffer layer is formed on a semi-insulating GaAs substrate 11,
An undoped AlGaAs layer 9 made of Al _X Ga _1-X As (composition ratio X = 0.3) is formed on the undoped GaAs layer 10, and an undoped GaAs layer 8 having a 2DEG region 12 is formed on the undoped AlGaAs layer 9. , An undoped AlGaAs layer 7 serving as a spacer layer is formed on the undoped GaAs layer 8,
The n-type AlGaAs layer 6 doped with Si is formed on the layer 7, and the n-type GaAs layer 5 having a thick film low resistance (sheet resistance of 50Ω / □) doped with Si on the n-type AlGaAs layer 6
Are formed, the mesa etching region 4 is provided in the n-type AlGaAs layer 6, the gate electrode 3 is formed on the n-type AlGaAs layer 6, and the source electrode 1 and the drain electrode 2 are formed on the n-type GaAs layer 5. A number of thin wires 13 are arranged in parallel between the source electrode 1 and the drain electrode 2. The length of the thin wire 13 is shorter than the length of the gate electrode 3, and the thin wire 13 exists only below the gate electrode 3.

Next, a method of manufacturing the field effect transistor shown in FIGS. 1 to 3 will be described. First, MBE (Molecular Beam Epitaxy) is formed on the semi-insulating GaAs substrate 11.
y) and the like to form an undoped GaAs layer 10 of 500 n
m, AlGaAs layer 9 is 500 nm, undoped GaA
The s layer 8 is 12 nm, and the undoped AlGaAs layer 7 is 2 n
A 35 nm thick m, n-type AlGaAs layer 6 is formed. Next, the n-type GaAs layer 5 is formed on the n-type AlGaAs layer 6 by 13
0 nm is formed. Next, CVD (Chemical Vapor Dep
SiO ₂ film is formed to a thickness of 30 nm by osition) and an ohmic source electrode 1 and a drain electrode 2 made of AuGe / Ni / Au are manufactured by a lift-off method and alloying. Next, after removing the SiO ₂ film of the spacer layer, CVD
To form a SiO ₂ film with a thickness of 30 nm, apply an electron beam resist to a thickness of 100 nm on the SiO ₂ film, and use an electron beam drawing device or the like to measure a length of 100 to 3 in a direction along the source electrode 1 and the drain electrode 2.
00 nm, width 30 to 100 nm, period 60 to 200 nm
Process the resist with the dimensions of and make a hole. Next, the underlying SiO ₂ film is etched with hydrofluoric acid containing a buffer to remove the resist. Using this SiO ₂ film as a mask, the n-type GaAs layer 5 is selectively dry-etched, and then n
The type AlGaAs layer 6 is wet-etched with a phosphoric acid-based etching solution to provide a mesa etching region 4. At this time, in order to minimize the influence of the surface level of the etched surface, the n-type AlGaAs layer 6 is etched shallowly to about 10 nm. Alternatively, a method of etching the entire undoped GaAs layer 8 by dry etching without damage may be used. Next, after cleaning this substrate, a SiO ₂ film is formed to 300 nm by CVD, an electron beam resist is applied, and a groove is formed in a portion corresponding to the portion where the mesa etching region 4 of the resist is provided by an electron beam drawing apparatus. And the SiO ₂ film is used as a mask by using the resist as a mask.
After 0 nm dry etching, the remaining 50 nm is wet etched. Next, the n-type GaAs layer 5 is selectively dry-etched. At this time, 100 in the lateral direction
Isotropic overetching is performed so that the etching is about 300 nm. Next, Al is vapor-deposited and the Schottky gate electrode 3 is formed by the lift-off method. At this time, the gate electrode 3 is formed so as to cover the mesa etching region 4 as shown in FIG.

In the field effect transistor shown in FIGS. 1 to 3, the source electrode 1, the drain electrode 2 and the thin wire 13 are provided.
And the n-type GaAs layer 5, which is a semiconductor cap layer having a sheet resistance of 50Ω / □, is formed between the source electrode 1 and the drain electrode 2 and the gate electrode 3, so that the source electrode resistance Rs Is very small, so that it is possible to sufficiently reduce noise and improve the transconductance gm and frequency characteristics.

That is, the source electrode 1 and the drain electrode 2
Is Rc (Ω · cm), and the sheet resistance of the active layer from the source electrode 1 to the gate electrode 3 is ρs (KΩ /
□), the distance from the source electrode 1 to the gate electrode 3 is Ls
If g and the width of the thin wire 13 are W, the source electrode resistance Rs is expressed by the following equation.

[0018]

## EQU1 ## Rs = Rsc + Rsg = Rc. (1 / W) +. Rho.s. (Lsg / W) Here, in a general 2DEG field effect transistor,
Gate electrode width 10 μm, sheet resistance ρs 1 KΩ / □
In this case, the contact resistance Rsc is about 20Ω, the active layer resistance Rsg is about 60Ω, and the source electrode resistance Rs is about 80Ω as a whole. Further, the contact resistance Rsc of the conventional quantum wire field effect transistor having a wire width W = 0.1 μm is 2DEG.
Almost same as field effect transistor, but active layer resistance Rsg
Is getting bigger. This is because the sheet resistance ρs is 5 KΩ / □, which is about 5 times larger than that of the 2DEG field effect transistor due to a decrease in carrier concentration. As a result, the source electrode resistance Rs has a considerably large value of about 320 KΩ. On the other hand, in the field effect transistor shown in FIGS. 1 to 3, the source electrode resistance Rs
The active layer resistance Rsg, which is the cause of increasing the
Like the DEG field effect transistor, it can be set to about 60Ω.

The voltage Vtr applied between the source electrode 1 and the gate electrode 3 is represented by the following equation.

[0020]

As is clear from Vtr = Vgs−Rs · Ids (Equation 2), the voltage Vtr is a value obtained by subtracting Rs · Ids from the voltage Vgs. Therefore, the larger the source electrode resistance Rs, the higher the transformer. The conductance gm becomes worse. That is, reducing the source electrode resistance Rs directly contributes to improving the transconductance gm. Further, since the gate electrode 3 is formed on the thin line 13 formed by shallow mesa etching, it is possible to suppress the decrease in carrier concentration. Further, when the gate electrode 3 is formed on the thin wire 13 formed by mesa etching, the potential can be changed from the side of the thin wire 13 by the voltage of the gate electrode 3 and the width of the thin wire 13 can be easily changed. It is possible to make the one-dimensional characteristic of This improves the transconductance gm in the form of the second term of the following equation.

[0021]

[Formula 3] gm = q ・ vs ・ W ・ N ・ ∂ns / ∂Vgs + q ・ ns ・ v
s · N · ∂W / ∂Vgs Note that q is the elementary charge, vs is the electron saturation speed, N is the number of fine lines, and ns is the two-dimensional electron concentration. Further, since the length of the thin wire 13 is shortened from several μm to about 0.1 μm, the transconductance gm is further improved due to the contribution of ballistic electron conduction.

There is a minimum noise figure NFmin as an index indicating noise performance. A parameter peculiar to a material or structure is K, an operating frequency is f, a capacitance between the source electrode 1 and the gate electrode 3 is Cgs, and a gate electrode is When the resistance is Rg, the minimum noise figure NFmin is expressed by the following equation.

[0023]

NFmin = 1 + K · f · Cgs · √ ((Rs + Rg) / gm) In the field effect transistor shown in FIGS. 1 to 3,
The source electrode resistance Rs can be reduced and the gate electrode resistance Rg can also be reduced. The reason is that when the channel is modulated by the gate electrode voltage, 1DEG (electrons in the thin wire) is more easily affected than 2DEG, so the so-called gate electrode length is determined by the thin wire length. In other words, even if the gate electrode length is made longer than the thin wire length, it does not affect the characteristics so much.
When compared with a field effect transistor having the same gate electrode length, the gate electrode length can be made slightly longer and the gate electrode resistance Rg
Can be made smaller. Then, as is clear from (Equation 4), when the gate electrode resistance Rg decreases, the minimum noise figure N
Fmin can be lowered.

FIG. 4 is a graph showing the transconductance characteristics of the quantum wire field effect transistor. Since the quantum wire field effect transistor has a short effective gate electrode width, the transconductance g is removed in order to eliminate this effect.
m is divided by the current Ids between the source electrode 1 and the drain electrode 2 and standardized. As you can see from this graph,
The transconductance gm of the quantum wire field effect transistor according to the present invention is up to about 10 as compared with the transconductance gm of the conventional quantum wire field effect transistor.
It is twice.

FIG. 5 is a graph showing the frequency characteristics of the current gain of the quantum wire field effect transistor. The quantum wire according to the present invention has a source electrode resistance Rs and a gate electrode resistance Rg.
Can be made small, the current gain is 10
It becomes about 20 dB at GHz, which is about 1.6 times that of the conventional quantum wire field effect transistor and about twice that of the 2DEG field effect transistor.

FIG. 6 is a graph showing the noise figure of the quantum wire field effect transistor. The quantum wire field effect transistor according to the present invention can have a noise figure of about 0.3 dB at an operating frequency of 30 GHz, which is about 40 to 50% as compared with the conventional quantum wire field effect transistor and about 30 as compared with the 2DEG field effect transistor. It can be up to 40%. In addition, this shows similarly good characteristics even at a minute current.

(Embodiment 2) FIG. 7 is a diagram showing another quantum wire field effect transistor according to the present invention. As shown in the figure, the length of the thin wire 13 is longer than the length of the gate electrode 3,
Others are the same as in the first embodiment.

(Embodiment 3) FIG. 8 is a sectional view showing another quantum wire field effect transistor according to the present invention. As shown in the figure, the Si-doped n-type GaAs layer 5 and SiN layer 16 are formed in stripes on the n-type AlGaAs layer 6, and the gate electrode 3 is formed on the n-type GaAs layer 5 and SiN layer 16. ing.

Next, a method of manufacturing the quantum wire field effect transistor shown in FIG. 8 will be described. First, the steps up to the step of forming the ohmic source electrode 1 and the drain electrode 2 are the same as in Example 1 except that the thickness of the n-type GaAs layer 5 is reduced to 10 nm. Next, by CVD, SiN
The layer 16 is formed to have a thickness of 30 nm, and the electron beam drawing is applied to the first embodiment.
A resist pattern is formed with the same dimensions as (to leave the resist pattern). At this time, the regions of the source electrode 1 and the drain electrode 2 are also covered. Using this resist as a mask, the underlying SiN layer 16 is etched. Next,
After removing the resist, a SiO ₂ film having a thickness of 300 nm is formed by CVD as in Example 1, and an electron beam resist is applied. Next, a resist pattern (groove) is formed for forming a gate electrode with an electron beam drawing apparatus. Next, the SiO ₂ film is selectively dry-etched so that the SiN layer 16 is not etched, and then the n-type GaAs layer 5 is dry-etched. After that, a Schottky gate electrode 3 made of Ti / Pt / Au or Al is vapor-deposited and formed by lift-off. The undoped GaAs layer 8 of the channel layer was strained (Pseudomorphi
c) It is also possible to use an InGaAs layer.

(Embodiment 4) FIG. 9 shows an MES according to the present invention.
(Metal Semiconductor) It is sectional drawing which shows a field effect transistor. As shown in the figure, an undoped GaAs layer 14 of a buffer layer is formed on the semi-insulating substrate 11,
Si is added to the undoped GaAs layer 14 by 2 × 10 ¹⁷ (1 /
cm ³ ), a doped n-type GaAs layer 15 is formed, and n
The mesa etching region 4 is provided in the type GaAs layer 15,
The gate electrode 3 is provided on the portion where the mesa etching region 4 is provided.
Are formed.

Next, a method of manufacturing the quantum wire field effect transistor shown in FIG. 9 will be described. First, an undoped GaAs layer 14 having a thickness of 1 μm is formed on the semi-insulating substrate 11 by MBE or the like, and then an n-type GaAs layer 15 is formed by 20.
0 nm is formed. Next, an insulating film made of SiO ₂ or the like is formed to a thickness of 300 nm by CVD, and a 500 nm groove is formed in the resist on the insulating film by using photolithography.
The lower insulating film is etched with buffered hydrofluoric acid. Next, the n-type GaAs layer 15 is etched by 100 nm with a phosphoric acid-based etchant. Next, an n-type GaAs having the same size and the same procedure as in Example 1 was prepared using an electron beam drawing apparatus.
The mesa etching region 4 of the layer 15 is formed, and the gate electrode 3 is formed by lift-off as in the third embodiment.

In this quantum wire field effect transistor, the saturation voltage of the current flowing between the source electrode 1 and the drain electrode 2 is 10 because the channel is formed one-dimensionally.
Ultra low voltage of 0 meV and power supply voltage of 1.0 to 1.5
As a power field effect transistor used at a low voltage of about V, high efficiency and low voltage operation are possible. Although the active layer is the n-type GaAs layer 15, the gate electrode 3 and the n-type G layer are used.
Undoped A of 10 to 300 nm between the aAs layer 15
The introduction of the 1GaAs layer can increase the logic amplitude.

(Embodiment 5) FIG. 10 shows an enhancement type junction according to the present invention.
ion) A gate electrode type field effect transistor is shown in a plan view, and FIG. 11 is a sectional view taken along line CC of FIG. As shown in the figure, Al _x doped with 1 × 10 ¹⁸ (1 / cm ³ ) of Si
N-type AlG composed of Ga _1-X As (composition ratio X = 0.3)
An n-type GaAs layer 22 is formed on the aAs layer 6, and n-type G
The source electrode 1 and the drain electrode 2 are formed on the aAs layer 22, and the undoped AlGaAs made of Al _X Ga _1-X As (composition ratio X = 0.3) is provided between the n-type GaAs layers 22 on the n-type AlGaAs layer 6. Layer 17 is formed, undoped Al
2 × 10 ¹⁹ (1 /) of C (carbon) on the GaAs layer 17
cm ³ ) Doped Al _X Ga _1-X As (composition ratio X =
0.45) p-type AlGaAs layer 18 is formed, and C is added to the p-type AlGaAs layer 18 at 4 to 8 × 10 4.
²⁰ (1 / cm ³ ) doped p ⁺⁺ type GaAs layer 19 is formed, and W (tungsten) is formed on the p ⁺⁺ type GaAs layer 19.
The layer 20 is formed, the SiN (silicon nitride) layer 21 is formed on the undoped AlGaAs layer 17, etc., and the W layer 20 is formed.
A gate electrode 23 is formed on the.

Next, a method for manufacturing the quantum wire field effect transistor shown in FIGS. 10 and 11 will be described. First, an undoped GaAs layer 10 of 1 μm and an undoped AlGaAs layer 9 are formed on the semi-insulating substrate 11 by MBE or the like.
With a thickness of 15 nm. Next, the undoped GaAs layer 8
Is 1 μm, the undoped AlGaAs layer 7 is 15 nm, n
Type AlGaAs layer 6 of 200 nm, undoped AlGa
The As layer 17 is 15 nm and the p-type AlGaAs layer 18 is 50 nm.
nm, p ^{+ +} type GaAs layer 19 is continuously formed for 50 nm. W is sputtered on the substrate having the above structure.
The layer 20 is deposited to a thickness of 800 nm, and a SiN layer is formed to a thickness of 50 nm using a plasma CVD apparatus. A 1 μm thick photoresist is applied on top of this, and after exposure, Si is used with the photoresist as a mask.
Etching the N layer. Next, the W layer 20 is dry-etched. After the W layer 20 is dry-etched, the GaAs layer 19 is etched by dry etching such as RIE, and then the p-type AlGaAs layer 18 is etched to 20 n.
m-etched and remaining 30 nm of p-type AlGaAs layer 1
8 is selectively etched with respect to the undoped AlGaAs layer 17 with hydrofluoric acid. Next, after removing the resist,
The SiN layer 21 is formed to 50 nm and the SiO ₂ film is formed to 300 nm by P-CVD. Next, dry etching is performed under the condition that the SiO ₂ film remains only on the side wall of the gate electrode 23 (SiN layer 21 is not etched). This S
Using the iO ₂ film as a mask, the lower SiN layer 21 is selectively etched with phosphoric acid boiled at 150 ° C., and further etched with hydrofluoric acid.
The 1GaAs layer 17 is selectively wet-etched.
Next, recrystallization growth of the n-type GaAs layer 22 is performed by MOCVD. Next, a SiO ₂ film is formed by CVD to 50
With a thickness of 0 nm, and AuGe / Ni /
A source electrode 1 and a drain electrode 2 made of Au are formed. Next, after removing the SiO ₂ film, an insulating film made of PIQ (polyimide resin) or the like is formed by 1.5 to flatten the surface.
μm coating, electron beam resist 100nm on insulating film
Apply. Next, a resist pattern is formed by an electron beam drawing apparatus so that a groove is formed on the W layer 20.
Next, the insulating film and the SiN layer 21 are dry-etched, Mo / Au is vapor-deposited at 50/400 nm, and then lift-off is performed to form the gate electrode 23.

In addition, the n-type AlGaAs layer 6 and the undoped AlGaAs layer 7 are formed into an n-type GaAs layer and p-type AlGaA.
If the s layer 18 is replaced with a p-type GaAs layer, a MES type junction gate electrode type field effect transistor is also possible.

[0036]

As described above, in the semiconductor device according to the present invention, since the source electrode resistance is small, it is possible to sufficiently reduce noise and improve transconductance and frequency characteristics.

When a semiconductor cap layer having a sheet resistance of 100 Ω / □ or less is formed between the source electrode and the gate electrode, the source electrode resistance is very small, so that noise reduction, transconductance and frequency are reduced. It is possible to more sufficiently improve the characteristics.

Further, when the length of the thin wire is shorter than the length of the gate electrode and the thin wire exists only under the gate electrode, the resistance of the source electrode is very small, resulting in low noise, low transconductance and frequency characteristics. Further improvement can be achieved.

[Brief description of drawings]

FIG. 1 is a diagram showing a quantum wire field effect transistor according to the present invention.

FIG. 2 is a sectional view taken along line AA of FIG.

FIG. 3 is a sectional view taken along line BB of FIG. 1;

FIG. 4 is a graph showing a transconductance characteristic of a quantum wire field effect transistor.

FIG. 5 is a graph showing frequency characteristics of current gain of a quantum wire field effect transistor.

FIG. 6 is a graph showing the noise figure of a quantum wire field effect transistor.

FIG. 7 is a diagram showing another quantum wire field effect transistor according to the present invention.

FIG. 8 is a sectional view showing another quantum wire field effect transistor according to the present invention.

FIG. 9 is a cross-sectional view showing another quantum wire field effect transistor according to the present invention.

FIG. 10 is a diagram showing an enhancement type junction gate electrode type field effect transistor according to the present invention.

11 is a cross-sectional view taken along line CC of FIG.

FIG. 12 is a diagram showing a conventional quantum wire field effect transistor.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Source electrode 2 ... Drain electrode 3 ... Gate electrode 5 ... N-type GaAs layer 13 ... Fine line 22 ... N-type GaAs layer 23 ... Gate electrode

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location H01L 29/80

Claims (4)

[Claims] 1. A semiconductor device having a source electrode, a drain electrode and a gate electrode, and a plurality of thin wires arranged in parallel under the gate electrode, wherein the source electrode and the thin wire are separated from each other. Semiconductor device. 2. The semiconductor device according to claim 1, wherein a semiconductor cap layer having a sheet resistance of 100 Ω / □ or less is formed between the source electrode and the gate electrode. 3. The semiconductor device according to claim 1, wherein the length of the thin wire is shorter than the length of the gate electrode, and the thin wire exists only under the gate electrode. 4. The semiconductor device according to claim 1, wherein the length of the thin wire is the same as or longer than the length of the gate electrode.