JPH08182000A - Image coder and image coding method - Google Patents

Abstract

PURPOSE: To suppress increase in a band width while minimizing the prediction efficiency deterioration by including a picture element to generate a predict picture element used for frame prediction to a picture element used to generate a predict image used for dual prime prediction. CONSTITUTION: A predict mode discrimination selection circuit 120 selects a signal with least prediction error among signals predicted by a frame predict signal, a field predict signal and a synchronization field and a 3rd predict signal obtained by averaging signals predicted from an inverted field and applies predict coding to a block signal. A motion vector to generate the frame predict signal is converted into a vector to generate an inverted field predict signal and an object of the inverted field signal is obtained. A dual prime vector detection dmv detection circuit 20 averages the frame predict signal and part of inverted field signal objects to generate plural 3rd predict signal objects and an object with least predict error is selected as a 3rd predict signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image coding apparatus and method for coding a video signal, and more particularly to a video coding apparatus such as digital broadcasting and cable television, a recording apparatus such as a digital video disc or a video conference. The present invention relates to an apparatus and method suitable for use in an apparatus or the like.

[0002]

2. Description of the Related Art Since a video signal has an enormous amount of information when it is digitized and transmitted or stored, technical studies for compressing it are being actively conducted. ISO / IEC 13818-2 (94.11, hereinafter, MP, which was standardized by International Organization Standardization (ISO), is a typical method of multiplexing video information.
EG2 video). For details of MPEG2 video, refer to the above ISO / IECDIS 13818-2 or Yu Watanabe: “MPEG2 / H.262”, Journal of Television Society Vol.48,
No.1, pp.44-49 (1994.1), etc. have detailed explanations, so only the outline will be explained in this explanation.

Image signals currently used for broadcasting and the like are
Interlaced scanning is performed as shown in FIG. FIG.
Shows the time axis in the right direction and the vertical axis of the screen in the downward direction, and displays a part of the image. Circles in the figure indicate that an image signal, that is, a scanning line exists at a vertical screen position corresponding to a corresponding time. The processing unit of the image signal is a frame, and the dotted line portions indicated by 1 and 2 in the figure are frames. One frame is composed of two fields 3, 4 or 5, 6 and is called interlaced scanning because its vertical position is shifted by a half scanning line segment. Although various images can be handled by MPEG2 video, the above-mentioned signal in frame units is mainly used among them.

In MPEG2 video, a frame image once encoded is immediately decoded (local decoding) in the encoding device, and the same image as the image held by the decoding device is always held. When encoding the input image, the most similar part is extracted from this locally decoded image and encoded as a predicted image. Specifically, the motion-compensated inter-frame coding is performed in which the motion of the screen is detected, the motion is corrected, and then the predicted image is generated. At this time, the information on the screen movement is measured in units of 16 × 16 pixels (macroblock) of the luminance signal, and is represented by the direction and size in the screen, that is, a vector. This vector is called a motion vector.

FIG. 2 shows an example of motion-compensated inter-frame prediction of some pixels shown in FIG. The arrows in the figure show the motion vector (which corresponds to the vertical component of the actual motion vector because the figure shows only the time-vertical relationship). Although two types of prediction are illustrated in the figure, the left frame 1 represents the signal of the locally decoded image, and the right frame 2 represents the signal of the image to be encoded. The left side of the two types of prediction is frame prediction. In frame prediction, all prediction pixels are represented by one vector (frame vector). On the other hand, the right side of the two types of prediction is field prediction. In field prediction, frame signals 1 and 2 are decomposed into fields 3, 4, 5, and 6, and one vector (field vector ) Represents a prediction pixel. That is, 1
Two vectors are needed for one macroblock,
There are two 16 × 8 pixel images used for prediction. In addition to this vector information, a signal indicating from which of the first field (field 3) and the second field (field 4) the prediction is made is added.

In MPEG2 video, half-pel (half pixel) prediction is adopted in order to improve the accuracy of motion compensation. Half-pel prediction realizes motion compensation with decimal point accuracy by interpolating between pixels. FIG. 3 is an example of half-pel prediction in field prediction. In the figure, white circles are positions where pixels actually exist (full pels or integer pels), and black dots are positions of half pels. For example pixel 5
If the vector in the vertical direction is 0.5 and the field to be selected is the first field, the pixel value of the black dot P marked with “0.5” in field 3 is used for the prediction. This value is actually calculated by using the upper and lower points Q and R as follows: P = (Q + R) / 2. The diagonal line (/) indicates rounding division. The same calculation is performed at the time of the prediction from the second field or the prediction to the second field. Similarly, half pels are also defined in the horizontal direction, and in the case of both horizontal and vertical half pels, the average value of four adjacent pixels is used as a prediction pixel.

In MPEG2 video, dual prime prediction is adopted in order to further improve the prediction efficiency. FIG. 4 shows an example of dual prime prediction. In dual prime prediction, for example, when generating a prediction pixel for pixel 5 in the first field, one pixel A in the first field is generated.
Then, one pixel D in the second field is averaged to be a prediction pixel. At this time, the pixels in the second field are ± 0..0 vertically and horizontally with respect to the pixel B when the motion vector in the first field is halved (actually, an offset for interlace correction is added in the vertical direction). Pixels within 5 pixels (B, C, D in the vertical direction in the figure) can be selected.
The correction component vector within ± 0.5 pixels is “dmv”
, And is coded at the same time as the motion vector. The right side of FIG. 4 is an example of prediction pixel generation of the pixel 7 of the second field. At this time, the motion vector from the second field 4 is multiplied by 3/2 to generate a prediction vector from the first field. Also, as in the above case, pixels within ± 0.5 pixels above, below, to the left, and to the right of F of the first field of the pixel F indicated by the vector that is multiplied by 3/2 (in the figure, F in the vertical direction,
G, H) can be selected by dmv. The operation of multiplying these dual prime vectors by a constant is called scaling. Here, in the macroblock, the vector of the first field and the vector of the second field must be the same vector. In addition, dm of the vector of the first field and the vector of the second field
v must also be the same vector. That is, for one macroblock, one vector and one d
mv is encoded. Hereinafter, the signals (pixels A and E) indicated by the dual prime vector are referred to as in-phase field signals, and the signals (pixels D and H) indicated by the dual prime vector and dmv are referred to as anti-phase field signals.

When encoding an image, the vector used for each prediction described above must be calculated. FIG. 6 shows the configuration of a general image coding apparatus. In FIG. 6, it is assumed that the frame vector and the field vector are calculated externally and are input in synchronization with the encoded image via the signal line 134. The input image is input through the signal line 30. On the other hand, the memory 101 storing the locally decoded image
First, in order to calculate a vector of dual prime prediction, eight types of images are input to the buffers 104 to 111 based on the vector of the field. The vector used for input will be described in detail later. When the input of the image for dual prime is completed, the dual prime vector detection / dmv detection circuit is activated and the dual prime vector and dmv vector of 1 are output to the signal line 34. At the same time, the frame prediction image and the field prediction image are read from the memory 101 and stored in the frame prediction buffer 102 and the field prediction buffer 103, respectively. Reading from these memories is performed by the buffer control circuit. The buffer control circuit 123 sends information such as a motion vector to the memory control circuit 12 via the signal line 135.
4 and the memory control circuit 124 sends the corresponding data from the memory to the bus 130 via the address and control line 136.
Read to. At the same time, the buffer control circuit 123 takes in the image data into a predetermined buffer through the control lines 137-1 to 13-8. The frame prediction image and the field prediction image are input to the prediction mode determination selection circuit 120 together with the dual prime prediction image 36, and the most suitable prediction mode is selected. For the input image 30, a difference is calculated by the predictive coding circuit 121 using the selected predicted image 131, and the difference image is coded. Details of encoding are omitted.
The encoded code is output from 132, and at the same time, the signal 133 for local decoding is input to the local decoding circuit 122 to obtain a locally decoded image. The locally decoded image is stored in the memory 101 again via the bus 130.

FIG. 7 shows a conventional example of a dual prime vector search circuit. In FIG. 7, four dual prime prediction vector candidates are generated based on the following four field vectors, and prediction errors are calculated for each candidate vector in combination with dmv (9 ways). The smallest vector and dmv are adopted. The search circuit includes four dmv detection circuits 20-1 to 20-4 and a minimum error detection circuit 21. The dmv detection circuit 20-1 is the first
The dmv is obtained by using the prediction field vector from the field to the first field as the dual prime prediction vector (FIG. 8A). The image signal to be encoded is the signal line 30.
From the signal line 31-1, the in-phase field prediction signal (field 1, field 2 in this order) that is input by the dual prime prediction vector and dmv at the same time. 2 and the order of field 1) are input from the signal line 32-1. Also, the motion vectors of these four signals (actually two types of dual prime prediction vector and dual prime prediction vector and dmv) are input from the signal line 35-1. Similarly, the dmv detection circuit 20-2 obtains dmv by using 2/3 times the prediction field vector from the first field to the second field (with an offset for interlace correction in the vertical direction) as the dual prime prediction vector ( 8 (b)), the dmv detection circuit 20-3 uses dmv as a dual prime prediction vector by doubling the prediction field vector from the second field to the first field (with an offset for interlace correction in the vertical direction). Obtaining (FIG. 8C), dmv detection circuit 20-4
Uses dm as the prediction field vector from the second field to the second field as the dual prime prediction vector.
v is calculated (FIG. 8D).

FIG. 9 shows a detailed view of the dmv detection circuit. The input prediction signal 32 of the reverse phase field is upsampled by the horizontal interpolation circuit 50 and the vertical interpolation circuit 51 to double each in the horizontal and vertical directions. The upsampled image is
The variable delay circuits 52-1 to 52-9 delay the signals for a predetermined time.
On the other hand, the input prediction signal 31 of the in-phase field is the horizontal half-pel filter 41 and the vertical half-pel filter 41.
The half-pel processing is performed at. The half-pel filter and the interpolation circuit have almost the same configuration. In the half-pel filter, the interpolating filter is used for up-sampling and then down-sampling is performed at a predetermined phase depending on whether half-pel or not. The interpolator outputs the upsampled pixel as it is using the interpolation filter (the number of output pixels is doubled). The filtered signal is delay-corrected by the variable delay circuit 42 so as to match the delay time of the antiphase field.

FIG. 10 shows an explanation of the delay amount of the reverse phase signal.
The figure shows a state in which one field prediction image is upsampled. White circles are real pixels and black circles are interpolated pixels. The figure shows an example in which the antiphase vector (a vector obtained by scaling the dual prime vector) is an integer pel in both horizontal and vertical directions. The white circled pixel inside the dotted line is the position of the predicted pixel (16 × 8) when dmv = (0,0). The numbers assigned to the pixels are in the order of input to the variable delay circuit, and are sequentially input horizontally from the upper left pixel. At this time, the variable delay circuits 52-1 to 52-9 are respectively 37, 3 and 3.
8, 39, 73, 74, 75, 109, 110, 111
The delay amount is determined so that the signal of the pixel is output at the same time. That is, when the delay amount of the variable delay circuit 52-9 is set to 0, each of the variable delay circuits 52-1 to 52-8 has 7
Delayed by 4, 73, 72, 38, 37, 36, 2 and 1 pixel. On the other hand, the variable delay circuit 42 is also delayed so that the pixel corresponding to the 74th pixel (the first pixel of the in-phase prediction signal) is output at the timing when these 9 pixels are output, and the first pixel of the data to be further encoded. Are simultaneously input from the signal line 30. To summarize the above, at this point, the signals of the pixels shown in Table 1 below are output to the respective signal lines.

[0012] Here, a is the first pixel of the in-phase prediction, and A is the first pixel of the encoded image.

The same processing is performed when the horizontal or vertical component of the anti-phase vector (vector obtained by scaling the dual prime vector) is half pel. In these cases, the corresponding pixel (dotted line part in FIG. 7) at the time of dmv = (0, 0) is displaced by one pixel up or left, so that the delay amount is also increased by 1, 36 or 37. . These processes are performed for all the first field pixels (16 ×
8) and the second field pixel (16 × 8), there are dmv9 error values (for example, error power).
It is simultaneously output to 7-1 to 9. Minimum error detection circuit 55
Selects the smallest of these errors and outputs the information of the selection result to the signal line 33.

The above-mentioned processing is performed for four types of vectors. If this is time-division multiplexed by one circuit, N
In the example of TSC television signal (horizontal 720 pixels, 480 vertical lines, 29.97 Hz), 44.7 μs (a simple calculation of the processing time of one macroblock) must be performed. The number of pixels read out is 1296
(= 18 × 18 × 4) pixels, the number of pixels after interpolation is 5184
On the other hand, when the processing clock is 27 MHz, which is twice the sampling rate, the number of clocks for the processing time is only 667 clocks, and therefore, time division processing cannot be simply performed. Even in the case of four parallel processing as shown in FIG.
With the MHz clock, 1296 pixels (after interpolation) are processed with 667 clocks, so it is necessary to internally parallelize or speed up the processing clock.

Further, in the second conventional example, the circuit size can be reduced by obtaining the dual prime vector and dmv by using only the dmv detection circuit 20-4 shown in FIG. 7, that is, using only the vector from field 2 to field 2. The reduction and the amount of read data are attempted. Regarding the processing speed, it is the same as in the first conventional example that parallelization or an increase in processing clock speed must be achieved internally.

[0016]

The above-mentioned conventional image coding apparatus has the following problems regarding the processing speed and the amount of data (bandwidth) to access per unit time of the image memory. Regarding the processing speed, it is necessary to internally parallelize or speed up the processing clock as described above. On the other hand, regarding the bandwidth, in order to obtain one dmv, four types of in-phase predicted images and four types of anti-phase image signals must be input. All of these eight types of images must be read from the memory storing the locally decoded image, and the processing must be completed within the macroblock processing time. In normal predictive coding, the number of times the locally decoded image memory is accessed per pixel (bandwidth is proportional to the number of accesses) is 0.7 times more accurate when reading a luminance signal than when reading a luminance / color difference signal (accurate). 0.666 times), (a) reading frame prediction candidate images (for prediction mode determination: 0.7 times) (b) reading field prediction candidate images (for prediction mode determination: 0. 7 times) (c) Reading of dual field prediction candidate image (for prediction mode determination: 0.7 times) (d) Reading of prediction image (1 or 2 times) (e) Writing of decoding result (1 time) The maximum is 5.1 times. However, in actuality, the reading of the prediction image of (d) is performed only by the color difference signal (temporarily storing the images of (a), (b), and (c) used in the prediction mode determination performed before that). 0.3 times or 0.6
It can be set to 3 times), and in the end 3.7 times will be enough. On the other hand, if dmv detection is added, dmv
Increase by 5.3 times (8 times x 0.666) in detection. Of these, 0.7 times can be shared with the reading of the field prediction candidate image of the above-mentioned 2, so that the number of times increases substantially 4.6 times, and doubles to 8.3 times in total.

In the second conventional example, the bandwidth is increased by dmv 1.4 times (cannot be used together with the reading of the field prediction candidate image) for a total of 5.1 times, and the bandwidth increase is 4 times.
It will be 0%. Further, regarding the processing speed, it is the same as in the first conventional example that the processing must be parallelized or the processing clock must be speeded up internally. At this time, the coding efficiency is slightly deteriorated as compared with the case of using four vectors.

[0018]

[Object] Therefore, the present invention has a small circuit scale and a small bandwidth d without significantly deteriorating the coding efficiency.
An object is to provide an image coding device including an mv detection circuit.

[0019]

In order to achieve the above object, the present invention inputs an interlaced-scanned image signal, divides the image signal into a plurality of small blocks, and previously encodes and decodes them. Of the respective prediction signals of the frame prediction signal, the field prediction signal, the signal predicted from the in-phase field, and the third prediction signal obtained by averaging the signals predicted from the anti-phase field, which are generated from the image held as In a picture coding apparatus that selects a signal with the smallest prediction error as a prediction signal and predictively codes the block signal, a means for holding a frame prediction signal, a means for holding a field prediction signal, and a frame prediction signal , A means for converting a motion vector for generating an anti-phase field prediction signal into a vector for generating an anti-phase field prediction signal, Means for holding the anti-phase field signal candidate obtained by the signal vector, the held frame prediction signal and a part of the held anti-phase field signal candidate are averaged to generate a plurality of third prediction signal candidates. Means for selecting a candidate with the smallest prediction error from the plurality of third prediction signal candidates as a third prediction signal.

As the anti-phase field signal candidate, there may be provided means for generating a candidate signal using a vector obtained by adding a vertical offset to a vector converted from a motion vector for generating a frame prediction signal. Alternatively, an interlaced-scanned image signal is input, the image signal is divided into a plurality of small blocks, and a frame prediction signal, a field prediction signal, and an in-phase signal generated from an image that is previously encoded and decoded and held. Of the respective prediction signals of the signal predicted from the field and the third prediction signal obtained by averaging the signals predicted from the anti-phase field, the signal with the smallest prediction error is selected as the prediction signal, and the block signal is the prediction code. In the image coding method for encoding, a step for holding a frame prediction signal, a step for holding a field prediction signal, a motion vector for generating a frame prediction signal, and a step for generating an anti-phase field prediction signal. Converting into a vector, an anti-phase field signal obtained by the anti-phase field prediction signal vector , Averaging a part of the held frame prediction signal and the held reverse phase field signal candidate to generate a plurality of third prediction signal candidates, the plurality of third prediction signals Of the candidates
It is characterized by including the step of selecting the candidate with the smallest prediction error as the third prediction signal.

A step of generating a candidate signal using a vector obtained by adding a vertical offset to a vector converted from a motion vector for generating a frame prediction signal may be included as the anti-phase field signal candidate.

[0022]

Since the pixels for generating the prediction image used in the dual prime prediction include the pixels for generating the prediction image used in the frame prediction, the reading of the frame prediction candidate image described above can be omitted. Therefore, the bandwidth can be suppressed by a little less than 20% (4.4 accesses per pixel). Further, by limiting the detection of dmv in the horizontal direction, the number of pixels to be processed is halved, and there is no need to internally parallelize or speed up the processing clock, and the circuit scale can be reduced. Further, the decrease in prediction efficiency can be suppressed to the same level as in the second conventional example.

[0023]

EXAMPLE FIG. 11 shows an example of an image coding apparatus using the present invention. The part of the dual prime vector detection / dmv detection circuit 20 is a part to which the present invention is applied. By applying the present invention, the number of buffers is greatly reduced. The basic processing flow is the same as in FIG.

FIG. 12 shows the dual prime vector detection
3 shows a detailed view of the dmv detection circuit 20. FIG. dmv detection circuit 7
It is composed of only 0, and the dual prime vector is generated from the frame vector. Since the counting method in the vertical direction is different from the frame vector and the dual prime vector (field vector), the frame vector (Vfx, Vdy) of the dual prime vector (Vdx, Vdy)
The calculation from fy) is as follows.

Vdx = Vfx ... Vdy = DIV (Vfy, 2, 0.5) .. Here, “DIV (a, b, c)” means that the result of a / b is rounded down to the 0 direction with the precision of c. Indicates. Dmv in FIG.
The detailed view of the detection circuit 70 is shown. The eleventh basic configuration is almost the same as in FIG. The different points are that the horizontal interpolation of the image of the anti-phase field is a horizontal half-pel filter, and that there are three prediction value generation circuits and error measurement circuits. The output phase of the horizontal half-pel filter of the anti-phase field signal is the same as the output phase of the in-phase field. That is, the x component of dmv is limited to 0. As a result, the signals input to the variable delay circuits 52-1 to 52-3 are halved as compared with the prior art, as shown in FIG. 14
In, white circles are pixels after half-pel processing. Black circles represent pixels generated by the interpolation operation. The delay amounts of the variable delay circuits 52-1 to 52-3 are 32, 16, and 0 when the vertical component of the antiphase field vector is an integer pel, respectively, and 48, 32 when the vertical component of the antiphase field vector is a half pel, respectively. It will be 16. Hereinafter, as in the case of FIG. 8, the prediction error for each dmv is calculated,
The minimum error detection circuit 73 calculates dmv that minimizes the error. In the circuits of FIGS. 12 and 13 using the present invention, the circuit scale is one-eighth or less, the processing speed is half, and the bandwidth is about half, as compared with the circuits of FIGS. Also, compared with the second conventional example, the circuit scale is about half, the processing speed is half, and the bandwidth is also reduced by 15%. On the other hand, as a result of the simulation experiment, the prediction efficiency is suppressed to a slight decrease as compared with FIGS. 7 and 9. For example MPEG2 v
In SP @ ML mode, which is a typical encoding mode of video, the signal-to-noise ratio (average S / N ratio) of the average noise of the luminance signal when encoding 150 frames of 4 Mbit / s NTSC signal is It is as shown in Table 2 below. (Below margin)

[0026] It can be seen from Table 2 that the effect of dual prime is suppressed by a decrease of 17% in the increase of the S / N ratio as compared with the conventional example and by about 6% as compared with the conventional example.

FIG. 15 shows the second embodiment of FIG. In FIG. 15, the vertical half-pel filter is omitted by limiting the vertical component of the dual prime vector to integer pels to reduce the circuit scale. Vdx = Vfx ... Vdy = DIV (Vfy, 2, 1.0) ... The prediction efficiency (S / N at the time of code) of the first modified example is shown in Table 3 below.
Shown in

[0028] FIG. 16 shows the third embodiment of FIG. This uses the statistical feature that the vertical component of the dual prime vector when the dual prime prediction is selected is close to 0, and that the vertical component of dmv at this time is small (+1 or -1). are doing. Dmv when Vdy = 0
In the case of y = + 1 and dmvy = -1, the vertical direction indicates integer pels. Therefore, the vertical interpolation processing of the negative phase field signal becomes unnecessary. At the same time, when Vdy is not other than 0, the signal line 79 is controlled to output a signal such that dual prime is not selected. The prediction efficiency (S / N when coded) of the first modified example is as shown in Table 4 below.
The efficiency is slightly lower than the other examples.

[0029] It is obvious that the following modifications are included in the present invention with respect to the above-described embodiments, the second embodiment, and the third embodiment.

In the methods shown in the embodiments, the second embodiment and the third embodiment, the detection of dmv is limited to the vertical direction only, but all nine vertical and horizontal points may be searched. Also d
A point of mv = (0,0) and a total of 5 points above, below, left and right thereof may be searched. In both cases, the prediction efficiency is slightly improved. When searching for dmv, the search may be performed by determining whether the pixel is an integer pel. For example, the search points may be adaptively switched depending on the magnitude of the vertical component of the frame vector. That is, when the vertical component is close to 0, it is estimated that the resolution is high due to the motion in the still or horizontal direction, and therefore only the search for dmv in which the integer pel is selected is performed. When the vertical component is large, it is estimated that the motion is large and the resolution is lowered. Therefore, only dmv for which half pel is selected is searched.

The methods shown in the embodiments, the second embodiment and the third embodiment can be applied to the case where the encoding is performed by software. Since parallel processing becomes difficult in software processing, the effect of reducing the processing amount according to the present invention is particularly great. The methods shown in the embodiment, the second embodiment, and the third embodiment are effective even when combined with the method of the conventional example. For example, the dmv is calculated for two types of the dual prime vector generated based on the frame vector and the dual prime vector generated based on the field vector of the second field → second field, and the one having a smaller prediction error is selected. Is also possible. In this case, the circuit scale and the bandwidth are slightly increased, but the coding efficiency is also improved. Note that the bandwidth is variable during a series of image encoding processes, and when there is a margin in the bandwidth, calculation is performed from multiple dual prime vectors. By performing the method shown, the coding efficiency is improved on average.

The present invention can be combined with a motion vector detection circuit. After obtaining the frame vector and the field vector by the conventional method, the present method is used to obtain the dual prime vector and the dmv or backward prediction vector for bidirectional prediction. In the motion vector detection circuit, the bandwidth of the image memory is very large, but by using this method, the dual prime vector and dmv or backward prediction vector for bidirectional prediction can be obtained without increasing the bandwidth so much.

[0033]

According to the present invention, it is possible to suppress an increase in bandwidth while minimizing a decrease in prediction efficiency.
Further, it is not necessary to internally parallelize or speed up the processing clock, and the circuit scale can be reduced.

[Brief description of drawings]

FIG. 1 is a diagram illustrating a configuration of an interlaced image signal.

FIG. 2 is a diagram illustrating frame prediction and field prediction.

FIG. 3 is a diagram illustrating half-pel prediction of field prediction.

FIG. 4 is a diagram illustrating vertical dual-prediction prediction.

FIG. 5 is a diagram for explaining horizontal dual-prime prediction.

FIG. 6 is a configuration diagram of a conventional image encoding device.

FIG. 7: Dual prime vector detection / dmv of FIG.
It is a detailed view of a detection circuit.

8 is a diagram illustrating the dual prime vector of FIG. 7. FIG.

9 is a detailed diagram of the dmv detection circuit of FIG.

FIG. 10 is a timing diagram of the processed pixel of FIG.

FIG. 11 is a configuration diagram of an image encoding device using the present invention.

FIG. 12 is a detailed diagram of a dual prime vector detection / dmv detection circuit using the present invention.

FIG. 13 is a detailed diagram of a dmv detection circuit using the present invention.

FIG. 14 is a timing diagram of processing pixels of FIG.

FIG. 15 is a configuration diagram of a second embodiment of a dmv detection circuit using the present invention.

FIG. 16 is a configuration diagram of a third embodiment of a dmv detection circuit using the present invention.

[Explanation of symbols]

 1: Frame signal 2: First field signal 3: Second field signal 10: Dual prime vector detection / dmv detection circuit 20, 70: dmv detection circuit 30: Encoded image signal 31: In-phase field prediction signal 32: In-phase field Prediction signal 35: Vector information 40: Horizontal half-pel filter 41: Vertical half-pel filter 42, 52: Variable delay circuit 50: Horizontal interpolation circuit 51: Vertical interpolation circuit 53: Prediction value generation circuit 54: Error measurement circuit 101: Local decoding Image memory 121: Predictive coding circuit 122: Local decoding circuit

Claims (4)

[Claims] 1. A frame prediction signal and field prediction generated by inputting an interlaced-scanned image signal, dividing the image signal into a plurality of small blocks, and encoding and decoding the image previously stored. The signal having the smallest prediction error is selected as the prediction signal from among the prediction signals of the signal, the signal predicted from the in-phase field, and the third prediction signal obtained by averaging the signals predicted from the in-phase field, and the block signal In a picture coding apparatus for predictively coding a frame prediction signal, a means for holding a frame prediction signal, a means for holding a field prediction signal, a motion vector for generating a frame prediction signal, and an anti-phase field prediction signal. Means for converting into a vector for storing the anti-phase field signal candidate obtained by the anti-phase field prediction signal vector. Means for generating a plurality of third predicted signal candidates by averaging a part of the held frame prediction signal and the held reverse phase field signal candidates, and a means for generating a plurality of third predicted signal candidates. An image coding apparatus, characterized by comprising means for selecting a candidate having the smallest prediction error as a third prediction signal. 2. A means for generating a candidate signal using a vector obtained by adding an offset in the vertical direction to a vector converted from a motion vector for generating a frame prediction signal as an anti-phase field signal candidate. The image coding apparatus according to claim 1. 3. A frame prediction signal and field prediction generated by inputting an interlaced-scanned image signal, dividing the image signal into a plurality of small blocks, and encoding and decoding the image previously stored. The signal having the smallest prediction error is selected as the prediction signal from among the prediction signals of the signal, the signal predicted from the in-phase field, and the third prediction signal obtained by averaging the signals predicted from the in-phase field, and the block signal In the image coding method of predictively coding, a step for holding a frame prediction signal,
A step for holding a field prediction signal, a step for converting a motion vector for generating a frame prediction signal into a vector for generating an antiphase field prediction signal, and an antiphase obtained by the antiphase field prediction signal vector Holding a field signal candidate, averaging a part of the held frame prediction signal and the held negative phase field signal candidate to generate a plurality of third predicted signal candidates, and the plurality of third predicted signal candidates. Of the prediction signal candidates of, the step of selecting a candidate with the smallest prediction error as the third prediction signal. 4. A step of generating a candidate signal using a vector obtained by adding a vertical offset to a vector converted from a motion vector for generating a frame prediction signal, as a negative-phase field signal candidate. The image coding method according to claim 3.