JPH0818354A - Operational amplifier - Google Patents

Abstract

PURPOSE:To provide the operational amplifier which has a performance superior in linearity and has a wide in-phase input signal range. CONSTITUTION:The operational amplifier has first an second differential amplification parts 1 and 2 which are operated by a power source VDD o the positive side or a power source VSS on the negative side. The current value of the first differential amplification part 1 is measured by a current measuring circuit 4 having the same constitution as the first differential amplification part 1, and the output of this circuit 4 is subtracted from a preliminarily determined current value by a current subtraction circuit 5. The output current value of the current subtraction circuit 5 and the current value of the current source of the second differential amplification part 2 are equalized, thereby operating only one of two differential amplification parts 1 and 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an operational amplifier capable of operating a common-mode signal level from a positive power supply voltage to a negative power supply voltage.

[0002]

BACKGROUND OF THE INVENTION Operational amplifiers are widely used in analog circuits, and the performance of operational amplifiers is so important that the performance of operational amplifiers dominates the performance of analog circuits. In recent years, electronic devices have been reduced in size, and at the same time, analog circuits have been required to operate at low voltage assuming the use of batteries. When the analog circuit is operated at a low voltage, the signal level that can be processed is inevitably lowered and the S / N characteristic is impaired. Therefore, in order to keep the signal processing voltage range as wide as possible with respect to the operational amplifier, the wider the common mode input signal level is, the more preferable. If the common mode input signal range can operate up to the positive and negative power supplies, respectively. It can be said that it is the most preferable. However, in the conventional amplifier, such an operational amplifier is difficult to design, and a preferable amplifier cannot be provided.

FIG. 4 shows an example of a conventional operational amplifier having a large common mode input signal range. Where 131 is the NMO
1st differential amplification part which made SFET the input transistor, 1
Reference numeral 32 is a second differential amplifier section using a PMOSFET as an input transistor, and 133 is a signal combining circuit that combines the signals of the first differential amplifier section 131 and the second differential amplifier section 132 and sums them. According to the conventional circuit shown in FIG. 4, when the in-phase input signal is near V _DD , the NMOSFET is used as the input MOSFET.
The first differential amplification unit 131 having T operates. When the in-phase input signal is near V _SS , the PMOSFET is input M
The second differential amplifying unit 132, which is an OSFET, operates, and the first differential amplifying unit 1 is further activated near the middle of V _SS and V _DD.
31 and the second differential amplifier 132 operate. Therefore, the conventional operational amplifier shown in FIG. 4 can operate over all in-phase signals.

[0004]

For this operational amplifier, it is necessary to design two types of first and second differential amplifiers 131 and 132. Therefore, there is a problem that it takes time to design.

Further, when the output section is constructed as in the conventional circuit shown in FIG. 4, when the in-phase input signal is divided into near V _DD, near the center and near V _SS as shown in FIG. The current values flowing in the load MOSFETs 151 and 152 near V _DD are I ₃ −I ₂ , I ₃ near the center, and I ₃ + I ₁ with V _SS , and the current values flowing in the load MOSFETs 151 and 152 for each region to. The fluctuation of is large. For this reason, the output operating point depends on the in-phase input level and the load MO is changed as shown in FIG.
There is a problem that the current fluctuates according to the amount of current flowing through the SFET, resulting in distortion in the input / output characteristics.

Further, the currents flowing in cascode MOSFETs 147 and 148 vary with respect to the in-phase input signal level. Due to this, the pole position of the transfer function in the operational amplifier fluctuates with respect to the in-phase signal level, so that there is a drawback that the current value and the speed are limited due to the design for maintaining the phase margin.

As another conventional example, M.K. D. PAR
IEEE JOURNA described by DOEN et al.
L OF SOLID STATE CIRCUITS
VOL. 25, NO. 2, there is a circuit example of an APRIL 1990 rail operational amplifier. But this circuit
The distortion is slightly improved by avoiding the input MOSFET pair of one of the differential amplifiers from being suddenly turned off, but the problem is not essentially solved.

An object of the present invention is to provide an operational amplifier having a large in-phase input signal range and having excellent linearity.

[0009]

In order to achieve such an object, the invention of claim 1 is, in an operational amplifier using a MOSFET, having an input MOSFET pair for amplifying at least an input signal and a current source. A first differential amplifier circuit,
A second differential amplifier circuit having at least an input MOSFET pair for amplifying an input signal and a current source, a signal combining circuit for combining the outputs of the first differential amplifier circuit and the second differential amplifier circuit, and a load MOSFET A current measurement circuit configured to have the same configuration as the first differential amplification circuit except that the gate and the drain of the first differential amplification circuit are connected to each other, and the current measurement circuit measures the current value of the input MOSFET pair of the first differential amplification circuit; A subtraction circuit for subtracting the output of the current measurement circuit from the obtained current value, wherein the output current value of the subtraction circuit and the current value of the current source of the second differential amplifier circuit are proportional. It is a characteristic operational amplifier.

According to a second aspect of the present invention, the MOSFET constituting the first differential amplifier circuit and the MOSFET constituting the second differential amplifier circuit have the same polarity, and the input MOSFET pair of the second differential amplifier circuit is 2. The operational amplifier according to claim 1, wherein an input signal is input to the gate via a level shifter circuit.

According to a third aspect of the present invention, a MOSFET forming the first differential amplifier circuit and a MOS forming the second differential amplifier circuit.
2. The operational amplifier according to claim 1, wherein the FET has the same polarity, and the input MOSFET pair of the second differential amplifier circuit is a depletion type.

According to a fourth aspect of the present invention, a MOSFET forming the first differential amplifier circuit and a MOS forming the second differential amplifier circuit.
The operational amplifier according to claim 1, wherein the FET and the FET have different polarities.

[0013]

The operational amplifier of the present invention has two differential amplifying sections which are operated by the positive power source V _DD or the negative power source V _SS , and these two amplifiers are operated by the current measuring circuit and the current subtracting circuit. Only one of the two differential amplifiers is operating. Also, when the operation shifts from one differential amplifier to the other, it does not turn on / off suddenly, but for a short period, the constant current source gradually decreases from the original current value to zero, The other gradually increases from zero to reach the original current value, and the sum of these current values is always kept constant. That is, since the current flowing through the load MOSFET on the signal combining circuit side is always constant, the output voltage does not change at all with respect to the input common-mode signal, and an operational amplifier with excellent linear performance in input / output characteristics is provided. it can.

[0014]

Embodiments of the present invention will be described below with reference to the drawings.

An embodiment of the present invention is shown in FIG. In FIG. 1, reference numeral 1 denotes a normally used first differential amplifier section composed of input MOSFETs 10 and 11 and a constant current source 14, and 2
Is connected to the input terminal pair of the differential amplifier having the same configuration as the first differential amplifier 1 and the output terminals of the level followers 6 and 7 of the source follower configuration are connected, and the input signal is differentially transmitted through the level shifters 6 and 7. The second differential amplifier is transmitted to the input MOSFETs 19 and 20 of the amplifier, and 3 is a signal combining circuit that combines the signals of the first and second differential amplifiers 1 and 2. 4 is a first differential amplifier 1 and a load MOSF
The current measurement circuit has exactly the same configuration except that the gates and drains of 32 and 33 corresponding to the ET pair are connected. Reference numeral 5 is a current subtraction circuit that can obtain a current value obtained by subtracting the current value flowing through the load MOSFET pairs 32 and 33 of the current measurement circuit 4 from the constant bias current value. Current value and input MOSFETs 19 and 2 of the second differential amplifier 2
The current value flowing to 0 is the same.

The operation of the embodiment of the present invention shown in FIG. 1 will be described. First, when the in-phase input signal is in the vicinity of the midpoint between V _DD and V _SS , the first differential amplification section 1 operates normally.
At this time, in the current measurement circuit 4 configured by the same circuit as the first differential amplifier 1, the sum of the currents flowing through the load MOSFET pairs 32 and 33 is the MOSFETs 30 and 3.
Since 1 is within the normal operating range, it is equal to the current flowing through the MOSFET 34 used as a current source. Also,
Since the MOSFETs 35 and 36 of the current subtraction circuit 5 form a current mirror circuit with the MOSFETs 32 and 33 of the current measuring circuit 4, the MOSFETs 35 and 36.
The sum of the currents flowing through the MOSFETs is also equal to the current flowing through the MOSFET 34. In the current subtraction circuit 5, MOSFE
The current flowing through T38 has a value obtained by subtracting the current flowing through MOSFETs 35 and 36 from the current flowing through MOSFET 37. Since the bias voltage applied to the bias terminals B ₁ and B ₂ is adjusted so that the current flowing through the MOSFET 37 of the current subtraction circuit 5 is the same as the current flowing through the MOSFET 34 of the current measuring circuit 4, no current flows through the MOSFET 38. , No current flows through MOSFET 39, which is a current mirror circuit for MOSFET 38. As a result, no current flows through the MOSFET 40 and the second differential amplification section 23 that is a current mirror circuit with the MOSFET 40, and the second differential amplification section 2 does not operate.

Next, the case where the in-phase input signal is near V _DD will be described. Even when the in-phase input signal is near V _DD , the MOSFET that is the input element of the first differential amplifier 1
Bias terminal B so that 10 and 11 are in the saturation region
The first differential amplifier 1 operates normally by adjusting the bias voltage applied to ₃ . Therefore, the second differential amplifier 2 does not operate as in the case where the in-phase input signal is near the midpoint between V _DD and V _SS .

A case where the in-phase input signal is near V _SS will be described. When the in-phase input signal is near V _SS ,
The MOSFETs 10 and 11 which are the input elements of the first differential amplifier 1 are turned off because a sufficient gate-source voltage cannot be obtained. At this time, in the current measurement circuit 4 configured by the same circuit as the first differential amplifier 1, the load MOSF
The sum of the currents flowing in the ET pair 32 and 33 is
Since T30 and 31 are turned off as in the differential amplifier unit 1,
It becomes zero. Further, since the MOSFETs 35 and 36 of the current subtraction circuit 5 form a current mirror circuit with the MOSFETs 32 and 33 of the current measurement circuit 4, the MOSFETs
The sum of the currents flowing through T35 and 36 is also
It becomes zero like the current flowing through T34. In the current subtraction circuit 5, the current flowing through the MOSFET 38 is
From the current flowing through the FET 37 to the MOSFETs 35 and 3
It is the value obtained by subtracting the current flowing in 6. Since a current determined by the bias voltage applied to the bias terminal B ₂ flows through the MOSFET 37, as a result, the MOSFET 3
MOSFET3 that is a current mirror circuit for 8
The same current as that of the MOSFET 37 also flows through 9. Therefore, the same current flows through the MOSFET 40 and the MOSFET 23 of the second differential amplification section 2 which is a current mirror circuit with the MOSFET 40. Here, due to the functions of the level shifters 6 and 7 in the second differential amplification section 2, the input signal is MOSFE.
The levels of T19 and T20 are level-shifted to the normal operation level, and the second differential amplification section 2 performs the normal operation in the same manner as the differential amplification section 1 in the normal operation.

As described above, the operational amplifier of the present invention has the first and second differential amplifying units 1 and 2 which are operated by the positive power source V _DD or the negative power source V _SS , and measures the current. Due to the circuit 4 and the current subtraction circuit 5, only one of these two differential amplifiers is operating. Also, when the operation shifts from one differential amplifier to the other, it does not turn on / off suddenly, but for a short period, the constant current source gradually decreases from the original current value to zero, The other gradually increases from zero to reach the original current value, and the sum of these current values is always kept constant. That is, since the currents flowing through the load MOSFETs 24 and 25 of the signal synthesizing circuit 3 are always constant, the output voltage does not change at all with respect to the input common-mode signal, and the operational amplifier having excellent linear performance in input / output characteristics. Can be provided.

Also, since the currents flowing in the cascade MOSFETs 26 and 27 are always constant, the pole position of the transfer function due to the cascade MOSFET does not change with respect to the in-phase input signal, and a high-speed operational amplifier is designed. This is also preferable.

In the embodiment shown in FIG. 1, the differential amplifier of the current measuring circuit 4 has been described as being the same as the first differential amplifier 1, but in reality the chip size and current consumption are saved. Therefore, only the size of the MOSFET may be reduced at a constant ratio while the circuit configuration remains the same. Similarly,
Current mirror circuit (MOSFET) in the current subtraction circuit 5
35, 36, 39), for the same reason, the size can be reduced at a constant rate to reduce the current consumption. Moreover, since the accuracy of the current mirror circuit is not accurate, the current becomes insufficient due to the mismatch of the current mirror circuit during the transient period when the operation is switched from the first differential amplifying unit 1 to the second differential amplifying unit 2. In some cases, there may be a problem that the operation is not performed or the operation is deteriorated. In order to avoid this problem, the current of the MOSFET 37 of the current subtraction circuit 5 may be set higher so that a small amount of current may flow in advance on the second differential amplifier 2 side.

In the embodiment shown in FIG. 1, the level shifter 6
Although the source follower circuit is used for 7 and 7, for example, an emitter follower using a bipolar circuit may be used as long as the input signal can be shifted by a desired amount.

In the embodiment shown in FIG. 1, the NMOS is
Although it is explained that it is composed of FET, PMOSF
Even in the case of ET, it is obvious that the same effect can be obtained by designing based on a similar method.

The level shifters 6 and 7 may not be used. In the embodiment shown in FIG. 1, a depletion-type NMOSFET is used as the input MOSFET so that the input MOSFET pair 19 and 20 of the second differential amplifier 2 can operate even when the input is V _SS . Obviously, with such a configuration, the operation is similar to that of the embodiment shown in FIG. 1 without the level shifter.

FIG. 2 shows another embodiment of the present invention. In FIG. 2, reference numeral 41 is a normally used first differential amplification section including input MOSFETs 50 and 51 and a constant current source 54, and 42 is a MOSFE having a polarity different from that of the first differential amplification section 1.
T, input PMOSFETs 55 and 56 in this example to M
A second differential amplifier used as the OSFET, and 43 is a signal combining circuit that combines the signals of the first and second differential amplifiers 41 and 42. 44 is a first differential amplifier 41
And the load MOSFET pairs 72 and 73 are connected between their gates and drains, the current measuring circuit has exactly the same configuration. 45 is a constant bias current value. In the current subtraction circuit that obtains the current value obtained by subtracting the current value flowing through the current value obtained by the current subtraction circuit 45, and the current value flowing through the input MOSFETs 55 and 56 of the second differential amplifier 42. And are used in the same way.

The operation of the embodiment shown in FIG. 2 will be described. First, when the in-phase input signal is near the midpoint between V _DD and V _SS , the first differential amplification section 41 operates normally. This time,
In the current measurement circuit 44 configured by the same circuit as the first differential amplifier 41, the load MOSFET pairs 72 and 73
The sum of the currents flowing through is equal to the current flowing through MOSFET 74, which is used as a current source, because MOSFETs 70 and 71 are in the normal operating range. In the current subtraction circuit 45, the MOSFETs 75 and 76 form a current mirror circuit with the MOSFETs 72 and 73 of the current measurement circuit 44, and therefore the MOSFETs 75 and 76.
The sum of the currents flowing through the
It is equal to the current flowing through ET74. Where MOSF
The current flowing through the ET 78 is a value obtained by subtracting the current flowing through the MOSFETs 75 and 76 from the current flowing through the MOSFET 77. When the bias voltage applied to the bias terminals B ₁ and B ₂ is adjusted so that the current flowing through the MOSFET 77 and the current flowing through the MOSFET 74 of the current measuring circuit 44 are the same, no current flows through the MOSFET 78.
Therefore, no current flows in the MOSFET 59 of the second differential amplification section 42 which is a current mirror circuit for the MOSFET 78, and as a result, the second differential amplification section 42 does not operate.

Next, the case where the in-phase input signal is near V _DD will be described. Even when the in-phase input signal is in the vicinity of V _DD, the bias voltage applied to the bias terminal B ₃ is adjusted so that the MOSFETs 50 and 51, which are input elements, enter the saturation region. It works normally. Therefore, the second differential amplifier 42 does not operate in the same manner as before.

A case where the in-phase input signal is near V _SS will be described. When the in-phase input signal is near V _SS ,
MOSFET 50 which is an input element of the first differential amplifier 41
And 51 are turned off because a sufficient gate-source voltage cannot be obtained. At this time, in the current measuring circuit 44 configured the same as the first differential amplifier 41, the load MO
The sum of the currents flowing through the SFET pairs 72 and 73 is
Since the FETs 70 and 71 are turned off similarly to the first differential amplification section 41, they become zero. Further, in the current subtraction circuit 45, the MOSFETs 75 and 76 form a current mirror circuit with the MOSFETs 72 and 73.
The sum of the currents flowing through the FETs 75 and 76 is also the MOSF.
It becomes zero like the current flowing through the ET74. Where M
The current flowing through the OSFET 78 is a value obtained by subtracting the current flowing through the MOSFETs 75 and 76 from the current flowing through the MOSFET 77. Here, since a current determined by the voltage applied to the bias terminal B2 flows through the MOSFET 77, a current having the same value as the current flowing through the MOSFET 77 also flows through the MOSFET 78. As a result, MOSF
A current having the same value as that of the MOSFET 77 also flows through the MOSFET 59 of the second differential amplification section which is a current mirror circuit with respect to the ET 78. The second differential amplifier 42 is an input MOS
Since the FET is a PMOSFET, it can operate normally even with a signal in the vicinity of V _SS , and therefore operates exactly the same as the first differential amplification section 41 during normal operation. That is, FIG.
The same result as in FIG.

When the operational amplifier of the present invention is used, in order to further improve the performance of the operational amplifier circuit, an output amplifier circuit may be added as shown in FIG.

In FIG. 3, reference numeral 123 is a first differential amplifier,
Reference numeral 124 is a second differential amplifier, 125 is a signal combining circuit for combining the signals of the first and second differential amplifiers 123 and 124, 126 is a current measuring circuit, 127 is a current subtracting circuit, and 128 and 129 are It is a level shifter. The configurations and operations of these circuits are the same as those of the operational amplifier shown in FIG. 118 is an output amplifier circuit,
It is connected to the output of the signal synthesis circuit 125.

Now, the output amplifier circuit 118 includes the current source 11
9 and MOSFET 120. In the output amplifier circuit 118, the resistor 121 and the capacitor 122 are inserted in order to maintain a sufficient phase margin. By adding the output amplifier circuit 118, the output signal amplification and the output current capability can be improved.

[0032]

As described above, in the operational amplifier of the present invention, the common-mode signal range extends from the negative power supply to the positive power supply by the current measuring circuit and the current subtracting circuit having the same configuration as one of the operational amplifiers. It is possible to provide an operational amplifier having a linear characteristic with very little distortion.

Further, since the pole position of the transfer function of the operational amplifier is constant regardless of the in-phase input signal range, it is possible to design the circuit at high speed.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an operational amplifier that is an embodiment of the present invention.

FIG. 2 is a circuit diagram of an operational amplifier according to another embodiment of the present invention.

FIG. 3 is a circuit diagram of an operational amplifier of the present invention to which an output amplifier circuit is added.

FIG. 4 is a circuit diagram of a conventional operational amplifier.

FIG. 5 is a graph showing input / output characteristics of a conventional operational amplifier.

[Explanation of symbols]

 1 1st differential amplification part 2 1st differential amplification part 3 signal combination circuit 4 current measurement circuit 5 current subtraction circuit 6, 7 level shifter 41 1st differential amplification part 42 2nd differential amplification part 43 signal combination circuit 44 Current measurement circuit 45 Current subtraction circuit 118 Output amplification circuit 123 First differential amplification section 124 Second differential amplification section 125 Signal synthesis circuit 126 Current measurement circuit 127 Current subtraction circuit 128,129 Level shifter 131 First differential amplification section 132 second differential amplifier 133 signal combining circuit

Claims (4)

[Claims] 1. An operational amplifier using a MOSFET, wherein a first differential amplifier circuit having at least an input MOSFET pair for amplifying an input signal and a current source, and at least an input MOSFET pair for amplifying an input signal and a current. Except that a second differential amplifier circuit having a source, a signal combining circuit for combining the outputs of the first differential amplifier circuit and the second differential amplifier circuit, and a gate and a drain of the load MOSFET are connected to each other. A current measuring circuit configured to be the same as the first differential amplifier circuit and measuring the current value of the input MOSFET pair of the first differential amplifier circuit; and subtracting the output of the current measuring circuit from a predetermined current value. An operational amplifier comprising: a subtraction circuit, wherein an output current value of the subtraction circuit and a current value of a current source of the second differential amplifier circuit are proportional to each other. 2. A MOS that constitutes the first differential amplifier circuit.
The FET and the MOSFET forming the second differential amplifier circuit have the same polarity, and the input MOSFET of the second differential amplifier circuit
The operational amplifier according to claim 1, wherein an input signal is input to the pair of gates via a level shifter circuit. 3. A MOS forming the first differential amplifier circuit.
The FET and the MOSFET constituting the second differential amplifier circuit have the same polarity, and the input MOSF of the second differential amplifier circuit is
The operational amplifier according to claim 1, wherein the ET pair is a depletion type. 4. A MOS constituting the first differential amplifier circuit.
The operational amplifier according to claim 1, wherein the FET and the MOSFET forming the second differential amplifier circuit have different polarities.