JPH0818448A - Control circuit for phase-synchronous frequency synthesizer - Google Patents

Abstract

(57) [Abstract] [Purpose] A control circuit used for constructing a phase-locked frequency synthesizer, capable of intermittent operation including a voltage-controlled oscillator, regardless of the off-time and the time constant of the loop filter. An object of the present invention is to provide a control circuit for realizing a phase-locked frequency synthesizer capable of stable and stable rising. [Structure] A voltage (Vcc / Vcc) corresponding to the central value of the range (0 to Vcc) of the control signal output by the loop filter 28.
2) is generated in the voltage supply unit 38, and the switches 30 and 32 are made non-conductive at the rising of the intermittent operation, that is, while the VCO on / off control signal is at H level and the PLL on / off control signal is at L level. By doing so, the output of the charge pump 26 is set to a floating level, the analog switch 36 is turned on, and a fixed voltage of Vcc / 2 is supplied to the loop filter 28.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control circuit used to construct a phase locked frequency synthesizer.

[0002]

2. Description of the Related Art A frequency synthesizer changes the frequency division ratio of a variable frequency divider provided in a PLL (phase locked loop) to make an output frequency f _{out a} desired frequency at a reference frequency interval. It is widely used as a local oscillator of a radio device having a variable transmission / reception frequency (for example, a radio device used for mobile communication such as a car phone, a personal radio, a cordless phone) or an electronic device such as an electronic tuning radio.

FIG. 7 shows, as an example of the phase-locking frequency synthesizer, a phase-locking frequency synthesizer employing a pulse swallow type variable frequency divider. In FIG. 7, a well-known pulse swallow-type variable frequency divider is configured by the prescaler 10 and the variable frequency dividers 12, 14 whose frequency division ratio is switched to P or P + 1 according to a control signal. When the frequency division ratios set in the variable frequency dividers 12 and 14 from the control circuit 16 are A and N, respectively, the overall frequency division ratio is P · N + A.
Is represented by

A signal having a reference frequency f _{r obtained} by _dividing the output f _ref of the reference crystal oscillator 18 by the frequency divider 20 into 1 / M is input to one input of the phase comparator 22. Also,
The output of the voltage controlled oscillator 24 in the high frequency band whose oscillation frequency is determined by the control voltage is divided by the above-mentioned pulse swallow frequency divider and the divided output f _v is input to the other input of the phase comparator 22. Perform phase comparison. The phase comparison result is converted into a level of three states including floating by the charge pump 26, and time-integrated by the loop filter 28 having a low-pass characteristic including a resistor and a capacitor, and an integrated voltage is output. The integrated voltage output from the loop filter 28 is given to the voltage controlled oscillator 24 as its control voltage, and its oscillation frequency is changed to change the phase of the divided output f _{v obtained} by dividing the oscillation output frequency of the voltage controlled oscillator 24. Then, loop control is performed until there is no phase error output from the phase comparator 22. The output f _out of the voltage controlled oscillator 24 at this time becomes the output of the local oscillator.

As described above, since the frequency synthesizer requires complicated operation, it consumes a large amount of current, which increases the current consumption of the entire device. Therefore, many wireless devices adopt an intermittent reception method in which the power is turned off except when it is necessary, such as during reception, and the frequency synthesizer also requires intermittent operation, and various types of intermittent operation methods have been announced. .

For example, Japanese Patent Laid-Open Publication No. 56-136037 discloses, as a first prior art, voltage control by interlocking a switch for turning on / off a power source of circuits other than a voltage controlled oscillator and a switch for interrupting a signal to a loop filter. A phase-locked oscillator that intermittently operates circuits other than the oscillator is disclosed. In addition, Japanese Patent Laid-Open No. 60-140030 discloses a second method.
In the prior art, in order to operate intermittently including the voltage controlled oscillator whose operation at start-up is unstable, the input of the loop filter is set to the floating level immediately before the operation is stopped and the last control voltage is held in the loop filter. By doing so, an intermittent oscillation frequency synthesizer circuit that stabilizes the operation of the voltage controlled oscillator when the operation is restarted is disclosed.

[0007]

In the above-mentioned first prior art, the power supply of the voltage controlled oscillator is not turned off even when the operation is stopped, so that there is a limit to the reduction of power consumption. Further, in the second conventional technique, problems occur when the operation is stopped for a long time and when the time constant of the loop filter is short.

When the off time is short, the discharge of the capacitor in the loop filter does not need to be considered so much, but when the off time is long, the discharge becomes large and the frequency shift at the time of intermittent rising is large. This increases the intermittent rise time. Further, in the current system, it is generally necessary to shorten the frequency switching time. Therefore, as a method for operating the frequency synthesizer at high speed, there is a tendency to reduce the time constant τ of the loop filter to increase the speed. This can be easily achieved by reducing the capacitance of the loop filter capacitor, but this also causes a further increase in discharge during open loop.

Therefore, an object of the present invention is to realize a phase-locked frequency synthesizer capable of intermittent operation including a voltage-controlled oscillator and capable of stable rising regardless of the length of the off time and the time constant of the loop filter. It is to provide a control circuit for.

[0010]

According to the present invention, a control signal generating circuit for comparing the phase of a controlled signal from a voltage controlled oscillator with the phase of a reference signal and generating a frequency control signal according to the comparison result. And a loop filter that generates a control voltage of the voltage controlled oscillator from the control signal output by the control signal generation circuit, and an output of the control signal generation circuit within a predetermined period immediately after power is supplied to the voltage controlled oscillator. And a loop open / close control circuit for performing open loop control, and a fixed voltage such that the control voltage output by the loop filter is substantially at the center of the control range at least within the predetermined period. A control circuit for a phase-locked frequency synthesizer, comprising a fixed voltage supply circuit for supplying to a filter.

[0011]

Since a fixed voltage is applied to the loop filter and a central value of the control range is output from the loop filter within a predetermined period immediately after the power supply to the voltage controlled oscillator is turned on,
Stable operation is realized regardless of the length of the off time and the time constant of the loop filter.

[0012]

1 shows a part of the construction of a phase-locked frequency synthesizer including a control circuit according to the present invention. The same components as those in FIG. 7 are designated by the same reference numerals. Also,
The frequency dividers 10, 12, 14, 20 shown in FIG. 7, the control circuit 16, and the crystal oscillator 18 are omitted.

The switch 30 is provided between the frequency divider 20 (FIG. 7) and the phase comparator 22, and the switch 32 is provided between the frequency divider 14 (FIG. 7) and the phase comparator 22. P
When the LL on / off control signal becomes L level, the switch 3
0 and 32 are turned off, and the signal f from the frequency dividers 20 and 14 is
_{Since r} and _fv are cut off, the control signal from the phase comparator 22 is not output, and the output of the charge pump 26 becomes a floating level and becomes an open loop. The voltage controlled oscillator 24 stops the power supply when the VCO on / off control signal becomes L level. The EX-OR circuit 34 has a VCO
The on / off control signal and the PLL on / off control signal are input, and when only one of them is at the H level, its output becomes the H level. The analog switch 36 is turned on when the output of the EX-OR circuit 34 is at H level, and supplies the fixed voltage output from the voltage supply unit 38 to the input of the loop filter 28. The voltage supply unit 38 divides the power supply voltage Vcc with a resistor and outputs a fixed voltage of Vcc / 2. Loop filter 2
Since the output of 8 changes in the range of 0 or more and Vcc or less, the fixed voltage Vcc / 2 output by the voltage supply unit 38 corresponds to the center value of the range of the control voltage of the voltage controlled oscillator 24.

FIG. 2 is a timing chart for explaining the operation of the circuit of FIG. VCO on / while operation is stopped
Both the OFF control signal and the PLL ON / OFF control signal are L
Since it is at the level, the supply of power to the voltage controlled oscillator 24 is stopped, and the output of the charge pump 26 is at the floating level. At the time of rising, the VCO on / off control signal first becomes H level, so the control remains open loop control and the voltage controlled oscillator 24 starts up first. At this time, since the output of the EX-OR circuit 34 becomes H level, the analog switch 36 becomes conductive, and the loop filter 28 is supplied with the voltage supply unit 3 instead of the voltage from the charge pump 26.
The voltage Vcc / 2 from 8 is supplied. Then the PLL
Since the on / off control signal becomes H level, the analog switch 26 becomes non-conductive and the voltage control oscillator 24
Is a closed loop control. Immediately before entering the closed loop control, the capacitor in the loop filter 28 is charged with a voltage of Vcc / 2 regardless of the length of the off time, which corresponds to the center value of the control range, so that the closed loop control is performed in a short time. Is stable.

FIG. 3 is a diagram showing another embodiment of the present invention. 1 except that the voltage Vcc / 2 output by the voltage supply unit 38 is not directly input to the loop filter 28 via the analog switch 36 but is directly supplied to the capacitor therein. Since the voltage Vcc / 2 is directly supplied to the capacitor, the capacitor Vcc / can be supplied in a shorter time than in the case of FIG.
2 can be charged, and the delay time at the time of rising can be shortened. The voltage of Vcc / 2 contains power supply noise because it is only the power supply voltage Vcc divided.
It is supplied directly to the voltage controlled oscillator 24. But,
In any case, the operation of the voltage-controlled oscillator at the start-up is unstable, so it does not increase the problem.

FIG. 4 is a diagram showing another embodiment of the present invention. 3 is similar to FIG. 3 except that the loop filter 28 includes a buffer amplifier at its output. Also in this type of loop filter, the voltage Vcc /
Of course, 2 may be supplied to the input of the loop filter. FIG. 5 is a diagram showing another embodiment of the present invention. The difference from FIG. 1 is that an inverter 40 is used instead of the EX-OR circuit 34. Therefore, as shown in FIG. 6, the VCO on / off control signal and the PL
Even when both the L on / off control signals are at the L level, the voltage from the voltage supply unit 38 is supplied, but at the time of rising,
And the operation in the closed loop is the same.

[0017]

As described above, according to the present invention, in the phase-locked frequency synthesizer including the voltage controlled oscillator, which operates intermittently, a stable rise is realized regardless of the off time and the length of the time constant of the loop filter. To be done.

[Brief description of drawings]

FIG. 1 is a block diagram showing a phase-locked frequency synthesizer according to an embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of the circuit of FIG.

FIG. 3 is a block diagram showing another embodiment of the present invention.

FIG. 4 is a block diagram showing another embodiment of the present invention.

FIG. 5 is a block diagram showing another embodiment of the present invention.

FIG. 6 is a timing chart explaining the operation of the circuit of FIG.

FIG. 7 is a block diagram showing a configuration of an example of a phase-locked frequency synthesizer.

[Explanation of symbols]

 10 ... Frequency divider 12, 14, 16, 20 ... Variable frequency divider 24 ... Voltage controlled oscillator 26 ... Charge pump 28 ... Loop filter

Claims (4)

[Claims] 1. A control signal generation circuit for comparing a phase of a controlled signal from a voltage controlled oscillator with a phase of a reference signal to generate a frequency control signal according to a comparison result, and the control signal generation circuit outputs the control signal. A loop filter that generates the control voltage of the voltage controlled oscillator from the control signal, and the output of the control signal generation circuit is set to the floating level for open loop control within a predetermined period immediately after the power supply to the voltage controlled oscillator is turned on. A loop opening / closing control circuit; and a fixed voltage supply circuit that gives a fixed voltage to the loop filter so that the control voltage output by the loop filter becomes substantially the center value of the control range at least within the predetermined period. A control circuit for a phase-locked frequency synthesizer, characterized in that 2. The control circuit according to claim 1, wherein the fixed voltage supply circuit applies the fixed voltage to an input of the loop filter within the predetermined period. 3. The control circuit according to claim 1, wherein the fixed voltage supply circuit directly applies the fixed voltage to a capacitor included in the loop filter within the predetermined period. 4. The control circuit according to claim 1, wherein the fixed voltage supply circuit applies the fixed voltage to the loop filter while the power supply to the voltage controlled oscillator is not turned on for the predetermined period.