JPH08195092A - Data read circuit - Google Patents

Abstract

(57) [Summary] [Object] To provide a data read circuit capable of determining binary data even with a large gate voltage without increasing the threshold voltage fluctuation of the memory transistor. [Structure] The load transistor 18 is used to generate a load voltage V1 that changes according to the magnitude of a passing current of the memory transistor 101. This load voltage V1 is used as a reference voltage V2
And the binary data stored in the memory transistor 101 is read. The reference voltage V2 is determined based on the passing current of the reference transistor 13. In order to make the resistance value of the load transistor 18 equal to the resistance value of the reference load transistor 19 and to make a difference between the passing current of the reference transistor 13 in the memory transistor 101, the passing current of the memory transistor 101 is set by the constant current circuit 22. Add a constant current.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data read circuit for reading binary data from a memory transistor which constitutes an EPROM memory cell or the like.

[0002]

2. Description of the Related Art For example, a nonvolatile EPROM memory cell is composed of a MOS transistor 101 having a floating gate, as shown in FIG. This M
The OS transistor 101 has a floating gate 10
The passing current between the drain 103 and the source 104 is changed in two steps, large and small, based on the presence / absence of electrons accumulated in 2. If electrons are not accumulated in the floating gate 102, the gate voltage of the control gate 105 facilitates the flow of current between the drain 103 and the source 104. On the other hand, when electrons are accumulated in the floating gate 102, the positive electric field of the control gate 105 is canceled by the accumulated electrons, so that the current between the drain 103 and the source 104 becomes difficult to flow.

Now, with the drain voltage fixed at 1.2V,
A gate voltage is applied to the control gate 105 while electrons are not accumulated in the floating gate 102. As shown by the curve A in FIG. 6, the MOS transistor 1
01 is set so as to start passing the current Ids between the drain 103 and the source 104 at the gate voltage Vg1.5V (hereinafter referred to as “first threshold”). Gate voltage V
The passing current Ids rises almost in proportion to the rise of g. This state is tentatively defined as binary data "1".

A write operation is performed on the MOS transistor 101 to accumulate electrons in the floating gate 102. The so-called threshold fluctuation voltage ΔVth is set to 2V,
Therefore, when a gate voltage is applied to the control gate 105, the MOS transistor 101 will have a gate voltage Vg.
The current Ids starts to pass between the drain and the source at 3.5 V (hereinafter referred to as "second threshold value"). Curve B in FIG.
As shown in, the current characteristic is a curve obtained by translating the curve A of the binary data “1”. This state is defined as binary data "0".

In the MOS transistor 101, binary data "1" or "0" is specified as follows by these two-step changes in the passing current.

FIG. 7 shows a data read circuit for reading the binary data stored in the non-volatile memory cell 101 composed of MOS transistors. The data read circuit 110 determines the magnitude of the passing current of the memory cell 101 on the basis of the magnitude of the current passing through the reference transistor 111, and reads the binary data based on this determination.

Generally, in an EPROM, a plurality of memory cells are arranged in a grid. In order to read data from the memory cell 101, first, the memory cell 101 is designated by supplying a current from the power supply Vcc to the bit line 112 by opening a gate (not shown) and applying a gate voltage through the word line 113. In the designated memory cell 101, the current Ids between the source and the drain is set based on the characteristic of either curve A or B in FIG.
Passes through.

The magnitude of the current Ids passing through the memory cell 101 is detected by the differential amplifier 115 through the sense line 114. That is, the transfer gate 116
The voltage of the bit line 112 is maintained at a substantially constant value by the action of the bias circuit 117 which applies a bias voltage to the transfer gate 116. As a result,
A load voltage V1 divided by the resistance of the memory cell 101 and the resistance of the load transistor 118 appears on the sense line 114. The level of the load voltage V1 depends on the memory cell 1
The magnitude of the passing current Ids of 01 is reflected. The differential amplifier 115 uses the load voltage V1 and the reference voltage generation circuit RV.
The reference voltage V2 from 1 is compared. When the magnitude of the load voltage V1 is larger than the reference voltage V2, it is determined that the passing current of the memory cell 101 is small and the binary data “0” is stored, and when the magnitude of the load voltage V1 is smaller than the reference voltage V2, It is determined that the passing current of the memory cell 101 is large and the binary data “1” is stored.

Reference voltage generating circuit RV1 divides the voltage from power supply Vcc using reference transistor 111 and reference load transistor 119, and supplies the divided voltage to differential amplifier 115 as reference voltage V2.

The resistance value of the reference transistor 111, which is a factor for setting the value of the reference voltage V2, depends on the magnitude of the current passing between the drain and the source. The size of the reference transistor 111 is made equal to the size of the MOS transistor of the memory cell 101, and as a result, the passing current characteristic of the reference transistor 111 is at the time of large passing current, that is,
It becomes equal to the passing current characteristic (curve A in FIG. 6) of the memory cell 101 when the binary data “1” is stored.

By the way, the reference voltage V2 depends on the memory cell 1
Since it is a reference for discriminating the magnitude of the 01 passing current Ids, it is between the high load voltage V1 at the time of low passing current of the binary data "0" and the low load voltage V1 at the time of large passing current of the binary data "1". Must exist In order to obtain such a reference voltage V2, conventionally, the resistance value of the reference load transistor 119 is set to, for example, ½ of the resistance value of the load transistor 118, so that as shown by a curve C in FIG. The slope of the passing current characteristic of the reference transistor 111 is made gentle (half the slope of the curve A).

[0012]

However, when the reference voltage V2 is set in this way, as shown in FIG. 6, in the range where the gate voltage Vg of the reference transistor exceeds 6.5 V, a low passing current is generated. The passing current of the reference transistor becomes smaller than the passing current of the memory cell. As a result, the reference voltage V2 becomes larger than the load voltage V1 regardless of whether the binary data is “1” or “0”, and the differential amplifier cannot determine the magnitude of the memory cell passing current.

Further, since the electrons accumulated in the floating gate of the MOS transistor gradually flow out from the floating gate due to the influence of heat or the like in actual use, the second threshold value of the MOS transistor tends to decrease. Therefore, the threshold fluctuation voltage, which was set to 2V at the time of factory shipment, becomes small (curve B in FIG. 6).
, But the voltage of 6.5 V, which makes the judgment by the differential amplifier impossible, gradually drops.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a data read circuit capable of judging binary data even with a large gate voltage without increasing the threshold voltage fluctuation of the memory transistor. To do.

[0015]

In order to achieve the above object, according to the present invention, a power supply for supplying a current to a memory transistor that changes a passing current in two steps, large and small, based on storage of binary data, and a large power supply are provided. A reference transistor, which has a passing current characteristic equal to that of a memory transistor at the time of passing current and is supplied with current from the power source, and a voltage provided from the power source, which is provided between the power source and the memory transistor, is used to divide the voltage of the passing current of the memory transistor. A load element that generates a load voltage that changes according to a magnitude, a reference load element that is provided between the power source and the reference transistor, divides the voltage from the power source, and generates a reference voltage based on the passing current of the reference transistor, and the load voltage. And a differential amplifier that compares the magnitude of the In the data read circuit that determines the magnitude of the passing current of the memory transistor based on the magnitude of the current passing through the memory transistor and reads the binary data based on this determination, a constant current circuit is connected in parallel to the memory transistor. And

[0016]

According to the above structure, the passing current flowing through the load element on the memory transistor side is always larger than the passing current flowing through the load element on the reference transistor side by a constant amount due to the current supplied from the constant current circuit. This fixed amount of build-up maintains the magnitude relationship between the load voltage and the reference voltage over a wide gate voltage of the memory transistor.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 shows the configuration of an EPROM using a data read circuit according to the present invention. This EPROM is
For example, a plurality of non-volatile memory cells 101 arranged in a grid pattern are provided (only one is shown in the figure). Each memory cell 101 is composed of the MOS transistor 101 shown in FIG.

The data read circuit 10 includes a memory cell 1 from which binary data is to be read according to an external command.
Specify 01. That is, the bit line 11 that supplies the current from the power supply Vcc to the drain of the memory cell 101.
Is connected. A gate (not shown) is provided between the bit line 11 and the power supply Vcc, and "column" designation of the EPROM is sequentially performed based on opening / closing of the gate. A word line 12 for applying a voltage from a power supply Vcc is connected to the gate of the memory cell 101. The "row" of the EPROM is designated based on the gate voltage from the word line 12.

The current supplied from the bit line 11 passes between the drain and source of the memory cell 101 according to the application of the gate voltage Vg. The passing current changes in two steps, large and small, according to the presence or absence of electrons in the floating gate, and the binary data “1” or “0” is specified based on this change. The data read circuit 10 determines the magnitude of the passing current of the designated memory cell 101 based on the magnitude of the current passing through the reference transistor 13, and reads the binary data based on the determination.

The magnitude of the current passing through the memory cell 101 is detected by the differential amplifier 16 through the sense line 15 connected via the transfer gate 14.
The sense line 15 has a load voltage V1 divided by the resistance of the memory cell 101 and the resistance of the load transistor 18.
Appears. The level of the load voltage V1 depends on the memory cell 101.
Reflects the magnitude of the passing current of. Transfer gate 1
A bias voltage is applied to the memory cell 4 from the bias circuit 17, whereby the drain voltage of the memory cell 101 is maintained at a substantially constant value.

The differential amplifier 16 compares the magnitude of the load voltage V1 with the reference voltage V2 from the reference voltage generating circuit RV2. In the differential amplifier 16, when the magnitude of the load voltage V1 is larger than the reference voltage V2, it is determined that the passing current of the memory cell 101 is small and the binary data “0” is stored, and the magnitude of the load voltage V1 becomes large. When the voltage is lower than the reference voltage V2, the passing current of the memory cell 101 is large and it is determined that the binary data “1” is stored.

The reference voltage generation circuit RV2 includes a reference transistor 13 and a reference load transistor 19 which cooperates with the reference transistor 13 to divide the voltage from the power supply Vcc to generate the reference voltage V2.

The reference transistor 13 has a memory cell 10
A current is supplied from the power supply Vcc common to 1 and 1. The supplied current passes between the drain and the source according to the application of the gate voltage Vg from the power supply Vcc. The current passing characteristic of the reference transistor 13 is that at the time of large passing current, that is,
It is set to be equal to the passing current characteristic (curve A in FIG. 6) of the memory cell 101 when the binary data “1” is stored. The size of the reference transistor 13 is equal to the size of the MOS transistor of the memory cell 101.

The magnitude of the reference voltage V2 is determined by the resistance value of the reference load transistor 19 and the resistance value of the reference transistor 13, that is, the magnitude of the passing current of the reference transistor 13. In the present invention, the resistance value of the reference load transistor 19 is set equal to the resistance value of the load transistor 18.

The transfer gate 20 fixes the drain voltage of the reference transistor 13 at a substantially constant value based on the bias voltage applied from the bias circuit 21.

A feature of the present invention is that the memory cell 101 has a constant current passing through the memory cell 101,
For example, a constant current circuit 22 that accumulates a current of 20 μA is connected in parallel. This additional current is set so that the passing current of the memory cell 101 at the time of low passing current, that is, when the binary data “0” is stored does not exceed the passing current of the reference transistor 13. Due to this additional current, the passing current of the MOS transistor of the memory cell 101 and the passing current of the reference transistor 13 at the time of a large passing current are distinguished from each other, even though the passing current characteristics are equal to each other.

For example, the transfer gates 14 and 20
By using the memory cell 101 and the reference transistor 1
When the drain voltage of 3 is fixed to approximately 1.2V, the additional current results in a pass current characteristic (curves A1 and B1) raised by 20 μA for the binary data “1” or “0” as shown in FIG. To be

Now, under these characteristics, the data read circuit 10 reads the binary data "1" from the memory cell 101.
Consider the case of reading. When the memory cell 101 is selected in the EPROM, the power supply Vcc voltage of 5V is applied to the gates of the memory cell 101 and the reference transistor 13. As shown in FIG. 6, the current from the power supply Vcc passes through the memory cell 101 according to the passing current characteristic of the curve A1 or B1, and passes through the reference transistor 13 according to the passing current characteristic of the curve A. As a result, as shown in FIG. 2, the load voltage V1 becomes smaller than the reference voltage V2 at the gate voltage Vg5V. This magnitude relationship is detected by the differential amplifier 16, and a high level signal is output as binary data "1".

When reading the binary data "0" from the memory cell 101, the load voltage V1 becomes larger than the reference voltage V2 at the gate voltage Vg5V, as shown in FIG. The differential amplifier 16 detects this magnitude relationship and outputs a low level signal as binary data "0".

As is apparent from FIG. 6, the pass current characteristic of the memory cell 101 has the same slope as the current pass characteristic of the reference transistor 13 in both cases of large and small. According to this current characteristic, as shown in FIG. 2, over the wide range of the gate voltage Vg, particularly in the large gate voltage Vg region, the reference voltage V2 and the two-step load voltage Vg.
The magnitude relationship of 1 is maintained. Due to the expansion of the gate voltage Vg range, the threshold voltage variation ΔVt of the memory cell 101.
The degree of freedom in EPROM design can be increased without increasing h. In addition, since the slope of the load voltage V1 and the slope of the reference voltage V2 when the binary data “0” is stored are substantially equal to each other, the memory cell 10 is affected by heat or the like.
Even if electrons flow out from the floating gate of the first MOS transistor, a large margin can be provided before the magnitude relationship between the load voltage V1 and the reference voltage V2 is reversed. Therefore, the threshold fluctuation voltage ΔV of the memory cell 101
It is possible to provide a durable EPROM without increasing th.

A known circuit can be applied as the constant current circuit 22. For example, FIG. 3 shows a constant current circuit using a current mirror. The constant current circuit 22 includes a first MOSFET 30 that allows the current from the power supply Vcc to pass according to the gate voltage, and a second MOS transistor that allows the current that has passed through the first MOSFET 30 to pass according to the gate voltage.
And an FET 31. The drain of the first MOSFET 30 is connected to the gate. The on-resistance of the first MOSFET 30 is set to be relatively high, and the drain and the gate are connected to operate in the saturation region.
A constant current flows through 30. A constant current passes through the second MOSFET 31 under a constant gate voltage, and a constant current also passes through the third MOSFET 33 by the action of the current mirror circuit.

FIG. 4 shows a constant current circuit using a depletion type MOSFET. This constant current circuit 22 has a MOSF
The source and gate of ET35 are connected. According to this MOSFET 35, the gate voltage is always held at 0 V, and as a result, when the drain voltage exceeds a predetermined value,
Even if the drain voltage changes, the drain-source current is kept substantially constant.

The reference voltage generating circuit RV2 may be provided for each memory cell, that is, for each memory transistor.
It may be provided in units of 8 bits or for each device. Also,
The present invention is not limited to the data read circuit of the EPROM memory cell, but can be applied to the data read circuit of other nonvolatile memories.

[0035]

As described above, according to the present invention, by increasing the passing current of the memory transistor by a constant amount, the magnitude relationship between the load voltage and the reference voltage is maintained over a wide range of the gate voltage of the memory transistor. be able to. As a result, the degree of freedom in memory design is expanded.

[Brief description of drawings]

FIG. 1 shows an E using a data read circuit according to the present invention.
It is a circuit block diagram of PROM.

FIG. 2 is a graph showing a relationship between a gate voltage of a memory transistor and a load voltage or a reference voltage.

FIG. 3 is a circuit configuration diagram showing a first embodiment of a constant current circuit.

FIG. 4 is a circuit configuration diagram showing a second embodiment of a constant current circuit.

FIG. 5 is a configuration diagram showing an outline of a memory cell.

FIG. 6 is a graph showing the relationship between the gate voltage and the passing current of a MOS transistor.

FIG. 7 is a circuit configuration diagram of a conventional data read circuit.

[Explanation of symbols]

10 data read circuit, 13 reference transistor,
16 differential amplifier, 18 load transistor as load element, 19 reference load transistor, 22 constant current circuit, 101 MOS transistor as memory transistor, Vcc power supply.

Claims (1)

[Claims] 1. Large / small 2 based on storage of binary data
Between the power supply and the memory transistor, a power supply that supplies a current to the memory transistor that changes the passing current in stages, a reference transistor that has the same passing current characteristics as the memory transistor at the time of a large passing current, and is supplied with the current from the power supply. Is provided between the power supply and the reference transistor to divide the voltage from the power supply to create a load voltage that changes according to the magnitude of the passing current of the memory transistor, and to divide the voltage from the power supply to provide the reference transistor. A reference load element that generates a reference voltage based on the passing current of the reference voltage, and a differential amplifier that compares the magnitude of the load voltage with the reference voltage. The size of the passing current of the memory transistor is judged based on the size, and the binary data is judged based on this judgment. In the data reading circuit for reading, data read circuit, characterized in that it is connected a constant current circuit in parallel to the memory transistor.