JPH08195410A - Pressurized contact type semiconductor device - Google Patents
Pressurized contact type semiconductor deviceInfo
- Publication number
- JPH08195410A JPH08195410A JP535195A JP535195A JPH08195410A JP H08195410 A JPH08195410 A JP H08195410A JP 535195 A JP535195 A JP 535195A JP 535195 A JP535195 A JP 535195A JP H08195410 A JPH08195410 A JP H08195410A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- positioning guide
- semiconductor device
- main
- main electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Abstract
(57)【要約】
【目的】複数個の半導体チップをパッケージ容器に組み
込んでモジュール化した半導体装置を対象に、半導体チ
ップと加圧、放熱体を兼ねたコンタクト端子体との正確
に位置決めすることで、組立時の素子破壊を防止し、素
子の信頼性を高める。
【構成】位置決めガイド2の張出部14により金属基板
7上のチップ搭載台8と半導体チップ4が位置決めさ
れ、はんだシート6ではんだ付けされた後、コンタクト
端子体1がこの位置決めガイド2で位置決めされ、コン
タクト端子体1の凸部10と集電電極5とが正確に位置
合わせされる。
(57) [Abstract] [Purpose] Accurate positioning of semiconductor chips and contact terminals that also function as pressure and heat radiators for semiconductor devices that are modularized by incorporating multiple semiconductor chips into a package container. Thus, the element breakdown during assembly is prevented and the reliability of the element is improved. [Structure] The chip mounting base 8 on the metal substrate 7 and the semiconductor chip 4 are positioned by the overhanging portion 14 of the positioning guide 2, soldered by the solder sheet 6, and then the contact terminal body 1 is positioned by this positioning guide 2. Then, the convex portion 10 of the contact terminal body 1 and the collector electrode 5 are accurately aligned.
Description
【0001】[0001]
【産業上の利用分野】この発明は、絶縁ゲート形バイポ
ーラトランジスタ(IGBT)モジュールなどのパワー
デバイスを対象に基板の一主面に第一の主電極と制御電
極、別の主面に第二の主電極を有する半導体チップの複
数個を同一のパッケージ内に組み込んだ加圧接触形半導
体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is applied to power devices such as insulated gate bipolar transistor (IGBT) modules and the like, and has a first main electrode and a control electrode on one main surface of a substrate and a second main electrode on another main surface. The present invention relates to a pressure contact type semiconductor device in which a plurality of semiconductor chips each having a main electrode are incorporated in the same package.
【0002】[0002]
【従来の技術】IGBTは、パワースイッチングデバイ
スとしてモータPWM制御インバータの応用などに幅広
く使われている。また、このIGBTは電圧駆動型で扱
い易いなどから、市場への要求は大容量化へ向かってき
ており、半導体チップの大型化と相まってますます大容
量化が進められる傾向にあり、最近では容量の増大を図
るために複数のIGBTを同一パッケージ内に組み込ん
だモジュール構造が多く採用されるようになっている。2. Description of the Related Art IGBTs are widely used as power switching devices for applications such as motor PWM control inverters. Also, because this IGBT is a voltage-driven type and easy to handle, the demand for the market is increasing toward larger capacities, and along with the increase in the size of semiconductor chips, there is a trend toward larger capacities. In order to increase the number of modules, a module structure in which a plurality of IGBTs are incorporated in the same package is often adopted.
【0003】ところで、IGBTのような絶縁ゲート形
素子(MOS制御デバイス)では半導体チップの一主面
上に主電極としてのエミッタ電極、および制御電極とし
てのゲート電極が並んで形成されている。このためIG
BTのチップをパッケージングして組立てる場合に、第
二主面側のコレクタは放熱体兼用の金属ベース上に直接
マウントすることができるが、第一主面側のエミッタ電
極とゲート電極は別々に外部導出端子を介して引き出す
必要がある。そこで、従来のパッケージ組立構造では、
前記の金属ベースとともにパッケージのケース上面側に
エミッタ、ゲート用の外部導出端子を装備し、エミッタ
電極と外部導出端子、およびゲート電極と外部導出端子
との間に線径300μm程度のアルミ導線をワイヤボン
デングして引き出すようにしている。In an insulated gate element (MOS control device) such as an IGBT, an emitter electrode as a main electrode and a gate electrode as a control electrode are formed side by side on one main surface of a semiconductor chip. Therefore IG
When the BT chip is packaged and assembled, the collector on the second main surface side can be directly mounted on the metal base that also serves as a heat radiator, but the emitter electrode and gate electrode on the first main surface side are separately provided. It is necessary to pull out through the external lead-out terminal. So, in the conventional package assembly structure,
An external lead terminal for the emitter and the gate is provided on the upper surface side of the package case together with the above-mentioned metal base, and an aluminum conductor wire having a wire diameter of about 300 μm is wired between the emitter electrode and the external lead terminal and between the gate electrode and the external lead terminal. I try to bond it and pull it out.
【0004】[0004]
【発明が解決しようとする課題】ところで、前記した従
来の組立構造ではコレクタ側からは十分な熱放散ができ
るが、エミッタ側からの熱放散は殆ど行われないために
電流容量が大幅に制限される。また、大電流容量の素子
ではエミッタ電極に接続したボンデングワイヤの本数も
多くなり、特に複数個のIGBTを同一パッケージに組
み込んでモジュール化した構成ではワイヤ本数が数百本
にも及ぶため、内部配線インダクタンスが増大し、これ
が基でIGBTのスイッチング動作時に大きなサージが
発生するといった問題も派生する。By the way, in the above-mentioned conventional assembly structure, although sufficient heat can be dissipated from the collector side, heat is hardly dissipated from the emitter side, so that the current capacity is significantly limited. It Also, in a device with a large current capacity, the number of bonding wires connected to the emitter electrode also increases. Especially, in the configuration in which a plurality of IGBTs are incorporated in the same package to form a module, the number of wires reaches several hundreds. The wiring inductance increases, which causes a problem that a large surge occurs during the switching operation of the IGBT.
【0005】一方、前記の組立構造による放熱性、配線
インダクタンスの問題解消を狙いに、在来の加圧接触形
半導体装置と同様に、IGBTを平形パッケージ内に組
み込み、その主面に形成されたコレクタ電極、エミッタ
電極をそれぞれパッケージ側に設けた上下の電極板に面
接触させて引き出すようにすることが考えられる。しか
しながら、IGBTはゲート電極を覆う絶縁層の上にエ
ミッタ電極にパッケージ側の電極板を圧接させると、こ
の加圧力がゲート電極にも加わってゲート電極構造を破
壊するおそれがあり、これを防ぐために、このゲート電
極部分を避けて、熱放散と電流通路を兼ね備えた集電電
極と呼ばれる部分を設けてその部分を加圧することによ
り平形素子を構成している。また、IGBTモジュール
として、同一パッケージ内にIGBTとこれに付属する
フライホイールダイオードを一緒に組み込んだ複合デバ
イスに加圧接触式の平形パッケージを採用した場合に
は、次のような問題が派生する。すなわち、電気的特性
面から要求されるIGBTとフライホイールダイオード
とは、一般的にチップの高さ寸法(ウエハの厚さ)が異
なるため、このような高さ寸法が異なる異種の半導体チ
ップを並置して同一の平形パッケージに組み込んだ場合
にはチップの上面高さが揃わず、各半導体チップを均一
に加圧接触させることが極めて困難となる。これを防ぐ
ため、半導体チップを平形パッケージの電極板に固着す
るのにはんだシートを用いて高さ寸法の差を吸収するよ
うにしている。On the other hand, in order to solve the problems of heat dissipation and wiring inductance by the above-mentioned assembly structure, the IGBT is built in the flat package and formed on the main surface thereof, like the conventional pressure contact type semiconductor device. It is conceivable that the collector electrode and the emitter electrode are respectively brought into surface contact with the upper and lower electrode plates provided on the package side to be drawn out. However, in the IGBT, if the package-side electrode plate is brought into pressure contact with the emitter electrode on the insulating layer covering the gate electrode, this pressure may also be applied to the gate electrode and destroy the gate electrode structure. A flat element is formed by avoiding the gate electrode portion and providing a portion called a collector electrode having both heat dissipation and current passage and pressurizing the portion. Further, when the pressure contact type flat package is adopted as the IGBT module in the composite device in which the IGBT and the flywheel diode attached to the IGBT are incorporated in the same package, the following problems occur. That is, since the IGBT and the flywheel diode, which are required in terms of electrical characteristics, generally have different chip height dimensions (wafer thickness), different semiconductor chips having different height dimensions are arranged side by side. Then, when the chips are assembled in the same flat package, the heights of the upper surfaces of the chips are not uniform, and it becomes extremely difficult to uniformly press and contact each semiconductor chip. To prevent this, a solder sheet is used to fix the semiconductor chip to the electrode plate of the flat package so as to absorb the height difference.
【0006】このはんだシートと半導体チップの位置合
わせ、ならびに組立時のコンタクト端子体と半導体チッ
プ上の集電電極の位置合わせが同一の耐熱性プラスチッ
クの位置決めガイドで従来行われてきた。図3に従来の
構造の要部断面図を示す。平形パッケージの電極板上の
チップ搭載台の側面を、位置決めガイド用スリットと、
その上部のはんだ逃げ代ろ用の溝と2段分の加工が施さ
れている。位置決めガイド用スリットの加工精度が極め
て重要であり、2段分の加工で高精度な加工を行うとは
高度な技術を必要とし、また加工コストの増大を招く。The alignment of the solder sheet and the semiconductor chip and the alignment of the contact terminal body and the collector electrode on the semiconductor chip during assembly have been conventionally performed with the same heat-resistant plastic positioning guide. FIG. 3 shows a sectional view of a main part of a conventional structure. The side of the chip mounting base on the electrode plate of the flat package is provided with a positioning guide slit,
A groove for solder relief on the upper part and two steps of processing are applied. The processing accuracy of the positioning guide slit is extremely important, and performing high-precision processing by processing two steps requires a high level of technology and increases processing cost.
【0007】この発明は、前記の課題を解決するため
に、耐熱性プラスチックで位置決めガイドの底部に張出
部を設け、半導体チップより小さなチップ搭載台に位置
決めガイドを固定することで、2段分の加工を1段の加
工で済ませ、高度な加工技術を不用とし、容易でしかも
安価な加工で高精度な位置合わせができる構造の加圧接
触型半導体装置を提供することにある。In order to solve the above-mentioned problems, the present invention provides a two-step structure by providing a protrusion on the bottom of the positioning guide with heat-resistant plastic and fixing the positioning guide to a chip mounting base smaller than a semiconductor chip. It is an object of the present invention to provide a pressure contact type semiconductor device having a structure that requires only one step of processing, does not require high-level processing technology, and can perform highly accurate alignment with easy and inexpensive processing.
【0008】[0008]
【課題を解決するための手段】この発明は前記の目的を
達成するために、第一主面に第一主電極と制御電極を、
第二主面に第二主電極をそれぞれ有する半導体チップを
複数個並置して、両面に露出する一対の共通電極板の間
に絶縁外筒を介装してなる平形パッケージに組み込んだ
半導体装置において、各半導体チップの第一主電極とこ
れに対向するパッケージ側の共通電極板との間にそれぞ
れ加圧、導電、放熱体を兼ねたコンタクト端子体を介装
し、各半導体チップと各コンタクト端子体とが対応する
ように、第二主電極と第二主電極に対向するパッケージ
側の共通電極板とに挟まれた金属基板上部に設けられ
た、半導体チップより小さなチップ搭載台の側面に、位
置決めガイドの底部を固定することである。この位置決
めガイドの底部にチップ搭載台の高さより低い張出部を
設け、この張出部で位置決めガイドをチップ搭載台に固
定すると効果的である。この位置決めガイドを耐熱性プ
ラスチック(液晶ポリマー)で製作するとよい。In order to achieve the above object, the present invention provides a first main electrode and a control electrode on a first main surface,
A plurality of semiconductor chips each having a second main electrode on the second main surface are juxtaposed, and a semiconductor device incorporated in a flat package formed by interposing an insulating outer cylinder between a pair of common electrode plates exposed on both surfaces. Contact terminals that also function as pressure, conduction, and heat radiators are respectively interposed between the first main electrode of the semiconductor chip and the common electrode plate on the package side facing the first main electrode, and each semiconductor chip and each contact terminal body are connected. , The positioning guide is provided on the side surface of the chip mounting base smaller than the semiconductor chip, which is provided on the upper part of the metal substrate sandwiched between the second main electrode and the common electrode plate on the package side facing the second main electrode. Is to fix the bottom of the. It is effective to provide an overhanging portion that is lower than the height of the chip mounting base at the bottom of this positioning guide, and fix the positioning guide to the chip mounting base by this overhanging portion. The positioning guide may be made of heat resistant plastic (liquid crystal polymer).
【0009】また、第一主面に第一主電極と制御電極、
第二主面に第二主電極を有する半導体チップが絶縁ゲー
ト形素子であり、同一の平形パッケージ内には複数個の
絶縁ゲート形素子と逆並列にフライホイールダイオード
を組み込み、かつ、絶縁ゲート形素子の第一主電極およ
びフライホイールダイオードのアノード電極とこれに対
向するパッケージ側の共通電極板との間にそれぞれ加
圧、放熱体とを兼ねたコンタクト端子体を具備したこと
である。さらにこの絶縁ゲート形素子が絶縁ゲート形バ
イポーラトランジスタ(IGBT)を含むMOSトラン
ジスタまたは絶縁ゲート形サイリスタ(MOS制御サイ
リスタ)からなることである。Further, a first main electrode and a control electrode are provided on the first main surface,
A semiconductor chip having a second main electrode on the second main surface is an insulated gate type element, and a flywheel diode is installed in antiparallel with a plurality of insulated gate type elements in the same flat package and That is, the first main electrode of the device and the anode electrode of the flywheel diode and the package-side common electrode plate facing the first main electrode are provided with contact terminal bodies that also function as pressure and heat radiators, respectively. Further, the insulated gate element is a MOS transistor including an insulated gate bipolar transistor (IGBT) or an insulated gate thyristor (MOS control thyristor).
【0010】[0010]
【作用】上記構成のように、平形パッケージに組み込ま
れた複数個の各半導体チップごとにゲート電極以外の領
域に設けた電流通路と放熱を兼ね備えた集電電極部に対
してパッケージ側の共通電極板(エミッタ側)との間に
面接触する、平行度と同一高さを確保した各コンタクト
端子体を介して加圧接触させることにより、半導体チッ
プのゲート電極部に不当な加圧力を加えることなしに、
このエミッタ側の第一主面からもコンタクト端子体およ
びパッケージの外面に露出する共通電極板を通して放熱
が効率よく行われる。これにより、コレクタ側の第二主
面側からの放熱と合わせて放熱性が飛躍的に向上するの
で半導体装置の電流容量の増大化が図れる。また主電極
の接続にはボンデングワイヤを使用しないので内部イン
ダクタンスも小さくなる。As described above, the common electrode on the package side with respect to the current collecting electrode portion provided in a region other than the gate electrode and having heat dissipation provided for each of the plurality of semiconductor chips incorporated in the flat package with respect to the package electrode. Applying an unreasonable pressure to the gate electrode part of the semiconductor chip by making pressure contact through each contact terminal body that has surface contact with the plate (emitter side) and that secures parallelism and the same height. Without,
Also from this first main surface on the emitter side, heat can be efficiently radiated through the common electrode plate exposed to the contact terminal body and the outer surface of the package. As a result, heat dissipation from the second main surface side on the collector side is dramatically improved, and the current capacity of the semiconductor device can be increased. Moreover, since the bonding wire is not used for connecting the main electrodes, the internal inductance is also reduced.
【0011】一方、複数のIGBTチップおよびフライ
ホイールダイオードが、基板に対し、最終的に素子内に
組み込まれる位置決めガイドにて正確に位置決めされな
がら、はんだ接合される。ここで従来のような金属基板
上のチップ搭載台にはんだ逃げ代ろ用溝や位置決めガイ
ド用スリットなどの複数の段差加工をせず、位置決めガ
イドの底部に張出部を設けて、はんだ逃げ代ろ部とする
ことで、チップ搭載台の側面の溝形成の加工を不用と
し、位置決めガイド用スリットの加工のみとする。この
ようにすることで、位置決めガイドがチップ搭載台に高
精度に位置合わせされ、同時に素子の製造工程が簡略か
され、コストダウンにつながる。On the other hand, a plurality of IGBT chips and flywheel diodes are solder-bonded to the substrate while being accurately positioned by a positioning guide finally incorporated in the device. Here, multiple steps such as solder relief groove and positioning guide slit are not formed on the chip mounting base on the metal substrate as in the past, and a protrusion is provided at the bottom of the positioning guide to remove the solder relief allowance. By forming the filter portion, it is not necessary to process the groove formation on the side surface of the chip mounting base, and only the positioning guide slit is processed. By doing so, the positioning guide is accurately aligned with the chip mounting base, and at the same time, the manufacturing process of the element is simplified and the cost is reduced.
【0012】[0012]
【実施例】図1はこの発明の一実施例を示す要部構成図
で、同図(a)は断面構造図、同図(b)は同図(a)
の位置決めガイドの斜視図である。同図(a)におい
て、金属基板7上部のチップ搭載台8上に溶融し固化し
たはんだシート6を介して半導体チップ4が固着する。
このとき、位置決めガイド2によりチップ搭載台8、は
んだシート6、半導体チップ4は位置決めされる。この
位置決めガイド2によりコンタクト端子体1の凸部10
が半導体チップ4の集電極5上に正確に位置合わせされ
る。金属基板7とコンタクト端子体1は共通電極板であ
るコレクタ電極板12とエミッタ電極板13とそれぞれ
外部力により圧接される。同図(b)において、位置決
めガイド2の底面に張出部14が設けられ、この張出部
14はチップ搭載台8の高さより低い。この張出部14
はチップ搭載台8に嵌め込まれ、位置決めガイド2は固
定される。また位置決めガイド2の上部にゲートワイヤ
用切り欠き3が設けられている。金属基板7とコレクタ
電極板12とを一体構造として共通電極板としてもよ
い。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a schematic view of a main part of an embodiment of the present invention, in which FIG. 1 (a) is a sectional structural view and FIG.
It is a perspective view of a positioning guide of. In FIG. 3A, the semiconductor chip 4 is fixed on the chip mounting table 8 on the metal substrate 7 via the melted and solidified solder sheet 6.
At this time, the chip mounting base 8, the solder sheet 6, and the semiconductor chip 4 are positioned by the positioning guide 2. With this positioning guide 2, the convex portion 10 of the contact terminal body 1
Are accurately aligned on the collector electrode 5 of the semiconductor chip 4. The metal substrate 7 and the contact terminal body 1 are pressed against the collector electrode plate 12 and the emitter electrode plate 13, which are common electrode plates, by external force. In FIG. 2B, a protrusion 14 is provided on the bottom surface of the positioning guide 2, and the protrusion 14 is lower than the height of the chip mounting table 8. This overhang 14
Is fitted into the chip mounting base 8 and the positioning guide 2 is fixed. Further, a notch 3 for gate wire is provided on the upper part of the positioning guide 2. The metal substrate 7 and the collector electrode plate 12 may be integrated into a common electrode plate.
【0013】図2はこの発明による位置決めガイドを使
用した素子の製作法を示す図である。金属基板7にチッ
プ搭載台8を設け、このチップ搭載台8の側面9に位置
決めガイド2の張出部14の内端が接するように位置決
めガイド2を嵌め込み、チップ搭載台9に、はんだシー
ト6と半導体チップ4を位置決めガイド2で位置決めし
て置き、はんだシート6でチップ搭載台8と半導体チッ
プ4を固着したあと、位置決めガイド2にコンタクト端
子体1を挿入し、コンタクト端子体1の凸部10と集電
極5とが正確に対応して接触するようにコンタクト端子
体1を位置決めする。また位置決めガイド2はゲートワ
イヤ引出し用切り欠き3を有している。尚、はんだシー
ト6によるチップ台8と半導体チップ4との固着はリフ
ロー炉などのはんだ付け炉により行われる。FIG. 2 is a diagram showing a method of manufacturing an element using the positioning guide according to the present invention. The chip mounting base 8 is provided on the metal substrate 7, and the positioning guide 2 is fitted so that the inner end of the overhanging portion 14 of the positioning guide 2 contacts the side surface 9 of the chip mounting base 8. The semiconductor chip 4 and the semiconductor chip 4 are positioned by the positioning guide 2, the chip mounting base 8 and the semiconductor chip 4 are fixed by the solder sheet 6, and then the contact terminal body 1 is inserted into the positioning guide 2 to project the convex portion of the contact terminal body 1. The contact terminal body 1 is positioned so that the collector electrode 10 and the collector electrode 5 correspond to each other in an accurate correspondence. The positioning guide 2 has a notch 3 for pulling out the gate wire. The chip base 8 and the semiconductor chip 4 are fixed by the solder sheet 6 in a soldering furnace such as a reflow furnace.
【0014】位置決めガイド2に張出部14を設け、張
出部14の厚さをチップ搭載台8の高さより薄くし、半
導体チップ4より小さいチップ搭載台8に位置決めガイ
ド2を固定することで、はんだ逃げ代部15となる空間
ができ、従来構造のはんだ逃げ代用溝11と同様の効果
が得られる。またチップ搭載台12の側面に従来のよう
にはんだ逃げ代を設ける必要がなく、チップ搭載台12
の側面加工が1段加工で済むため、精度良い加工が容易
にでき、集電電極とコンタクト端子体との位置合わせが
精度良くでき、さらに加工コストの低減が図れる。By providing the positioning guide 2 with the protruding portion 14, making the thickness of the protruding portion 14 thinner than the height of the chip mounting base 8, and fixing the positioning guide 2 to the chip mounting base 8 smaller than the semiconductor chip 4. A space to be the solder escape allowance portion 15 is formed, and the same effect as the solder escape allowance groove 11 of the conventional structure can be obtained. Further, unlike the conventional case, it is not necessary to provide a solder clearance on the side surface of the chip mounting table 12,
Since only one step is required for the side surface processing, the accurate processing can be easily performed, the current collecting electrode and the contact terminal body can be accurately aligned, and the processing cost can be reduced.
【0015】前記の位置決めガイド2の材質ははんだ付
けの温度である320°Cより高い340°C以上に耐
える耐熱性プラスチック(液晶ポリマー)などである。
また前記の構成にすることで半導体チップ4が基板7と
コンタクト端子体1を介して両面冷却できるようにな
る。また半導体チップ4はIGBTを含むMOSトラン
ジスタ、MOS制御サイリスタなどの絶縁ゲート形素子
およびフライホイールダイオードである。The material of the positioning guide 2 is a heat-resistant plastic (liquid crystal polymer) which can withstand 340 ° C. or higher, which is higher than the soldering temperature of 320 ° C.
Further, with the above configuration, the semiconductor chip 4 can be cooled on both sides via the substrate 7 and the contact terminal body 1. The semiconductor chip 4 is a MOS transistor including an IGBT, an insulated gate element such as a MOS control thyristor, and a flywheel diode.
【0016】尚、図1は半導体チップが2個の場合を示
すが、さらに多数の半導体チップが配置される場合もあ
る。また、絶縁ゲート形素子とフライホイールダイオー
ドとの双方が存在する場合にはお互いが逆並列になるよ
うに配置される。Although FIG. 1 shows the case where there are two semiconductor chips, a larger number of semiconductor chips may be arranged. When both the insulated gate element and the flywheel diode are present, they are arranged so as to be antiparallel to each other.
【0017】[0017]
【発明の効果】この発明によれば、半導体チップのゲー
ト電極に不当な加圧力を加えること無しに、複数個の半
導体チップを面接触により均一な加圧接触が達成できる
ように平形パッケージ内に組み込み、各半導体チップの
両面からの放熱を可能とし、電流容量の増加を図るほ
か、主電極からの電流の引出しにボンデングワイヤを使
用しないので内部配線インダクタンスも小さくなり、ハ
ーメチックシール構造の平形パッケージと組み合わせて
半導体装置の大幅な信頼性向上が図れる。また加えて組
立ガイドにより、素子とコンタクト端子体間の位置決め
が正確に確保され、位置ずれ等によるゲート電極部分の
加圧がなくなり、ゲート電極部分を損傷することがなく
なる。According to the present invention, a plurality of semiconductor chips can be placed in a flat package in a flat package so that a uniform pressure contact can be achieved by surface contact without applying an undue pressing force to the gate electrodes of the semiconductor chips. Assembled, allowing heat to be dissipated from both sides of each semiconductor chip to increase the current capacity, and because the bonding wire is not used to draw out the current from the main electrode, the internal wiring inductance is also reduced, and the flat package has a hermetically sealed structure. In combination with this, the reliability of the semiconductor device can be greatly improved. In addition, the assembly guide ensures accurate positioning between the element and the contact terminal body, and pressure applied to the gate electrode portion due to displacement or the like is eliminated so that the gate electrode portion is not damaged.
【0018】また従来、金属基板にチップ搭載台とはん
だ逃げ代用溝の複数段の加工が必要であったが、この発
明でははんだ逃げ代用溝の加工は不用となり、容易に精
度良い加工ができ、位置決めガイドとチップ搭載台との
位置決めが精度よくでき、従って、コンタクト端子体と
半導体チップ上の集電電極との位置合わせも高精度でで
きる。また加工工程が簡素化され、製造コストを大幅に
低減できる。Conventionally, it was necessary to process the chip mounting base and the solder relief groove on the metal substrate in a plurality of steps. However, in the present invention, the machining of the solder relief groove is unnecessary, and it is possible to easily and accurately perform machining. The positioning guide and the chip mounting base can be positioned with high accuracy, and therefore the contact terminal body and the collector electrode on the semiconductor chip can be positioned with high accuracy. Further, the processing steps are simplified, and the manufacturing cost can be significantly reduced.
【図1】この発明の一実施例を示す要部構成図で、同図
(a)は断面構造図、同図(b)は位置決めガイドの斜
視図1A and 1B are configuration diagrams of a main part showing an embodiment of the present invention, in which FIG. 1A is a sectional structural view and FIG. 1B is a perspective view of a positioning guide.
【図2】この発明による位置決めガイドを使用した素子
の製作法を示す図FIG. 2 is a diagram showing a method of manufacturing an element using a positioning guide according to the present invention.
【図3】従来の要部構成図で同図(a)は断面構造図、
同図(b)は位置決めガイドの斜視図FIG. 3 is a sectional view showing a conventional main part configuration in FIG.
FIG. 3B is a perspective view of the positioning guide.
1 コンタクト端子体 2 位置決めガイド 3 ゲートワイヤ用切り欠き 4 半導体チップ 5 集電電極 6 はんだシート 7 金属基板 8 チップ搭載台 9 チップ搭載台の側面 10 コンタクト端子体の凸部 11 はんだ逃げ代用溝 12 コレクタ電極板 13 エミッタ電極板 14 張出部 15 はんだ逃げ代部 DESCRIPTION OF SYMBOLS 1 Contact terminal body 2 Positioning guide 3 Gate wire notch 4 Semiconductor chip 5 Current collecting electrode 6 Solder sheet 7 Metal substrate 8 Chip mounting base 9 Side surface of chip mounting base 10 Convex portion of contact terminal body 11 Solder escape substitute groove 12 Collector Electrode plate 13 Emitter electrode plate 14 Overhang 15 Solder relief area
Claims (5)
主面に第二主電極をそれぞれ有する半導体チップを複数
個並置して、両面に露出する一対の共通電極板の間に絶
縁外筒を介装してなる平形パッケージに組み込んだ半導
体装置において、各半導体チップの第一主電極とこれに
対向するパッケージ側の共通電極板との間にそれぞれ加
圧、導電、放熱体を兼ねたコンタクト端子体を介装し、
各半導体チップと各コンタクト端子体とが対応するよう
に、第二主電極と第二主電極に対向するパッケージ側の
共通電極板とに挟まれた金属基板上部に設けられた、半
導体チップより小さなチップ搭載台の側面に、位置決め
ガイドの底部を固定することを特徴とする加圧接触形半
導体装置。1. A plurality of semiconductor chips, each having a first main electrode and a control electrode on a first main surface and a second main electrode on a second main surface, are arranged side by side and between a pair of common electrode plates exposed on both surfaces. In a semiconductor device incorporated in a flat package having an insulating outer tube interposed therebetween, a pressure member, a conductor member, and a heat radiator are provided between the first main electrode of each semiconductor chip and the common electrode plate on the package side facing the first main electrode. By interposing the double-ended contact terminal body,
Smaller than the semiconductor chip, provided on the metal substrate sandwiched between the second main electrode and the common electrode plate on the package side facing the second main electrode so that each semiconductor chip and each contact terminal body correspond to each other. A pressure contact type semiconductor device characterized in that a bottom of a positioning guide is fixed to a side surface of a chip mounting base.
さより低い張出部を設け、該張出部で位置決めガイドを
チップ搭載台に固定することを特徴とする請求項1記載
の加圧接触形半導体装置。2. The pressure contact according to claim 1, wherein an overhanging portion lower than the height of the chip mounting base is provided at the bottom of the positioning guide, and the positioning guide is fixed to the chip mounting base by the overhanging portion. Type semiconductor device.
晶ポリマー)からなることを特徴とする請求項1又は2
記載の加圧接触形半導体装置。3. The positioning guide is made of heat resistant plastic (liquid crystal polymer).
The pressure contact type semiconductor device described.
面に第二主電極を有する半導体チップが絶縁ゲート形素
子であり、同一の平形パッケージ内には複数個の絶縁ゲ
ート形素子と逆並列にフライホイールダイオードを組み
込み、かつ、絶縁ゲート形素子の第一主電極およびフラ
イホイールダイオードのアノード電極とこれに対向する
パッケージ側の共通電極板との間にそれぞれ加圧、導
電、放熱体とを兼ねたコンタクト端子体を具備したこと
を特徴とする請求項1記載の加圧接触形半導体装置。4. A semiconductor chip having a first main electrode and a control electrode on a first main surface and a second main electrode on a second main surface is an insulated gate element, and a plurality of insulating elements are provided in the same flat package. A flywheel diode is installed in antiparallel with the gate type element, and pressure is applied between the first main electrode of the insulated gate type element and the anode electrode of the flywheel diode and the common electrode plate on the package side facing the anode electrode, respectively. 2. The pressure contact type semiconductor device according to claim 1, further comprising a contact terminal body that also functions as a conductor and a heat radiator.
ラトランジスタ(IGBT)を含むMOSトランジスタ
もしくは絶縁ゲート形サイリスタ(MOS制御サイリス
タ)からなることを特徴とする請求項4記載の加圧接触
形半導体装置。5. The pressure contact type semiconductor device according to claim 4, wherein the insulated gate element is a MOS transistor including an insulated gate bipolar transistor (IGBT) or an insulated gate thyristor (MOS control thyristor). .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP535195A JP3166527B2 (en) | 1995-01-18 | 1995-01-18 | Pressure contact type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP535195A JP3166527B2 (en) | 1995-01-18 | 1995-01-18 | Pressure contact type semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH08195410A true JPH08195410A (en) | 1996-07-30 |
| JP3166527B2 JP3166527B2 (en) | 2001-05-14 |
Family
ID=11608782
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP535195A Expired - Fee Related JP3166527B2 (en) | 1995-01-18 | 1995-01-18 | Pressure contact type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3166527B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013231626A (en) * | 2012-04-27 | 2013-11-14 | Honda Motor Co Ltd | Electrification inspection apparatus for semiconductor chip and electrification inspection method of semiconductor chip |
| CN112652612A (en) * | 2019-10-12 | 2021-04-13 | 深圳第三代半导体研究院 | Stacked crimping type power module and manufacturing method thereof |
-
1995
- 1995-01-18 JP JP535195A patent/JP3166527B2/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013231626A (en) * | 2012-04-27 | 2013-11-14 | Honda Motor Co Ltd | Electrification inspection apparatus for semiconductor chip and electrification inspection method of semiconductor chip |
| CN112652612A (en) * | 2019-10-12 | 2021-04-13 | 深圳第三代半导体研究院 | Stacked crimping type power module and manufacturing method thereof |
| WO2021068399A1 (en) * | 2019-10-12 | 2021-04-15 | 深圳第三代半导体研究院 | Stacked crimp-type power module and method for manufacture thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3166527B2 (en) | 2001-05-14 |
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