JPH08195664A - Snubber circuit of semiconductor device - Google Patents

Snubber circuit of semiconductor device

Info

Publication number
JPH08195664A
JPH08195664A JP7005350A JP535095A JPH08195664A JP H08195664 A JPH08195664 A JP H08195664A JP 7005350 A JP7005350 A JP 7005350A JP 535095 A JP535095 A JP 535095A JP H08195664 A JPH08195664 A JP H08195664A
Authority
JP
Japan
Prior art keywords
voltage
current
capacitor
snubber
resistance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7005350A
Other languages
Japanese (ja)
Other versions
JP3261911B2 (en
Inventor
Masateru Igarashi
征輝 五十嵐
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP00535095A priority Critical patent/JP3261911B2/en
Publication of JPH08195664A publication Critical patent/JPH08195664A/en
Application granted granted Critical
Publication of JP3261911B2 publication Critical patent/JP3261911B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Dc-Dc Converters (AREA)
  • Power Conversion In General (AREA)
  • Electronic Switches (AREA)

Abstract

PURPOSE: To reduce generated loss and reduce the size by providing an insulation gate type bipolar transistor(TR), a capacitor, and a resistance. CONSTITUTION: A voltage driven type thyristor turns OFF, a main current I0 is ceased, and a main power source I0 shifts to the snubber circuit 6, thereby obtaining a snubber current IS. The snubber current IS flows to a main circuit through a capacitor 2, a resistance 3, and an insulation gate type bipolar TR IGBT4. A current IIGBT flowing to the IGBT4 is generated by generating a resistance voltage VR across a resistance 3 with a resistance current IR, applying this resistance voltage VR as a gate voltage to the IGBT 4, and placing the IGBT4 in an active area to make part of the snubber current IS flow. Consequently, the snubber current IS is shunt to the IGBT4 and capacitor 2 and the current IC which flows to the capacitor 2 is less than that in the absence of the IGBT4, and the voltage rise rate of the voltage of the capacitor 2, i.e., a voltage VT applied to the voltage-driven type thyristor 1 decreases.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】この発明は、半導体装置をスイッ
チング素子として用いた電力変換装置において、この半
導体装置に加わるスパイク電圧(電圧上昇率および尖頭
値)を抑制するためのスナバ回路に関するもので、特に
ターンオフ時の安全動作領域の狭い電圧駆動形サイリス
タなどの半導体装置のスナバ回路に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a snubber circuit for suppressing a spike voltage (voltage rise rate and peak value) applied to a semiconductor device in a power converter using the semiconductor device as a switching element. In particular, the present invention relates to a snubber circuit of a semiconductor device such as a voltage drive thyristor having a narrow safe operation area at turn-off.

【0002】[0002]

【従来の技術】図4は従来の電圧駆動形サイリスタ(以
下単にサイリスタと称す)のスナバ回路と主回路を示
す。主回路は降圧チョッパ回路を例にとった。つぎにこ
の回路について説明をする。直流電源Edと電圧駆動形
サイリスタ1とダイオード8が逆直列に、ダイオード8
と並列にリアクトル9と抵抗32の直列回路がそれぞれ
接続され主回路を構成している。またダイオード81と
コンデンサ21が直列接続され、このダイオード81と
抵抗31が並列接続され構成されたスナバ回路6が電圧
駆動形サイリスタ1に接続される。この降圧チョッパ回
路は電圧駆動形サイリスタ1をオンオフさせることで出
力電力(リアクトルと抵抗とで消費する電力)を調整す
る回路である。このスナバ回路6は前記コンデンサ21
へ主電流を転流させることで、ターンオフ時に電圧駆動
形サイリスタ1に印加される電圧の上昇率および尖頭値
(跳ね上がり電圧の尖頭値)を抑制している。
2. Description of the Related Art FIG. 4 shows a snubber circuit and a main circuit of a conventional voltage drive type thyristor (hereinafter simply referred to as thyristor). The main circuit is a step-down chopper circuit as an example. Next, this circuit will be described. The DC power supply Ed, the voltage drive type thyristor 1 and the diode 8 are connected in anti-series, and the diode 8
And a series circuit of the reactor 9 and the resistor 32 are respectively connected in parallel to form a main circuit. Further, the snubber circuit 6 in which the diode 81 and the capacitor 21 are connected in series and the diode 81 and the resistor 31 are connected in parallel is connected to the voltage drive type thyristor 1. This step-down chopper circuit is a circuit that adjusts the output power (power consumed by the reactor and the resistor) by turning on and off the voltage-driven thyristor 1. This snubber circuit 6 has the capacitor 21
The main current is commutated to suppress the rise rate and peak value of the voltage applied to the voltage-driven thyristor 1 at the time of turn-off (peak value of jump voltage).

【0003】[0003]

【発明が解決しようとする課題】しかしながら、従来の
前記のようなスナバ回路6では、電圧駆動形サイリスタ
1がターンオンしたとき、コンデンサ21に蓄えられた
電荷が抵抗31を介して放電され、このときの電流値と
抵抗値の積でジュール損失が発生する。電圧駆動形サイ
リスタ1の動作周波数が10kHzと高くなるとジュー
ル損失は極めて大きくなり、抵抗の容量増大によるスナ
バ回路の大型化や装置効率の低下などの不都合が生じ
る。
However, in the conventional snubber circuit 6 as described above, when the voltage drive type thyristor 1 is turned on, the electric charge stored in the capacitor 21 is discharged through the resistor 31. Joule loss occurs at the product of the current value and the resistance value. When the operating frequency of the voltage drive type thyristor 1 becomes as high as 10 kHz, the Joule loss becomes extremely large, and the snubber circuit becomes large due to the increase of the resistance capacity, and the efficiency of the device is deteriorated.

【0004】この発明は、前記の問題点を除去し得る半
導体装置のスナバ回路を提供することを目的とする。
It is an object of the present invention to provide a snubber circuit of a semiconductor device which can eliminate the above problems.

【0005】[0005]

【課題を解決するための手段】この発明は前記目的を達
成するために、回路を開閉するスイッチング手段として
の半導体装置に加わるスパイク電圧を吸収するスナバ回
路において、前記半導体装置の高電位側となるアノード
および低電位側となるカソードにそれぞれコレクタおよ
びエミッタが接続された絶縁ゲート型バイポーラトラン
ジスタ(IGBT)と、このIGBTのコレクタ・ゲー
ト間に接続されたコンデンサと、ゲート・エミッタ間に
接続された抵抗とを有することである。
In order to achieve the above object, the present invention is a snubber circuit which absorbs a spike voltage applied to a semiconductor device as a switching device for opening and closing a circuit, and is a high potential side of the semiconductor device. An insulated gate bipolar transistor (IGBT) whose collector and emitter are connected to an anode and a cathode on the low potential side, a capacitor connected between the collector and gate of this IGBT, and a resistor connected between the gate and emitter And to have.

【0006】またIGBTのコレクタおよびゲートに定
電圧ダイオードのカソードおよびアノードをそれぞれ接
続すると一層効果的である。またこのスナバ回路を電圧
駆動形スイッチング素子に適用すると効果的である。
It is more effective to connect the cathode and anode of the constant voltage diode to the collector and gate of the IGBT, respectively. It is also effective to apply this snubber circuit to a voltage-driven switching element.

【0007】[0007]

【作用】電圧駆動形サイリスタがターンオフするとき、
電圧駆動形サイリスタに流れていた主電流はスナバ回路
に流入し、この電流でコンデンサに電荷が蓄えられ、抵
抗の両端に電圧が発生する。ターンオフ期間では流入す
る電流は一定と近似でき、そのため抵抗の両端に発生す
る電圧も一定になる。この一定電圧はIGBTのゲート
に印加され、この電圧値を適宜選ぶことでIGBTを活
性領域での動作状態にする。この活性領域のIGBTに
主電流の一部を流すことで、コンデンサに蓄えられる電
荷量を減らし、電圧駆動形サイリスタがターンオンする
ときの抵抗を介して流れる放電電流を減らし、抵抗で発
生するジュール損失を低減する。これによって、回路効
率の向上とスナバ回路の小型化が図れる。
[Operation] When the voltage drive type thyristor turns off,
The main current flowing through the voltage-driven thyristor flows into the snubber circuit, and this current causes electric charge to be stored in the capacitor, generating a voltage across the resistor. During the turn-off period, the inflowing current can be approximated to be constant, so that the voltage generated across the resistor is also constant. This constant voltage is applied to the gate of the IGBT, and by appropriately selecting this voltage value, the IGBT is brought into the operating state in the active region. By flowing a part of the main current through the IGBT in this active region, the amount of charge stored in the capacitor is reduced, the discharge current that flows through the resistor when the voltage-driven thyristor turns on is reduced, and the Joule loss that occurs in the resistor is reduced. To reduce. As a result, the circuit efficiency can be improved and the snubber circuit can be downsized.

【0008】またコンデンサに流入する電流が小さくな
るため、電圧駆動形サイリスタのアノード.カソード間
に印加される電圧の立上がり(電圧上昇率)が小さくな
り、安全動作領域(ターンオフ時の電圧と電流の軌跡を
示し、これが広いと高い電圧で大きい電流を流すことが
できる)の狭い電圧駆動形サイリスタでも破壊すること
なく、確実にターンオフできる。
Further, since the current flowing into the capacitor becomes small, the anode. The rise of the voltage applied between the cathodes (rate of voltage increase) becomes small, and the safe operation area (the locus of the voltage and current at turn-off is shown; if this is wide, a large current can flow at a high voltage) and a narrow voltage Even a drive type thyristor can be turned off without damage.

【0009】さらにコンデンサと並列に定電圧ダイオー
ドを接続すると、電圧駆動形サイリスタに過電圧が印加
されることが防止でき、さらに確実にターンオフでき
る。
Further, by connecting a constant voltage diode in parallel with the capacitor, it is possible to prevent an overvoltage from being applied to the voltage drive type thyristor, and it is possible to reliably turn off the thyristor.

【0010】[0010]

【実施例】図1はこの発明の第1実施例のスナバ回路を
図4の主回路に接続した図を示す。IGBT4のコレク
タ41・エミッタ42間に、コンデンサ2と抵抗3の直
列回路が並列に接続され、コンデンサ2と抵抗3の接続
点5とIGBT4のゲート43が接続しているスナバ回
路6が電圧駆動形サイリスタ1のアノード11・カソー
ド12間に並列に接続され、主回路と接続する。主回路
は従来例の図4と同一のため説明は省略する。
1 shows a diagram in which the snubber circuit of the first embodiment of the present invention is connected to the main circuit of FIG. The snubber circuit 6 in which the series circuit of the capacitor 2 and the resistor 3 is connected in parallel between the collector 41 and the emitter 42 of the IGBT 4 and the connection point 5 of the capacitor 2 and the resistor 3 and the gate 43 of the IGBT 4 is connected is a voltage drive type. It is connected in parallel between the anode 11 and the cathode 12 of the thyristor 1 and connected to the main circuit. The main circuit is the same as that of the conventional example shown in FIG.

【0011】図2は図1のスナバ回路を接続した電圧駆
動形サイリスタの動作を説明するための動作波形図であ
る。電圧駆動形サイリスタがターンオフし、主電流IO
が零になりスナバ回路1に主電流IO は移りスナバ電流
S となる。実際のターンオフは極めて短時間で行われ
るため、ここではターンオフ期間の現象は省略し瞬時に
主電流IO が零となるものとした。スナバ電流IS はコ
ンデンサ2と抵抗3およびIGBT4を通り主回路へ流
れだす。IGBTに流れる電流(IGBT電流IIGBT
は、抵抗電流IR で抵抗3に抵抗電圧VR が発生し、こ
の抵抗電圧VRがゲート電圧としてIGBT4に印加さ
れ、IGBT4は活性領域に入り、スナバ電流IS の一
部を流すことで生ずる。そのため、スナバ電流IS はI
GBT4とコンデンサ2に分流し、IGBT4がない場
合(従来のスナバ回路)と比べてコンデンサ2に流れる
電流(コンデンサ電流IC )は減少し、コンデンサ2の
電圧つまり電圧駆動形サイリスタ1に印加される電圧V
T の電圧上昇率(dV/dt=IC /C,C:コンデン
サ容量)が減少する。またコンデンサ2に蓄積する電荷
Qが減少するためコンデンサの電圧(VC =Q/C)つ
まり電圧駆動形サイリスタ1に印加される電圧VT も低
下する。また抵抗電流IR も少なくなり、抵抗3で発生
するジュール損失(E=RIR /2,IR :抵抗電流)
は減少する。コンデンサ電圧VC は数100Vないし千
数百V、抵抗電圧VR は数Vないし十数であり、コンデ
ンサ電圧VC が2桁程度大きいので電圧駆動形サイリス
タに印加される電圧VT はコンデンサ電圧VC とほぼ等
しい。
FIG. 2 is an operation waveform diagram for explaining the operation of the voltage drive thyristor to which the snubber circuit of FIG. 1 is connected. The voltage-driven thyristor turns off and the main current I O
Becomes zero and the main current I O moves to the snubber circuit 1 and becomes the snubber current I S. Since the actual turn-off is performed in an extremely short time, the phenomenon during the turn-off period is omitted here and the main current I O is instantly zero. The snubber current I S flows out to the main circuit through the capacitor 2, the resistor 3 and the IGBT 4. Current flowing in IGBT (IGBT current I IGBT )
The resistance voltage V R is generated in the resistor 3 by the resistance current I R , the resistance voltage V R is applied as a gate voltage to the IGBT 4, the IGBT 4 enters the active region, and a part of the snubber current I S flows. Occurs. Therefore, the snubber current I S is I
The current (capacitor current I C ) that splits between the GBT 4 and the capacitor 2 and flows in the capacitor 2 is reduced compared to the case where the IGBT 4 is not provided (conventional snubber circuit), and the voltage of the capacitor 2, that is, the voltage-driven thyristor 1 is applied. Voltage V
The voltage increase rate of T (dV / dt = I C / C, C: capacitor capacity) decreases. Further, since the charge Q accumulated in the capacitor 2 decreases, the capacitor voltage (V C = Q / C), that is, the voltage VT applied to the voltage-driven thyristor 1 also decreases. Further, the resistance current I R also decreases, and the Joule loss (E = RI R / 2, I R : resistance current) generated in the resistor 3 is generated.
Decreases. The capacitor voltage V C is several hundreds to several thousand and several hundreds V, the resistance voltage V R is several V to several tens, and since the capacitor voltage V C is large by about two digits, the voltage VT applied to the voltage drive thyristor is the capacitor voltage V It is almost equal to C.

【0012】また電圧駆動形サイリスタに印加される電
圧VT は電源電圧Edになると、電圧上昇率dV/dt
は急激に小さくなりスナバ電流IS (IC +IIGBT)が
零の時点で電源電圧Edになる。図3はこの発明の第2
実施例のスナバ回路を示す。図1のスナバ回路と異なる
点はコンデンサに並列に定電圧ダイオードを接続したこ
とである。定電圧ダイオードを接続することで電圧駆動
形サイリスタのターンオフ時にスナバ回路6のコンデン
サ2が過電圧になることを防ぎ、電圧駆動形サイリスタ
に過電圧が印加されることを防止する。
When the voltage V T applied to the voltage drive thyristor becomes the power supply voltage Ed, the voltage increase rate dV / dt.
Rapidly decreases and becomes the power supply voltage Ed when the snubber current I S (I C + I IGBT ) becomes zero. FIG. 3 shows the second aspect of the present invention.
3 shows a snubber circuit of an embodiment. The difference from the snubber circuit of FIG. 1 is that a constant voltage diode is connected in parallel with the capacitor. By connecting the constant voltage diode, it is possible to prevent the capacitor 2 of the snubber circuit 6 from being overvoltage when the voltage driving thyristor is turned off, and to prevent the overvoltage from being applied to the voltage driving thyristor.

【0013】上記のことから、IGBT4に主電流の半
分ないしそれ以上の電流をターンオフ期間(数μs)に
流すことで、安全動作領域が狭い、別の言い方をすると
許容電圧上昇率が小さい電圧駆動形サイリスタ1でも、
このスナバ回路4を接続することで許容電圧上昇率dV
/dtを従来の1/2以下に低減でき、確実にターンオ
フできる。またターンオフ時にスナバ回路6で発生する
ジュール損失を1/4以下に低減することで、スナバ回
路4の大きさを従来の1/2以下に小型化できる。
From the above, by driving a current of half or more of the main current in the IGBT 4 during the turn-off period (several μs), the safe operation area is narrow, in other words, the voltage drive with a small allowable voltage increase rate. In the thyristor 1,
By connecting this snubber circuit 4, the allowable voltage rise rate dV
/ Dt can be reduced to 1/2 or less of the conventional value, and the turn-off can be reliably performed. Further, by reducing the Joule loss generated in the snubber circuit 6 at the time of turn-off to 1/4 or less, the size of the snubber circuit 4 can be reduced to 1/2 or less of the conventional size.

【0014】またコンデンサと並列に定電圧ダイオード
を接続することで、ターンオフ時に電源電圧より跳ね上
がる電圧をカットでき、電圧駆動形サイリスタをより一
層確実にターンオフできる。
By connecting a constant voltage diode in parallel with the capacitor, the voltage jumping from the power supply voltage at the time of turn-off can be cut and the voltage-driven thyristor can be turned off more reliably.

【0015】[0015]

【発明の効果】IGBTとコンデンサおよび抵抗を有す
るスナバ回路とすることで、半導体装置のスイッチオフ
時に発生する電圧の上昇率(dV/dt)を抑制でき、
安全動作領域の狭い電圧駆動形サイリスタでも確実にタ
ーンオフできる。またスナバ回路の発生損失を低減出来
るため、スナバ回路の小型化ができる。さらにコンデン
サと並列に定電圧ダイオードを接続することで、電圧駆
動形サイリスタに印加される過電圧を防止でき、より一
層確実にターンオフできる。
By using a snubber circuit having an IGBT, a capacitor and a resistor, the rate of increase in voltage (dV / dt) generated when the semiconductor device is switched off can be suppressed,
Even a voltage-driven thyristor with a narrow safe operation area can be reliably turned off. Further, since the generated loss of the snubber circuit can be reduced, the snubber circuit can be downsized. Furthermore, by connecting a constant voltage diode in parallel with the capacitor, it is possible to prevent an overvoltage applied to the voltage drive type thyristor and turn off more reliably.

【図面の簡単な説明】[Brief description of drawings]

【図1】この発明の第1実施例のスナバ回路図FIG. 1 is a snubber circuit diagram of a first embodiment of the present invention.

【図2】図2は電圧駆動形サイリスタの動作波形図FIG. 2 is an operation waveform diagram of a voltage drive thyristor.

【図3】この発明の第2実施例のスナバ回路図FIG. 3 is a snubber circuit diagram of a second embodiment of the present invention.

【図4】従来のスナバ回路と主回路の回路図FIG. 4 is a circuit diagram of a conventional snubber circuit and a main circuit.

【符号の説明】[Explanation of symbols]

1 電圧駆動形サイリスタ 11 アノード 12 カソード 2 コンデンサ 21 コンデンサ 3 抵抗 31 抵抗 32 抵抗 4 IGBT 41 コレクタ 42 エミッタ 43 ゲート 5 接続点 6 スナバ回路 7 定電圧ダイオード 8 ダイオード 9 リアクトル IT 電圧駆動形サイリスタ電流 VT 電圧駆動形サイリスタ電圧 IS スナバ電流 IC コンデンサ電流 VC コンデンサ電圧 IIGBT IGBT電流 IR 抵抗電流 VR 抵抗電圧1 voltage-driven thyristor 11 anode 12 cathode 2 capacitor 21 capacitor 3 resistor 31 resistor 32 resistor 4 IGBT 41 collector 42 emitter 43 gate 5 connection point 6 snubber circuit 7 a constant voltage diode 8 diode 9 reactor I T voltage drive thyristor current V T the voltage drive thyristor voltage I S snubber current I C capacitor current V C capacitor voltage I IGBT IGBT current I R resistor current V R resistor voltage

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 FI 技術表示箇所 H03K 17/567 ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Office reference number FI technical display location H03K 17/567

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】回路を開閉するスイッチング手段としての
半導体装置に加わるスパイク電圧を吸収するスナバ回路
であって、前記半導体装置の高電位側となるアノードお
よび低電位側となるカソードにそれぞれコレクタおよび
エミッタが接続された絶縁ゲート型バイポーラトランジ
スタ(IGBT)と、このIGBTのコレクタ・ゲート
間に接続されるコンデンサと、ゲート・エミッタ間に接
続される抵抗とを有することを特徴とする半導体装置の
スナバ回路。
1. A snubber circuit for absorbing a spike voltage applied to a semiconductor device as switching means for opening and closing the circuit, wherein a collector and an emitter are respectively provided on an anode on a high potential side and a cathode on a low potential side of the semiconductor device. An insulated gate bipolar transistor (IGBT) connected to each other, a capacitor connected between the collector and the gate of the IGBT, and a resistor connected between the gate and the emitter of the snubber circuit of a semiconductor device. .
【請求項2】IGBTのエミッタおよびゲートに定電圧
ダイオードのカソードおよびアノードがそれぞれ接続さ
れることを特徴とする請求項1記載の半導体装置のスナ
バ回路。
2. A snubber circuit for a semiconductor device according to claim 1, wherein a cathode and an anode of a constant voltage diode are connected to an emitter and a gate of the IGBT, respectively.
【請求項3】半導体装置が電圧駆動形スイッチング素子
であることを特徴とする請求項1または2記載の半導体
装置のスナバ回路。
3. The snubber circuit for a semiconductor device according to claim 1, wherein the semiconductor device is a voltage-driven switching element.
JP00535095A 1995-01-18 1995-01-18 Snubber circuit of semiconductor device Expired - Lifetime JP3261911B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP00535095A JP3261911B2 (en) 1995-01-18 1995-01-18 Snubber circuit of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP00535095A JP3261911B2 (en) 1995-01-18 1995-01-18 Snubber circuit of semiconductor device

Publications (2)

Publication Number Publication Date
JPH08195664A true JPH08195664A (en) 1996-07-30
JP3261911B2 JP3261911B2 (en) 2002-03-04

Family

ID=11608755

Family Applications (1)

Application Number Title Priority Date Filing Date
JP00535095A Expired - Lifetime JP3261911B2 (en) 1995-01-18 1995-01-18 Snubber circuit of semiconductor device

Country Status (1)

Country Link
JP (1) JP3261911B2 (en)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003338239A (en) * 2002-04-12 2003-11-28 Lg Industrial Syst Co Ltd Hybrid dc electromagnetic contactor
JP2009055692A (en) * 2007-08-27 2009-03-12 Diamond Electric Mfg Co Ltd Snubber circuit and power conversion circuit having the same
JP2010220471A (en) * 1999-07-22 2010-09-30 Mks Instruments Inc Power supply having protection circuit
CN103501109A (en) * 2013-10-25 2014-01-08 北京交通大学 Converter bridge arm circuit with energy active feedback absorption loop and converter
WO2014061114A1 (en) * 2012-10-17 2014-04-24 株式会社日立製作所 Power conversion device
WO2015174107A1 (en) * 2014-05-16 2015-11-19 シャープ株式会社 Composite semiconductor device
US9692226B2 (en) 2012-08-23 2017-06-27 General Electric Technology Gmbh Circuit interruption device
US9813054B2 (en) 2013-06-14 2017-11-07 General Electric Technology Gmbh Semiconductor switching string
CN107800305A (en) * 2016-09-01 2018-03-13 富士电机株式会社 Semiconductor device and power inverter
CN113794357A (en) * 2021-07-29 2021-12-14 广东美的白色家电技术创新中心有限公司 Fault processing circuit, chip, intelligent power module and household appliance

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010220471A (en) * 1999-07-22 2010-09-30 Mks Instruments Inc Power supply having protection circuit
JP2003338239A (en) * 2002-04-12 2003-11-28 Lg Industrial Syst Co Ltd Hybrid dc electromagnetic contactor
US7079363B2 (en) 2002-04-12 2006-07-18 Lg Industrial Systems Co., Ltd. Hybrid DC electromagnetic contactor
JP2009055692A (en) * 2007-08-27 2009-03-12 Diamond Electric Mfg Co Ltd Snubber circuit and power conversion circuit having the same
US9692226B2 (en) 2012-08-23 2017-06-27 General Electric Technology Gmbh Circuit interruption device
WO2014061114A1 (en) * 2012-10-17 2014-04-24 株式会社日立製作所 Power conversion device
JPWO2014061114A1 (en) * 2012-10-17 2016-09-05 株式会社日立製作所 Power converter
US9813054B2 (en) 2013-06-14 2017-11-07 General Electric Technology Gmbh Semiconductor switching string
US9819337B2 (en) 2013-06-14 2017-11-14 General Electric Technology Gmbh Semiconductor switching circuit
CN103501109A (en) * 2013-10-25 2014-01-08 北京交通大学 Converter bridge arm circuit with energy active feedback absorption loop and converter
WO2015174107A1 (en) * 2014-05-16 2015-11-19 シャープ株式会社 Composite semiconductor device
JPWO2015174107A1 (en) * 2014-05-16 2017-04-20 シャープ株式会社 Composite type semiconductor device
CN107800305A (en) * 2016-09-01 2018-03-13 富士电机株式会社 Semiconductor device and power inverter
CN107800305B (en) * 2016-09-01 2020-11-03 富士电机株式会社 Power conversion device
CN113794357A (en) * 2021-07-29 2021-12-14 广东美的白色家电技术创新中心有限公司 Fault processing circuit, chip, intelligent power module and household appliance

Also Published As

Publication number Publication date
JP3261911B2 (en) 2002-03-04

Similar Documents

Publication Publication Date Title
US5107151A (en) Switching circuit employing electronic devices in series with an inductor to avoid commutation breakdown and extending the current range of switching circuits by using igbt devices in place of mosfets
US5123746A (en) Bridge type power converter with improved efficiency
US5200878A (en) Drive circuit for current sense igbt
US6426666B1 (en) Diode-assisted gate turn-off thyristor
JP3812353B2 (en) Semiconductor power converter
US7368972B2 (en) Power transistor control device
US7315439B2 (en) Method and circuit arrangement for limiting an overvoltage
US9509299B2 (en) Apparatus and method for control of semiconductor switching devices
GB2324664A (en) Protection of half-bridge driver IC against negative voltage failures
EP1235334B1 (en) Gate driver for thyristor
JPH0947015A (en) Driver circuit for self-extinguishing semiconductor device
JP3261911B2 (en) Snubber circuit of semiconductor device
US6856520B2 (en) Double sided IGBT phase leg architecture and clocking method for reduced turn on loss
US4415963A (en) FET commutated current-FED inverter
JP7595785B2 (en) DRIVE CIRCUIT FOR POWER SEMICONDUCTOR DEVICE, POWER SEMICONDUCTOR MODULE, AND POWER CONVERSION DEVICE
KR100385789B1 (en) Gate driving circuit of power semiconductor switch
GB2053606A (en) Improvements in and relating to semiconductor switching circuits
Klaka et al. A family of reverse conducting gate commutated thyristors for medium voltage drive applications
JPH10209832A (en) Semiconductor switch circuit
JPS60107917A (en) Compound semiconductor switch
JP3558324B2 (en) Gate drive device of voltage drive type device
KR970006428Y1 (en) Over Current Protection Circuit
Li et al. A novel approach for realizing hard-driven gate-turn-off thyristor
JPS5914356A (en) Gate controller for gate turn-off thyristor
JPH08130866A (en) GTO gate circuit

Legal Events

Date Code Title Description
R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20071221

Year of fee payment: 6

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20081221

Year of fee payment: 7

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20081221

Year of fee payment: 7

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313113

S533 Written request for registration of change of name

Free format text: JAPANESE INTERMEDIATE CODE: R313533

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20081221

Year of fee payment: 7

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20081221

Year of fee payment: 7

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20091221

Year of fee payment: 8

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313111

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20091221

Year of fee payment: 8

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20091221

Year of fee payment: 8

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20101221

Year of fee payment: 9

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20101221

Year of fee payment: 9

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20111221

Year of fee payment: 10

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20111221

Year of fee payment: 10

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313111

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20111221

Year of fee payment: 10

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20121221

Year of fee payment: 11

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20121221

Year of fee payment: 11

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20131221

Year of fee payment: 12

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

EXPY Cancellation because of completion of term