JPH081986B2 - Manufacturing method of wiring board - Google Patents
Manufacturing method of wiring boardInfo
- Publication number
- JPH081986B2 JPH081986B2 JP24712687A JP24712687A JPH081986B2 JP H081986 B2 JPH081986 B2 JP H081986B2 JP 24712687 A JP24712687 A JP 24712687A JP 24712687 A JP24712687 A JP 24712687A JP H081986 B2 JPH081986 B2 JP H081986B2
- Authority
- JP
- Japan
- Prior art keywords
- copper
- wiring
- insulating resin
- wiring conductor
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Manufacturing Of Printed Wiring (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は配線板,特にチップオンボード化に適した高
密度配線板の製造法に関する。The present invention relates to a method for manufacturing a wiring board, particularly a high-density wiring board suitable for chip-on-board.
LSIチップの高集積化,高速化に伴ない配線板にも高
密度配線や低誘電率化等の要求が強く現われている。特
に最近ではチップ〜チップ間の配線長を短縮する目的で
裸のチップを直接基板に搭載するチップオンボード化が
望まれている。安価で,量産性の高いプラスチックス製
でのチップオンボード化に適した配線板の製造法として
は,SHS板等の保持基板上に銅層を設け,その上に配線導
体とポリイミド等の耐熱樹脂よりなる多層配線を形成し
た後,保持基板を剥離して得られる多層配線基板と他の
一般の積層板を基板した配線板基板とを積層一体化した
後,必要な回路形成加工を行う方法がある。As LSI chips become more highly integrated and faster, there are strong demands for wiring boards with high-density wiring and low dielectric constant. In particular, recently, there has been a demand for a chip-on-board in which a bare chip is directly mounted on a substrate for the purpose of shortening the wiring length between chips. As a method of manufacturing a wiring board that is inexpensive and has high mass productivity and is suitable for chip-on-boarding, a copper layer is provided on a holding substrate such as an SHS board, and a wiring conductor and a heat-resistant material such as polyimide are formed on the copper layer. A method of performing necessary circuit forming processing after a multilayer wiring board obtained by peeling a holding substrate after forming a multilayer wiring made of a resin and a wiring board substrate on which another general laminated board is laminated and integrated There is.
この方法によれば,真空蒸着やスパッタで必要となる
真空下(減圧下)において材料(積層板)からの放出ガ
スがないため,配線導体を容易に形成でき,高密度な配
線板が製造できる。According to this method, since no gas is released from the material (laminated plate) under the vacuum (under reduced pressure) required for vacuum vapor deposition or sputtering, a wiring conductor can be easily formed and a high-density wiring board can be manufactured. .
しかし,この配線板の製造法において,次の問題点が
ある。保持基板にSUS板を使用し,この表面に銅層を設
け,この上に必要な配線を成形し,ポリイミド樹脂を塗
布,硬化する工程において,ポリイミド樹脂の硬化温度
が通常300〜400℃であるため,SUS板上の銅がポリイミド
硬化時に熱拡散し,SUS板と銅の密着力が高くなる。この
ため多層配線形成後,SUS板と銅層界面を容易に分離でき
ないことがあった。However, this wiring board manufacturing method has the following problems. A SUS plate is used as the holding substrate, a copper layer is provided on this surface, the necessary wiring is formed on this, and the curing temperature of the polyimide resin is usually 300-400 ℃ in the process of applying and curing the polyimide resin. Therefore, the copper on the SUS plate is thermally diffused when the polyimide is cured, and the adhesion between the SUS plate and the copper is increased. For this reason, the interface between the SUS plate and the copper layer may not be easily separated after the multilayer wiring is formed.
本発明は,保持基板上に銅層を設け,その上に配線導
体とポリイミド等の耐熱樹脂よりなる多層配線を形成し
た後,容易に保持基板を剥離することができる配線板の
製造法を提供するものである。The present invention provides a method for manufacturing a wiring board in which a copper layer is provided on a holding substrate, a wiring conductor and multilayer wiring made of a heat-resistant resin such as polyimide are formed on the copper layer, and then the holding substrate can be easily peeled off. To do.
本発明は,少なくとも表面がガラス質である保持基板
上に銅層を設け,その上に配線導体とポリイミド等の絶
縁樹脂より成る多層配線を形成した後,保持基板を剥離
して得られる多層配線基板と他の配線基板とを積層一体
化した後,必要な回路形成加工を行うものである。The present invention provides a multilayer wiring obtained by providing a copper layer on a holding substrate having at least a glass surface, forming a multilayer wiring made of a wiring conductor and an insulating resin such as polyimide on the holding substrate, and then peeling the holding substrate. After the board and other wiring boards are laminated and integrated, necessary circuit forming processing is performed.
少なくとも表面ガラス質である保持基板としては,ガ
ラス基板,ガラス質を表面に形成した基板がある。As the holding substrate having at least a glassy surface, there are a glass substrate and a substrate having a glassy surface.
ガラス基板としてはソーダ石灰ガラス,鉛アルカリガ
ラス,硼珪酸ガラス,バリウム硼珪酸ガラス,アルミノ
珪酸ガラス,96%珪酸ガラス,石英ガラス等が使用でき
る。As the glass substrate, soda lime glass, lead alkali glass, borosilicate glass, barium borosilicate glass, aluminosilicate glass, 96% silicate glass, quartz glass, etc. can be used.
ガラス質を表面に形成した基板としては,鉄,鉄合
金,アルミニウム,アルミニウム合金,銅,銅合金,ニ
ッケル,ニッケル合金,クロム,クロム合金,セラミッ
クス等の基板表面に,ソーダ石灰ガラス,鉛アルカリガ
ラス,硼酸珪酸ガラス,バリウム珪酸ガラス,アルミナ
珪酸ガラス,96%珪酸ガラス,石英ガラスをコーティン
グしたものが使用できる。Substrates with glassy surfaces are iron, iron alloys, aluminum, aluminum alloys, copper, copper alloys, nickel, nickel alloys, chromium, chromium alloys, ceramics, etc., soda lime glass, lead alkali glass , Those coated with borate silicate glass, barium silicate glass, alumina silicate glass, 96% silicate glass, and quartz glass can be used.
以下図面に基いて本発明の一実施例について説明す
る。An embodiment of the present invention will be described below with reference to the drawings.
第1図においてガラス基板1に真空抵抗過熱蒸着法,
電子ビーム蒸着法,スパッタ法,無電解めっき法により
銅層2を形成する。この際必要であれば,電気銅めっき
を併用してもよい。次に銅層2の表面に感光性レジスト
フィルムをラミネートする方法又は液状の感光性レジス
トを塗布後,乾燥すること等により,レジスト層を形成
し,露光,現像することによりレジストパターンを形成
し,電気銅めっきあるいは無電解銅めっきでレジストが
ない部分に銅めっきを形成し,レジスト剥離して,第2
図3のような層間接続用金属柱を形成する。ついで液状
ポリイミドを塗布後硬化する方法又はBステージポリイ
ミドフィルムをラミネート後硬化する方法によりポリイ
ミド層4を設けた後,ポリイミドを機械的,物理的,化
学的に平坦化し,層間接続柱を第3図のように表面に露
出させる。次に第4図5に示すような配線導体を形成す
る。形成法としては ポリイミド層および露出した層間接続柱表面に真空
抵抗加熱蒸着法,電子ビーム蒸着法,スパッタ法,無電
解めっき法,あるいはこれらと電気めっき法との併用で
配線導体を堆積し,その後配線となる箇所にレジストパ
ターンを設けて不要な導体をエッチングする方法,ある
いは ポリイミド層および露出した層間接続金属柱表面に
真空抵抗加熱蒸着法,電子ビーム蒸着法,スパッタ法,
無電解めっき法等により配線導体を堆積し,その後配線
とならない箇所にレジストパターンを設けて,無電解め
っき又は電気めっきで配線導体を厚付けした後,レジス
トを剥離して不要部分の導体をエッチングする方法があ
る。In FIG. 1, a vacuum resistance heating vapor deposition method is applied to the glass substrate 1,
The copper layer 2 is formed by the electron beam evaporation method, the sputtering method, and the electroless plating method. At this time, electrolytic copper plating may be used together if necessary. Next, a resist layer is formed by a method of laminating a photosensitive resist film on the surface of the copper layer 2 or by applying a liquid photosensitive resist and then drying, and a resist pattern is formed by exposing and developing, The copper plating is formed on the part where there is no resist by electrolytic copper plating or electroless copper plating, the resist is peeled off, and the second
A metal column for interlayer connection as shown in FIG. 3 is formed. Then, after the polyimide layer 4 is provided by a method of applying liquid polyimide and then curing it or a method of laminating and curing a B-stage polyimide film, the polyimide is mechanically, physically and chemically planarized, and the interlayer connection column is shown in FIG. To expose it to the surface. Next, a wiring conductor as shown in FIG. 4 is formed. As a forming method, a wiring conductor is deposited on the surface of the polyimide layer and the exposed interlayer connection column by vacuum resistance heating vapor deposition method, electron beam vapor deposition method, sputtering method, electroless plating method, or a combination of these and electroplating method, and thereafter. A method of etching unnecessary conductors by providing a resist pattern in the area to be the wiring, or vacuum resistance heating evaporation method, electron beam evaporation method, sputtering method on the surface of the polyimide layer and the exposed interlayer connection metal pillar,
A wiring conductor is deposited by electroless plating, etc., and then a resist pattern is provided in a place where wiring is not formed. After thickening the wiring conductor by electroless plating or electroplating, the resist is peeled off to etch the unnecessary portion of the conductor. There is a way to do it.
このような配線導体材料としては望ましくは銅である
が,クロム,ニッケル,金などを併用してもよい。この
後2図〜第4図の工程を必要回数繰り返して,第5図に
示す多層化構造とした後,ガラス基板1を機械的に(ガ
ラス基板と銅層の間にガラス基板と銅層を剥離する力を
加えて)剥離して,第6図に示す片面銅箔ポリイミド多
層配線基板6を得る。この片面銅箔ポリイミド多層配線
基板6はガラス基板1の両側に同時に形成してもよい。Copper is preferably used as such a wiring conductor material, but chromium, nickel, gold or the like may be used together. After that, the steps of FIGS. 2 to 4 are repeated a necessary number of times to form the multilayer structure shown in FIG. 5, and then the glass substrate 1 is mechanically (a glass substrate and a copper layer are provided between the glass substrate and the copper layer). Peeling is performed (by applying a peeling force) to obtain a single-sided copper foil polyimide multilayer wiring board 6 shown in FIG. The single-sided copper foil polyimide multilayer wiring board 6 may be formed on both sides of the glass substrate 1 at the same time.
その後片面銅箔ポリイミド多層配線基板6をプリプレ
グ7を介して,電源層接地層をあらかじめ形成した回路
形成済み銅張積層板8と第7図のように配置し,加熱加
圧することにより積層体を得る。After that, the single-sided copper foil polyimide multilayer wiring board 6 is arranged via a prepreg 7 with a circuit-formed copper clad laminate 8 in which a power source layer and a ground layer are previously formed as shown in FIG. obtain.
プリプレグ7には,ガラス布,ケブラー布,クォーツ
布にポリエステル樹脂,エポキシ樹脂,ポリイミド樹脂
を含浸させ,Bステージ状態まで硬化させたものを使用す
ることができる。また,Bステージポリイミドフィルムで
あってもよい。回路形成済み銅張積層板8には前述した
プリプレグ7の材料を用いた積層板,あるいはメタルコ
ア銅張積層板でもよい。この際メタルの材質としては
銅,銅合金、アルミ,アルミ合金,鉄,鉄合金またはこ
れらをクラッド化したものでもよい。更に,コア材質と
してセラミック基板,ほうろう基板等の無材質基板でも
良い。そして第8図のように必要な箇所にドリル等でス
ルーホール9を形成し,無電解めっきまたは無電解めっ
きと電気めっきの併用でスルーホール内と積層体表面に
銅めっき層を形成した後,必要な箇所にレジストパター
ンを形成して不要部分の銅をエッチングすることにより
第8図に示す配線板が得られる。As the prepreg 7, glass cloth, Kevlar cloth, or quartz cloth impregnated with polyester resin, epoxy resin, or polyimide resin and cured to the B stage state can be used. It may also be a B-stage polyimide film. The circuit-formed copper clad laminate 8 may be a laminate using the material of the prepreg 7 described above or a metal core copper clad laminate. At this time, the material of the metal may be copper, copper alloy, aluminum, aluminum alloy, iron, iron alloy or clad of these. Further, a non-material substrate such as a ceramic substrate or an enamel substrate may be used as the core material. Then, as shown in FIG. 8, through holes 9 are formed in necessary places by a drill or the like, and after electroless plating or a combination of electroless plating and electroplating to form a copper plating layer in the through holes and on the surface of the laminate, A wiring pattern shown in FIG. 8 is obtained by forming a resist pattern at a necessary portion and etching copper in an unnecessary portion.
また,スルーホール9を形成した後,スルーホール内
と積層体表面に無電解めっきまたは無電解めっきと電気
めっきの併用で銅めっき層を形成した後,最終的に導体
を必要としない箇所にレジストパターンを形成し,レジ
ストパターンがない部分に銅,ニッケル,金を順次ある
いはニッケル,金を順次,あるいは銅はんだを順次,あ
るいははんだを無電解めっきまたは電気めっきで堆積
し,レジスト剥離後,不要の銅めっき層をエッチングす
る方法を用いてもよい。In addition, after forming the through hole 9, a copper plating layer is formed in the through hole and on the surface of the laminated body by electroless plating or a combination of electroless plating and electroplating, and finally a resist is applied to a portion where a conductor is not required. After forming a pattern and depositing copper, nickel, gold in sequence, nickel, gold in sequence, copper solder in sequence, or solder on electroless plating or electroplating on the part where there is no resist pattern. A method of etching the copper plating layer may be used.
本発明に於ては保持基板にガラス基板あるいは表面が
ガラス質で形成された基板を用いるため,300〜400℃の
高温熱処理を行っても保持基板上に形成した銅が,ガラ
ス中へ拡散せず,ガラスと銅の適度な密着性が構造工程
中保持され,保持基板上に形成した多層配線基板を容易
に剥離することができる。In the present invention, since a glass substrate or a substrate whose surface is made of glass is used as the holding substrate, the copper formed on the holding substrate is not diffused into the glass even after high temperature heat treatment at 300 to 400 ° C. Instead, the appropriate adhesion between glass and copper is maintained during the structure process, and the multilayer wiring board formed on the holding board can be easily peeled off.
第1図〜第8図は本発明による配線板の製造工程を示す
断面図である。 符号の説明 1:ガラス基板 2:銅層 3:層間接続金属柱 4:ポリイミド 5:配線導体 6:片面銅箔ポリイミド多層配線基板 7:プリプレグ 8:回路形成済み銅張積層板 9:スルーホール 10:スルーホールめっき1 to 8 are cross-sectional views showing a manufacturing process of a wiring board according to the present invention. References 1: Glass substrate 2: Copper layer 3: Interlayer connection metal pillar 4: Polyimide 5: Wiring conductor 6: Single-sided copper foil Polyimide multilayer wiring board 7: Prepreg 8: Circuit-formed copper clad laminate 9: Through hole 10 : Through hole plating
Claims (1)
持基板上に銅層を設け、 (B)銅層上めっきレジストパターンを形成し、めっき
により層間接続用金属柱を形成し、 (C)めっきレジストパターンを除去し、全面に絶縁樹
脂層を形成し、該絶縁樹脂表面を除去し層間接続用金属
柱の頭部を露出させ、 (D)層間接続用金属柱の頭部と接続した配線導体を形
成し、 (E)配線導体上に配線導体と接続し頭部が露出した層
間接続用金属柱および層間接続用金属柱の露出した頭部
以外の箇所に絶縁樹脂層を形成し、 (F)前記(D)(E)の工程を必要回数繰り返すこと
により配線導体と絶縁樹脂より成る多層配線を形成し、 (G)層間接続用金属柱の頭部と接続した配線導体を形
成し、 (F)配線導体上の全面に絶縁樹脂層を形成し、 (H)保持基板を剥離し得られる多層配線基板の保持基
板を剥離した面と反対側の面である絶縁樹脂層の面と、
回路形成済み銅張り積層板の回路形成面とを向かい合わ
せてプリブレグを介して多層配線基板と回路形成済み銅
張り積層板とを積層一体化し、 (I)スルーホールの形成、スルーホール内めっき層の
形成、スルーホール部及び多層基板と回路形成済み銅張
り積層板との積層体表面の必要な箇所にレジストパター
ン形成し不要部分の金属を除去する回路形成加工を行う ことを特徴とする配線板の製造法。1. (A) A copper layer is provided on a holding substrate having at least a glass surface, (B) a plating resist pattern on the copper layer is formed, and metal columns for interlayer connection are formed by plating. ) The plating resist pattern is removed, an insulating resin layer is formed on the entire surface, the insulating resin surface is removed to expose the heads of the metal columns for interlayer connection, and (D) the heads of the metal columns for interlayer connection are connected. A wiring conductor is formed, and (E) an insulating resin layer is formed on a portion other than the exposed head portion of the metal pillar for interlayer connection and the metal pillar for interlayer connection, which is connected to the wiring conductor on the wiring conductor and the head is exposed, (F) The steps (D) and (E) are repeated a required number of times to form a multi-layered wiring made of a wiring conductor and an insulating resin, and (G) a wiring conductor connected to the head of the interlayer connecting metal column. , (F) An insulating resin layer is formed on the entire surface of the wiring conductor, (H) a surface of the insulating resin layer, which is a surface of the multilayer wiring board obtained by peeling the holding substrate, the surface being opposite to the surface from which the holding substrate is peeled
The multilayer wiring board and the circuit-formed copper-clad laminate are laminated and integrated by facing the circuit-formed surface of the circuit-formed copper-clad laminate through a prepreg, and (I) through-hole formation, through-hole plating layer A wiring board characterized by forming a resist pattern on a required portion of the surface of a laminated body of a multilayer board and a circuit-formed copper-clad laminate, and removing metal in an unnecessary portion. Manufacturing method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24712687A JPH081986B2 (en) | 1987-09-30 | 1987-09-30 | Manufacturing method of wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24712687A JPH081986B2 (en) | 1987-09-30 | 1987-09-30 | Manufacturing method of wiring board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6489593A JPS6489593A (en) | 1989-04-04 |
| JPH081986B2 true JPH081986B2 (en) | 1996-01-10 |
Family
ID=17158816
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24712687A Expired - Lifetime JPH081986B2 (en) | 1987-09-30 | 1987-09-30 | Manufacturing method of wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH081986B2 (en) |
-
1987
- 1987-09-30 JP JP24712687A patent/JPH081986B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6489593A (en) | 1989-04-04 |
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