JPH08201428A - Semiconductor device inspecting jig - Google Patents

Abstract

PURPOSE: To improve the testing mechanical accuracy of a semiconductor device inspecting jig by constituting the jig of three parts, two substrates and one intermediate body, which are independently separated from each other at every function. CONSTITUTION: The probe group 11 of a substrate 1 is directly brought into contact and is arranged in corresponding to the terminal group of an object to be inspected and a connecting terminal group 13 is arranged in corresponding to the connecting terminal group 21 of another substrate 2. A circuit conductor group 12 is designed so that the group 12 can connect the probe group 11 to the terminal group 13. The connecting terminal group 21 is arranged in corresponding to the pattern of the terminal group 13 and a connecting terminal group 23 is arranged in corresponding to the input-out pins of an inspecting device. A circuit terminal group 22 is designed so that the group 22 can connect the terminal groups 21 and 23 to each other. In other words, the size of the substrate 1 is reduced by designing the whole circuit of the inspecting jig so that the terminal groups 13 and 21 can be brought nearer to the terminal group of the object to be inspected as much as possible and the probe testing mechanical accuracy of the jig can be improved by constituting the jig of a material which is not deformed much by heat.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the structure of a semiconductor device inspection jig.

[0002]

2. Description of the Related Art A probe test is performed as an intermediate inspection for manufacturing a semiconductor device such as a large scale integrated circuit (LSI). As a recent tendency of this test, the number of inspection methods in which an operation check is performed while applying a temperature to a specimen is increasing. This is intended to pick up temperature-dependent defects and improve the yield in the final test process. On the other hand, due to the remarkable high performance and multi-functionality of semiconductor devices in recent years, there is a tendency that the area of the specimen is enlarged, the number of test points is increased, and the point area is miniaturized. These trends severely demand improvements in electrical and mechanical testing accuracy.

By the way, an inspection jig 0 for a probe test called a probe card or a probe board is
It has the structure shown in FIG. That is, a probe pin 01 made of a printed wiring board having a glass fiber cloth epoxy resin or a glass fiber cloth polyimide resin as a base 04 and made of tungsten copper, beryllium copper or the like at a predetermined position.
Is set up. On the opposite surface of the probe, a connection terminal 03 for connection with the inspection device is provided, and the probe and the connection terminal are connected by a circuit conductor 02. Recently, in order to improve the mechanical accuracy of testing, the probe pin length, that is, the connection distance between the specimen and the inspection jig tends to be short. As an ultimate example, a method of directly connecting an inspection jig to a test point without using a probe pin is being studied.

[0004]

However, since the above-mentioned base material is used for the printed wiring board which is the main body of the inspection jig, the thermal deformation of the inspection jig itself and the thermal expansion of the specimen (mainly silicon) are caused. There is an unavoidable difference in volume. On the other hand, examples of substrates having excellent dimensional stability include ceramic substrates and metal core substrates, but there is no example adopted as an inspection jig because of problems such as the cost and the limitation of the manufacturable size.

An object of the present invention is to provide a semiconductor device inspecting jig which can improve the mechanical accuracy of testing while keeping the cost low.

[0006]

FIG. 2 schematically shows a jig for inspecting a semiconductor device according to the present invention. It is composed of three parts that are separated and independent for each function. The first part is the part that contacts the specimen and controls the exchange of electrical signals (substrate 1), the second is the part that is connected to the inspection device and controls the exchange of electrical signals (the substrate 2),
Third is the part that controls the connection between the substrate 1 and the substrate 2 (intermediate 3)
Is.

The probe group 11 of the substrate 1 is in direct contact with the sample, and the array thereof corresponds to the terminal group of the sample, and the connection terminal group 13 corresponds to the connection terminal group 21 of the substrate 2. The circuit conductor group 12 is designed to connect the connection terminal groups 11 and 13. The connection terminal group 21 is the connection terminal group 13
The connection terminal group 23 has an array corresponding to the input / output pins of the inspection apparatus. The circuit conductor group 22 is designed to connect the connection terminal groups 21 and 23. That is, by designing the circuit of the entire inspection jig so that the arrangement of the connection terminal groups 13 and 21 is as close as possible to that of the sample, the entire substrate 1 can be downsized.

As described above, by adopting the structure in which the sample and the test device are individually handled, the size of the substrate 1 can be reduced, and the conventional jig structure has difficulty in increasing the size. It is possible to adopt a base material based on ceramics, a metal core, quartz or the like for the substrate 1. By the way, a method of dividing a substrate for the purpose of improving the commonality of burn-in substrates is disclosed in Japanese Patent Laid-Open No. 4-305174,
And JP-A-3-10175. The present invention provides a connection method between divided boards, which is essentially the content of the present invention of reducing the size of the board 1 and specializing the material thereof to improve the mechanical accuracy of the probe test. Different to

As the material 14 of the substrate 1, alumina (A
A ceramic substrate based on a material selected from 1 ₂ O ₃ ), silicon carbide (SiC), aluminum nitride (AlN) and beryllia (BeO) is suitable. Further, a fiber selected from a metal core substrate having therein a metal layer selected from Invar (Fe-Ni 36% alloy) and molybdenum, quartz (SiO ₂ ), glass containing 60% or more of quartz, and aromatic polyamide. A substrate or the like having a cloth or a non-woven fabric inside is also suitable for this purpose. Quartz (Si
Glasses containing 60% or more of O ₂ ) and quartz are available as Q glass and T glass, respectively. Epoxy resin base material and prepreg reinforced with T glass fiber cloth are MCL-E-679 (L), GEA-679N
(L) (trade name, manufactured by Hitachi Chemical Co., Ltd.). Aromatic polyamide fiber cloth is available as Kevlar (trade name, manufactured by DuPont Toray), and its non-woven fabric is available as Technora (trade name, Teijin). The base resin used here does not matter what kind of material is used, and a normal resin material used in printed wiring boards can be used. For example, epoxy resin, polyimide resin, bismaleimide triazine (BT) resin, polyphenylene ether (PPE) resin, fluororesin, etc. are suitable.

The probe 11 of the substrate 1 is formed by soldering a pin made of tungsten copper or beryllium copper to a circuit conductor as described above, or a three-layer structure of carrier copper / nickel / phosphorus intermediate layer / wiring conductor layer. The metal foil can be used to form bumps by etching, or the bumps can be formed by a general method such as bumping. However, in any of the methods, in order to make uniform and accurate contact with all test points of the sample, it is necessary to pay sufficient attention to the dimensional accuracy and position of the probe when forming the probe.

It is not necessary to use the substrate 2 specially designed for this purpose, and a general ordinary printed wiring board can be used. It is preferable that the structure of the intermediate body 3 is such as to prevent electrical interference between signal lines due to the characteristics of inspection. That is, the connection distance between the substrate 1 and the substrate 2 is 10
When the structure is less than 10 mm, or when the connection distance between the substrate 1 and the substrate 2 is 10 mm or more, it is preferable that the signal lines are shielded and the characteristic impedance is constant, for example, a coaxial structure capable of maintaining 50Ω. . Connection distance 10
An elastic connector such as PCR (trade name of Nippon Rubber Co., Ltd.) or
A method of connecting via a bumped film, for example, ASMAT (trade name, manufactured by Nitto Denko Corporation) is effective.

The material of the conductor circuit is preferably copper, which can be easily bonded to various resins and has excellent electric conductivity. Further, in order to prevent deterioration due to oxidation or the like, the surface of the conductor circuit may be covered with a thin film of various metals such as solder, nickel and gold.
The thickness and width of the circuit conductor are not specified.

[0013]

The mechanical accuracy of the probe test can be improved by separating and downsizing the probe mounting portion of the semiconductor device inspecting jig and constructing it from a material having a small amount of thermal deformation.

[0014]

The preferred embodiments of the present invention will be described below. 3 and 4 show an example of the substrate 1, FIG. 5 shows an example of the substrate 2, and FIG. 6 shows an example of the intermediate 3.

Example 1 A substrate 1 shown in FIG. 3 having a bump-shaped probe group 4, a connection terminal group 5, and a circuit conductor group 6 was produced by the following procedure.
T glass fiber cloth epoxy resin prepreg GEA-679
N (L) (manufactured by Hitachi Chemical Co., Ltd., trade name), a copper layer (5 μm) to be a circuit, an intermediate layer (0.18 μm) made of 2% phosphorus-nickel, and a copper layer (15 to be a bump on the surface).
a copper foil having a three-layer structure made of (μm) so that the copper layer serving as a circuit is in contact with the prepreg, and the pressure is 2.94 MPa.
(30 kg / cm ² ), the temperature was set to 175 ° C., the molding and integration were performed for 65 minutes, and drill holes were formed at predetermined positions to connect the front and back circuit layers. Next, an etching resist H-K450 (trade name, manufactured by Hitachi Chemical Co., Ltd.) is formed in a shape to be bumps, and a copper layer to be bumps up to an intermediate layer made of 2% phosphorus-nickel is an alkaline etching solution. Etching solution for A process (made by Soltex,
(Trade name) is selectively removed by etching, the etching resist is removed by stripping, and the exposed intermediate layer made of 2% phosphorus-nickel is nitric acid 200 g / l, hydrogen peroxide solution 10
After removing by etching with an etching solution containing ml / l, malic acid 100 g / l and benzotriazole 5 g / l, electroless copper plating and electrolytic copper plating are 30 μm.
Then, the necessary conductors were formed on the inner wall of the hole and the surface. Then, the etching resist H-K450 is formed into a circuit shape.
(Hitachi Chemical Co., Ltd., trade name) was formed, the copper layer to be a circuit was selectively removed by etching, the above etching resist was peeled off, and external processing was performed to obtain a substrate 1. Next, the substrate 2 shown in FIG. 5 having the connection terminal groups 7 and 8 and the circuit copper layer group 9 was produced by the following procedure. Inner layer conductor circuits 10 were formed on both surfaces of a glass fiber cloth epoxy resin copper-clad laminate MCL-E-679 (trade name, manufactured by Hitachi Chemical Co., Ltd.) to prepare an inner layer circuit board. In order to improve the adhesion between the inner layer circuit conductor and the resin, the surface of the circuit conductor was treated with copper oxide and then reduced with an alkaline solution containing formaldehyde. Epoxy resin adhesive sheet AS-102 (manufactured by Hitachi Chemical Co., Ltd., trade name) is applied on the surface thereof, pressure 4.9 N / m, temperature 100 ° C., speed 3 m.
/ Lamination conditions, using a numerically controlled wire machine, on this adhesive sheet φ0.1 insulation wire HAW-
216C (manufactured by Hitachi Cable, Ltd., trade name) was laid and a necessary circuit pattern was formed. A prepreg GEA-679N (manufactured by Hitachi Chemical Co., Ltd., trade name) and a 18 μm copper foil were laid on the surface of this substrate, and a pressure of 2.9 M was applied.
Molding and integration were performed under conditions of Pa, temperature of 175 ° C., and time of 65 minutes, punching, electroless copper plating, and electrolytic copper plating. Then, the etching resist H-K4 is formed into a required shape.
50 (made by Hitachi Chemical Co., Ltd., product name) was formed,
The substrate 2 was obtained by performing selective etching, peeling and removing the etching resist, and performing external shape processing. next,
The intermediate body 3 shown in FIG. 6 having the coaxial structure including the connection terminal group 15 and the circuit conductor group was produced by the following procedure. Glass fiber cloth epoxy resin copper-clad laminate MCL-E-67 (Hitachi Chemical Co., Ltd., trade name) is punched in the necessary places, electroless copper plating is performed on the entire surface, and electrolytic copper is used at the required places.
Four pieces were prepared by solder plating, etching, and external processing. The bushings 16 made of tetrafluoroethylene having a through hole at the center are set in the holes plated with each other so that they are in close contact with each other. The head was taken out from both surfaces of the laminated body of the plate, and when pressed with a finger, the plate was fixed so that the head was slightly retracted from the surface of the laminated body to obtain Intermediate 3. The substrate 1, the intermediate 3 and the substrate 2 described above were stacked in this order, and the whole was crimped and fixed with screws to obtain a semiconductor device inspection jig.

Example 2 A substrate 1 shown in FIG. 4 having a bump-shaped probe group 4, a connection terminal group 5, and a circuit conductor group 6 was produced by the following procedure.
Glass fiber cloth Polyimide resin copper-clad laminate MCL-I-
671 (manufactured by Hitachi Chemical Co., Ltd., trade name) was formed with inner layer conductor circuits on both sides to produce an inner layer circuit board. In order to improve the adhesion between the inner layer circuit conductor and the resin, the surface of the circuit conductor was treated with copper oxide and then reduced with an alkaline solution containing formaldehyde. Next, copper / invar / copper glad plate CIC (trade name of Texas Instruments Japan Co., Ltd.), which is a metal core, is perforated at necessary places, and after copper oxide treatment is applied to the surface, it contains formaldehyde. It was reduced with an alkaline solution. The above-mentioned inner layer circuit board, glass fiber cloth polyimide resin prepreg GIA-671N (manufactured by Hitachi Chemical Co., Ltd., trade name), CIC, prepreg, and a copper layer to be a circuit (5
μm) / 2% phosphorus-nickel intermediate layer (0.18
μm) / a copper foil with a three-layer structure consisting of a copper layer (15 μm) to be bumps on the surface so that the copper layer to be in contact with the prepreg is overlaid, and the pressure is 5.9 MPa (60 kg / c).
m ² ), the temperature was 175 ° C., and the molding and integration were performed under the conditions for 180 minutes, and drill holes were formed at predetermined positions to connect the front and back circuit layers. Next, an etching resist H-K450 (trade name, manufactured by Hitachi Chemical Co., Ltd.) is formed in a shape to be bumps, and a copper layer to be bumps up to an intermediate layer made of 2% phosphorus-nickel is an alkaline etching solution A.
The etching resist is selectively removed by etching with a process etching solution (manufactured by Soltex Co., Ltd.), the above etching resist is peeled off, and the exposed intermediate layer consisting of 2% phosphorus-nickel is treated with 200 g / l of nitric acid and hydrogen peroxide. Water 10ml / l,
After etching away with an etching solution containing 100 g / l of malic acid and 5 g / l of benzotriazole,
Electroless copper plating and electrolytic copper plating were performed to 30 μm to form required conductors on the inner wall of the hole and the surface. Then, an etching resist H-K450 (manufactured by Hitachi Chemical Co., Ltd., product name) is formed in a shape to be a circuit, the copper layer to be a circuit is selectively etched and removed, and the etching resist is peeled and removed, Outer shape processing was performed to obtain a substrate 1. next,
The substrate 2 and the intermediate body 3 of Example 1 are replaced by the substrate 1, the intermediate body 3,
Substrates 2 were superposed in this order, and the whole was crimped and fixed with screws to obtain a semiconductor device inspection jig.

[0017]

As described above, according to the present invention,
The probe mounting portion can be separated and downsized, and the probe mounting portion can be made of a material having a small amount of thermal deformation, so that a semiconductor device inspection jig having excellent mechanical accuracy can be provided.

[Brief description of drawings]

FIG. 1 is a conventional semiconductor device inspection jig.

FIG. 2 shows an embodiment of the present invention.

FIG. 3 shows an embodiment of the substrate 1 of the present invention.

FIG. 4 shows another embodiment of the substrate 1 of the present invention.

FIG. 5 shows an embodiment of the substrate 2 of the present invention.

FIG. 6 shows an example of the intermediate 3 of the present invention.

[Explanation of Codes] 0. Jig plate 1. Substrate 1 2. Substrate 2 3. Intermediate 3 01. Probe 11. Probe 21. Connection terminal 31. Connection terminal 02. Conductor circuit 12. Conductor circuit 22. Conductor circuit 32. Conductor circuit 03. Connection terminal 13. Connection terminal 23. Connection terminal 33. Connection terminal 04. Support 14. Support 24. Support 34. Support 4. Bump probe 5. Connection terminal 6. Circuit conductor 7. Support 8. Metal core 9. Circuit conductor 10. Inner layer circuit 15. Springiness 16. Bushing 17. Plated conductor 18. Laminated pin

Claims (4)

[Claims] 1. A jig for inspecting a semiconductor device, comprising a substrate 1, a substrate 2 and an intermediate body 3, wherein the substrate 1 is a probe group 11 for controlling electrical contact with a sample.
And a connection terminal group 13 that controls electrical connection with the intermediate body 2,
The circuit board group 12 has a circuit conductor group 12 that controls electrical connection between the plug group 11 and the connection terminal group 13, and is configured by a support body 14 that supports and fixes these. The substrate 2 is a connection terminal group of the intermediate body 3. 33 includes a connection terminal group 21 that controls electrical connection with the inspection device 33, a connection terminal group 23 that controls electrical connection with the inspection device, and a circuit conductor group 22 that controls electrical connection between the connection terminal groups 21 and 23. The intermediate body 3 has a connection terminal group 31 that electrically connects with the connection terminal group 13 and a connection body that electrically connects with the connection terminal group 21. A semiconductor device inspection including a terminal group 33 and a circuit conductor group 32 that controls the electrical connection between the connection terminal groups 31 and 33, and a support 34 that supports and fixes these terminals. Jig. 2. The support 14 of the substrate 1 is selected from at least alumina (Al ₂ O ₃ ), silicon carbide (SiC), aluminum nitride (AlN) and beryllia (BeO). The semiconductor device inspection jig according to claim 1. 3. The support 14 of the substrate 1 is an insulating plate having therein a metal layer selected from at least Invar (Fe—Ni 36% alloy) and molybdenum. Jig for semiconductor device inspection. 4. The support 14 of the substrate 1 is made of at least quartz (S
iO _2), the semiconductor device according to claim 1 or 3, characterized in that an insulating plate having a glass, a selected fiber cloth or nonwoven or nonwoven aromatic polyamide therein containing quartz 60% Inspection jig.