JPH08201765A - Liquid crystal driving circuit - Google Patents

Abstract

PURPOSE: To warrant the life and the display quality of a liquid crystal panel without consuming a useless current by supplying optimum voltage and current from a bias voltage generation circuit according to the bias system and the load of the connected liquid crystal panel. CONSTITUTION: Plural bias voltage generation circuits 27, 29 with different current supply amounts respectively constituted of plural resistance division circuits are provided, and the display data, the switch data and the selection data are inputted to a shift register 23 as a series of the serial data, and the contents are latched by a latch circuit 24, and bias voltage values to segment and common drivers 7, 11 are switched according to the latched switch data, and the resistance division states in the bias voltage generation circuits 27, 29 are revised according to a decoded output decoding the switch data and the selection data, and the current supply amounts to the segment and common drivers 7, 11 are selected.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal drive circuit having a bias voltage supply circuit for driving liquid crystal,
In particular, it relates to the same circuit in which the bias system can be changed.

[0002]

2. Description of the Related Art A liquid crystal drive system has a 1/2 bias,
There are a plurality of bias methods such as ⅓ bias, and a circuit configuration capable of selectively using the plurality of bias methods has been conventionally proposed. FIG. 6 shows a conventional liquid crystal drive circuit having a built-in bias voltage generation circuit.
An example in which two types of drive methods, that is, the / 3 duty / 1/3 bias method and the 1/3 duty / 1/2 bias method can be switched is shown.

In FIG. 6, 1 is a clock signal C sent from a system controller such as a microcomputer (not shown).
Clock input terminal for inputting L, 2 is display data D transmitted as serial data from the system controller
A data input terminal for inputting I and the switching data DR for switching the bias method, 3 is a shift register for taking in the display data and the switching data input to the data input terminal 2 based on the clock signal CL input to the clock input terminal 1,
A latch circuit 4 latches the contents of the shift register 3 by a latch pulse L from the latch signal generation circuit 6, and includes a switching data holding latch 5 that latches the switching data DR.

Reference numeral 7 is composed of a segment driver output waveform control circuit 8 and a segment driver output waveform generation circuit 9, and supplies output waveforms from the output terminals 10a, 10b, ..., 10n to the segments of the liquid crystal panel. The segment driver 11 is composed of a common driver output waveform control circuit 12 and a common driver output waveform generation circuit 13, and is a common driver for supplying output waveforms from the output terminals 14a, 14b, 14c to the common of the liquid crystal panel. Further, reference numeral 19 is composed of a resistance division circuit composed of three resistors having the same resistance value R1, and the bias voltages V1 (= VDD), V2 and V3 of three levels and the ground voltage VSS are supplied to the segment driver 7 and the common driver 11. It is a bias voltage generating circuit to be supplied.

Further, 101, 102, 103, 104
Is a bias voltage supply line for supplying the bias voltages V1, V2, V3, and VSS output from the bias voltage generation circuit 19 to the common and segment drivers, respectively.
Reference numerals a, 16b and 18 are transmission gates connected between the bias voltage supply lines, 17a and 17b are transmission gates inserted into the bias voltage supply lines 102 and 103, and these transmission gates are switched from the latch 5. A bias type switching circuit is configured by being on / off controlled by the data DR or its inverted signal BDR.

Therefore, when the display data and the switching data and the clock signal are sent from the system controller, the display data and the switching data are fetched in the shift register 3 in synchronization with the clock, and at the time when the fetching is completed, the latch pulse L Accordingly, the display data and the switching data are latched in the latch circuit 4. The latched display data is
Each 3 bits is applied to the segment driver output waveform control circuit 8 of the segment driver 7, and here, four segment driver output waveform control signals corresponding to the display data are generated in synchronization with the timing signal generated from the timing generation circuit 15. It

In the common driver 11, each common driver output waveform control circuit 12 generates four common driver output waveform control signals in synchronization with the timing signal generated from the timing generation circuit 15. By the way, the transmission gates 16a, 16b, 17a, 17b, 1 are connected to the bias voltage supply line.
Since 8 is connected, different bias voltages are supplied to the common and segment drivers by turning them on and off.

That is, in the case of the 1/3 duty / 1/3 bias method, by setting the switching data DR to "0",
Since the transmission gates 16a, 16b, 18 are turned off and 17a, 17b are turned on, the bias voltage supply lines 101, 105, 10 to the segment driver 7 are provided.
The voltage levels of 6 and 104 are VDD and 2 / 3VD, respectively.
It becomes D, 1/3 VDD, VSS. These bias voltage supply lines 101, 105, 106, 104 are connected to the segment output terminals 10a, 10b, ..., 10n via four transmission gates 9, and each segment driver output waveform control circuit. The four segment driver output waveform control signals from 8 control the opening and closing of these four transmission gates 9 to form a segment driver output waveform. Then, the segment driver output waveforms are output terminals 10a, 10b, ...
Output from 10n and applied to the liquid crystal panel.

The voltage levels of the bias voltage supply lines 101, 102, 103 and 104 to the common driver 11 are VDD, 2/3 VDD, 1/3 VDD and VSS, respectively.
These lines are connected to the respective common output terminals 14a, 14b, 14c via the four transmission gates 13 as in the segment driver 7, and the four commons from the respective common driver output waveform control circuits 12 are connected. This is controlled by the driver output waveform control signal.
By controlling the opening and closing of the three transmission gates 13,
The common driver output waveform is formed. This common driver output waveform is output to the output terminals 14a, 14b, 14
It is output from c and applied to the liquid crystal panel.

Therefore, in this case, as shown in FIGS. 8A to 8D, the common driver output waveforms COM1, COM2, COM in which the bias voltage changes to four levels every T / 6 hours.
3 and the segment driver output waveform Sn is obtained. On the other hand, in the case of the 1/3 duty 1/2 bias system,
By setting the switching data DR to "1", the transmission gates 16a, 16b, 18 are turned on, and 17a, 1
Since 7b is turned off, the voltage level of the bias voltage supply lines 101 and 105 to the segment driver 7 is VDD,
The voltage level of 104 and 106 becomes VSS. Since the same timing signal is output from the timing generation circuit 15 regardless of the value of DR, each segment driver output waveform control circuit 8 outputs four transmission gates 9
The four segment driver output waveform control signals output to the same are also the same signals. Therefore, as shown in FIG. 9D, the segment driver that takes either VDD or VSS voltage level every T / 6 hours. The output waveform Sn is formed.

The voltage level of the bias voltage supply line 101 to the common driver 11 is VDD, 102 and 1.
The voltage level of 03 is 1/2 VDD, the voltage level of 104 is VS
Since the same signal is output as the four common driver output waveform control signals from each common driver output waveform control circuit 12 irrespective of the value of DR, the signal S is output through the four transmission gates 13 as shown in FIG. Common driver output waveforms COM1, COM2, COM3 in which the bias voltage changes to three levels every T / 6 hours as shown in C are formed.

In FIGS. 8 and 9, the segment driver output waveform is a common driver output waveform COM.
Only the lighting waveform corresponding to 1 is shown. By the way, when the load of the liquid crystal panel connected to the segment output terminals 10a, 10b, ..., 10n and the common output terminals 14a, 14b, 14c is large, the amount of current supplied from these output terminals to the liquid crystal panel increases. . In such a case,
When the resistance value R1 of the bias voltage generating circuit 19 is large, the common and segment output waveforms are distorted, which leads to early deterioration of the liquid crystal panel and deterioration of display quality.

Therefore, conventionally, the resistance value R1 of the bias generating circuit 19 is set to a small value so that the life and the display quality can be guaranteed for all the liquid crystal panels having a small load to a liquid crystal panel having a large load. Also, IC
In order to suppress the current consumption of the resistor, as shown in FIG. 7, in the built-in bias voltage generation circuit 20, the resistance value R2 of the resistance division circuit is set to a large value and the resistance value of the resistance value R3 is small outside the IC. An external bias voltage generating circuit 21 composed of a dividing circuit can be connected in parallel with the bias voltage generating circuit 20, and in the case of a liquid crystal panel having a large load, the external bias voltage generating circuit 21 is used. There were things.

[0014]

In the circuit shown in FIG. 6,
Since the resistance value R1 of the bias voltage generation circuit 19 is set to be small, the current consumption becomes large. Therefore, when driving a liquid crystal panel with a small load, there was a problem that wasted current was consumed. . In addition, the circuit of FIG. 7 requires an external resistor depending on the liquid crystal panel used, which causes an increase in external components and also causes an external resistor to be used even when the IC is not operating. Since this consumes a current, it is not suitable for lowering the current.

[0015]

SUMMARY OF THE INVENTION The present invention provides a timing generation circuit for generating a timing signal for display control, a segment driver for forming a segment driver output waveform based on display data and the timing signal, and the timing signal. A common driver that forms a common driver output waveform according to the above, and a plurality of bias voltage generation circuits that supply bias voltages for driving the liquid crystal to the segment driver and the common driver, and different current supply amounts, respectively. A selection circuit for selecting one or more of the plurality of bias voltage generation circuits according to selection data for selection, and supply from the bias voltage generation circuit to the segment driver and the common driver according to switching data for switching a bias method. Switch circuit that switches the bias voltage value Only by a liquid crystal drive circuit it is intended to solve the above problems.

Further, according to the present invention, a timing generation circuit for generating a timing signal for display control, a segment driver for forming a segment driver output waveform based on display data and the timing signal, and a common driver according to the timing signal. A common driver that forms an output waveform; a plurality of bias voltage generation circuits that supply a bias voltage for driving a liquid crystal to the segment driver and the common driver through a bias voltage supply line, and each current supply amount is different; A switching circuit connected to the bias voltage supply line for switching the bias voltage value supplied from the bias voltage generation circuit to the segment driver and the common driver according to the switching data for switching the bias method, and the switching data and the current supply amount selection Deco selected data of A liquid crystal drive circuit is configured by providing a decoding circuit for switching and a selection circuit for selecting the current supply amount of the plurality of bias voltage generating circuits according to the decoding output of the decoding circuit, thereby solving the above problems. Is.

Further, in the present invention, each of the plurality of bias voltage generation circuits is composed of a plurality of resistance division circuits, and a predetermined resistance division point is connected to the bias voltage supply line. By including a plurality of gate circuits inserted in a plurality of resistance division circuits for switching the connection state of the resistance between the power supply voltage and the bias voltage supply line, and controlling the opening / closing of the gate circuits by the output of the decoding circuit. It is characterized in that the current supply amount is selected.

Further, in the present invention, the plurality of gate circuits are inserted between the predetermined resistance division point connected to the bias voltage supply line and a power supply voltage, and opened / closed by an output of the decoding circuit. The resistance value between the bias voltage supply line and the power supply voltage is changed by. Furthermore, the present invention provides a shift register for inputting the display data, switching data and selection data,
And a latch circuit for latching the contents of the shift register.

Further, in the present invention, the display data is inputted as serial data, and the switching data and the selection data are data inputted as a series of serial data together with the display data.

[0020]

According to the present invention, by simply inputting the switching data and the selection data, it is possible to switch to a desired bias system, and to reduce the current supply amount to a liquid crystal panel with a small load, a liquid crystal with a large load can be obtained. It becomes possible to increase the amount of current supplied to the panel.

Further, since the switching data and the selection data are the display data and a series of serial data, the data input terminal can be used also as the display data, and the circuit configuration of the shift register, the latch circuit, etc., increases the number of bits. You can deal with it.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, in which all illustrated components are built in an LSI. Further, the same components as those of the conventional example shown in FIGS. Here, a system controller (not shown) sends 1-bit switching data DR for switching the bias method and 1-bit selection data CU for selecting the current supply amount as a series of serial data immediately after the display data DI. For this reason, the shift register 23 and the latch circuit 24 are the same as those of the conventional shift register 3
The number of bits is one bit larger than that of the latch circuit 4. Then, in the latch circuit 24, the latch 25 at the final bit position is a latch for selected data. Further, in this embodiment, two AND gates 26 are provided.
1, 262, and decodes the inversion signal BDR of the switching data DR from the latch 5, the selection data CU from the latch 25 and its inversion signal BCU, and outputs the signals C, D, E,
A decoder 26 that outputs F is provided.

As for the bias voltage generating circuit, the resistance value R4 of the resistance dividing circuit is set to a small value to increase the current supply amount, and the resistance value R5 of the resistance dividing circuit is set. Is set to a large value to reduce the amount of current supply, and a second bias voltage generating circuit 29 is provided. Each bias voltage generation circuit 27, 29 is composed of first and second two-row resistance division circuits 271, 291 and 272, 292, respectively, and each resistance division circuit 271, 272, 291, 292.
, The first transmission gates 28a, 28c, 30a, 30c are connected between the power supply potential VDD and the first resistor.
However, the second transmission gates 28b, 28d, 30b and 30d are inserted between the ground potential VSS and the third resistor, respectively. The output C of the decoder 26,
D, E and F are respectively the transmission gate 28b
And 28c, 28a and 28d, 30a and 30d, 3
It is input to 0b and 30c as an on / off control signal.

Here, in the decoder 26, AND
The outputs of the gates 261 and 262 become signals C and F, and the selection data CU and its inverted signal BCU become signals D and E. In addition, the first resistance and the second resistance of the resistance division circuits 271, 291
The division point A between the resistors is connected to the bias voltage supply line 102, and the division point B between the second resistor and the third resistor of the resistor division circuits 272 and 292 is the bias voltage supply line 103.
It is connected to the. Bias voltage supply lines 101, 1
04 is directly connected to the power supply voltages VDD and VSS of the resistance division circuit 272.

Next, the operation of this embodiment will be described in detail.
Serial data consisting of display data, switching data and selection data is input to the data terminal 2 and the clock signal CL
Is input to the clock terminal 1, the shift register 23
The display data, the switching data, and the selection data are fetched in the. Latch signal L after acquisition
Is applied, the display data of the shift register 23, the switching data and the selection data are latched by the latch circuit 24. Specifically, the switching data and the selection data are latched by the latches 5 and 25 in the latch circuit 24.

Now, if the switching data DR = “0” and the selection data CU = “0”, 17a and 17b of the transmission gates connected to the bias voltage supply line are selected.
Is turned on and 16a, 16b and 18 are turned off, so that each supply line becomes an independent state, that is, a state corresponding to the 1/3 bias system. In the bias voltage generating circuits 27 and 29, the outputs C, D, E and F of the decoder 26 are respectively "001".
1 ", all the transmission gates 30a to 30d of the bias voltage generating circuit 29 are turned on and all the transmission gates 28a of the bias voltage generating circuit 27 are turned on as shown in the first row of FIG. ~ 28d turns off. Therefore, the bias voltage supply lines 101, 105, 106 and 104 to the segment driver 7 are connected to the bias voltages VDD and 2 / 3VD from the bias voltage generation circuit 29.
D, 1/3 VDD, VSS will be supplied.

Here, in the bias voltage generating circuit 29,
Since the resistance value R5 is large, the amount of current supplied to the segment and common drivers 7 and 11 is small. Therefore, when connecting a liquid crystal panel with a small load, no unnecessary current is consumed and optimum driving is performed. Can be done. Next, if the switching data DR = "0" and the selection data CU = "1", the transmission gates 16a, 16b, 17
Similarly to the above, a, 17b and 18 are in a state corresponding to the 1/3 bias system. Also, the output C of the decoder 26,
Since D, E, and F are "1100", respectively,
As shown in the row, all the transmission gates 28a to 28d of the bias voltage generating circuit 27 are turned on, and all the transmission gates 30a to 30d of the bias voltage generating circuit 29 are turned off. Therefore, the bias voltage supply lines 101, 105,
Bias voltages VDD, 2/3 VDD, 1/3 VDD and VSS are supplied from the bias voltage generating circuit 27 to 106 and 104.

In the bias voltage generating circuit 27, the resistance value R
4 is small, so segment and common drivers 7,
The amount of current supplied to 11 becomes large. Therefore, when a liquid crystal panel with a large load is connected, optimum driving can be performed without distorting the output waveform. Switching data DR =
When "1" and selection data CU = "0", 17a and 17b of the transmission gates connected to the bias voltage supply line are turned off and 16a, 16b and 18 are turned on, so that the segment driver 7 supplies them. Lines 101 and 105 are connected and this line is fixed to voltage VDD, supply lines 104 and 106 are connected and this line is fixed to voltage VSS. In the common driver 11, the supply lines 102 and 103 are connected, and these lines are the supply lines 105 and 1 to the segment driver.
It is cut off as 06. That is, the state corresponds to the 1/2 bias system.

Since the outputs C, D, E and F of the decoder 26 are "0010", the transmission gates 30a and 30d of the bias voltage generating circuit 29 are shown in the third row of FIG. Only turns on and the current is from VDD,
Transmission gate 30a, point A, transmission gate 18, point B, transmission gate 3
Through 0d to VSS. Therefore, the supply line 10
A voltage ½ VDD divided into ½ by the first resistance of the resistance division circuit 291 and the third resistance of the resistance division circuit 292 is supplied to the circuits 2, 103. Here, in the bias voltage generation circuit 29, since the resistance value R5 is large,
The amount of current supplied to the drivers 7 and 11 for the segment and the common becomes small.

On the other hand, when the switching data DR = "1" and the selection data CU = "1", the outputs C, D, and
Since E and F are both "0100", as shown in the fourth row of FIG. 2, only the transmission gates 28a and 28d of the bias voltage generating circuit 27 are turned on and the current is V
It flows from DD to VSS through the transmission gate 28a, point A, the transmission gate 18, point B, and the transmission gate 28d. Therefore, the supply line 102, 103 is supplied with the voltage ½ VDD divided into ½ by the first resistance of the resistance division circuit 271 and the third resistance of the resistance division circuit 272. In the bias voltage generation circuit 27, since the resistance value R4 is small,
The amount of current supplied to the drivers 7 and 11 for the segment and the common becomes large.

As described above, the switching method and the selection data make it possible to select the optimum bias method and current supply amount according to the connected liquid crystal panel. In the embodiment shown in FIG. 1, the bias voltage generating circuit is composed of a plurality of resistance dividing circuits. However, if the bias voltage generating circuit is composed of only one resistance dividing circuit as in the conventional case. Requires the transmission gate to be inserted between the resistance dividing points A and B and the supply lines 102 and 103. In the case of the common driver, the transmission gate is provided through this one transmission gate, or in the segment driver. Is this transmission gate and 17a or 1
Via two transmission gates of 7b,
It is necessary to supply a bias voltage, and at low voltage, the on-impedance of these transmission gates becomes relatively large, which makes it impossible to supply an accurate bias voltage.

However, in the embodiment, since the bias voltage generation circuit is composed of a plurality of resistance division circuits,
The resistance division point A of one of the resistance division circuits 271, 291 is directly connected to the supply line 102, and the other resistance division circuit 27.
The resistance dividing points B of 2,292 can be directly connected to the supply line 103, and an accurate bias voltage can be supplied to the supply line even when the power supply voltage VDD becomes low.

Next, a second embodiment will be described with reference to FIG. Here, the selection data CU is CU1,
The shift register 31 and the latch circuit 32 are configured by 3 bits of CU2 and CU3, and the number of bits is increased accordingly. Further, the decoder 34 that decodes the selection data and the switching data DR is specifically shown in FIG.
And its inputs DR, CU1, CU
2, the relationship between CU3 and the outputs C, D, E, F is as shown in FIG. 10, and the on / off state of each transmission gate in this case is as shown in FIG.

First, when the switching data DR is "0", the transmission gate 16a connected to the supply line.
Similarly to the above-described embodiment, the states of 18 to 18 are independent states corresponding to the 1/3 bias, and in the case of "1", they are the connected states corresponding to the 1/2 bias. However, the ON / OFF states of the transmission gates in the bias voltage generating circuits 27 and 29 are different.

That is, the data DR, CU1, CU2, CU
When 3 is “0000”, the bias voltage generation circuit 29
Since all the transmission gates of 1 are turned on and all the transmission gates of the bias voltage generation circuit 27 are turned off, the current supply amount is small. Data DR,
When CU1, CU2, and CU3 are "0100", all the transmission gates of the bias voltage generation circuit 27 are turned on and all the transmission gates of the bias voltage generation circuit 29 are turned off, so that the current supply amount becomes large.

Then, the data DR, CU1, CU2, C
When U3 is “0010”, the bias voltage generation circuit 2
Since all the transmission gates 7 and 29 are turned on, currents are supplied from the two bias voltage generating circuits 27 and 29, and the current supply amount becomes maximum. Next, when the data DR, CU1, CU2, and CU3 are “1000”, only the transmission gates 30b and 30c of the bias voltage generation circuit 29 are turned on, so that the supply lines 102 and 103 are the first lines of the resistance division circuit 292. And the second
Are connected to the power supply voltage VDD via the two resistors (2R5) of the same, and are connected to the power supply voltage VSS via the second and third resistors (2R5) of the resistance division circuit 291. That is, in this case, the resistance value for resistance division becomes large, and therefore the current supply amount becomes the smallest.

When the data DR, CU1, CU2, CU3 is "1100", only the transmission gates 30a, 30d of the bias voltage generating circuit 29 are turned on, so that the supply lines 102, 103 are connected to the resistance dividing circuit 29.
1 is connected to the power supply voltage VDD via the first resistance (R5) and is connected to the power supply voltage VSS via the third resistance (R5) of the resistance division circuit 292, and therefore the resistance value for resistance division is as described above. It becomes smaller and the current supply amount becomes slightly larger.

When the data DR, CU1, CU2, and CU3 are "1010", all the transmission gates 30a to 30d of the bias voltage generating circuit 29 are turned on, so that the supply lines 102 and 103 are connected to the resistance dividing circuit 2.
Power supply voltage VDD via the first resistor (R5) 91 and the first and second two resistors (2R5) of the resistance division circuit 292.
Of the resistance divider circuit 291. It is connected to the power supply voltage VSS through the third two resistors (2R5) and the third resistor (R5) of the resistor divider circuit 292, and therefore the power supply voltages VDD and VSS and the supply lines 102 and 103 are connected.
The resistance value between the two becomes 2/3 · R5, and the current supply amount further increases.

Data DR, CU1, CU2, CU3
Is "1110", only the transmission gates 28b and 28c of the bias voltage generating circuit 27 are turned on.
72 first and second two series-connected resistors (2R
4) connected to the power supply voltage VDD, and the second and third two resistors (2
It is connected to the power supply voltage VSS via R4). Therefore, by setting the resistance value 2R4 smaller than the resistance value R5, the current supply amount in this case is further increased.

Further, the data DR, CU1, CU2, CU
When 3 is “1001”, the bias voltage generation circuit 27
Since only the transmission gates 28a and 28d are turned on, the supply lines 102 and 103 are connected to the power supply voltage VDD through the first resistance (R4) of the resistance division circuit 271 and the third resistance of the resistance division circuit 272. It is connected to the power supply voltage VSS via (R4), and therefore the resistance value for resistance division becomes smaller than the above and the current supply amount further increases.

When the data DR, CU1, CU2, and CU3 are "1101", all the transmission gates 28a to 28d of the bias voltage generating circuit 27 are turned on, and the power supply voltages VDD and VSS and the supply lines 102 and 103.
The resistance value between the two becomes 2/3 · R4, and the current supply amount further increases. Then, the data DR, CU1, CU2, CU
When 3 is “1011”, the bias voltage generation circuit 27
Since all the transmission gates 29 and 29 are turned on, currents are supplied from the two bias voltage generating circuits, and the current supply amount becomes the largest.

As described above, the current supply amount can be selected more finely by a plurality of selection data, and optimum driving can be performed according to the load of the liquid crystal panel without consuming unnecessary current. In addition to the embodiments described above, the number of bias voltage generating circuits and the number of bias voltage levels may be increased if necessary, and the number of bits of switching data and selection data may be increased accordingly. Further, as a driving method, it is naturally applicable to other methods.

[0043]

According to the present invention, the optimum voltage and current amount can be supplied from the bias voltage generating circuit according to the bias system and load of the liquid crystal panel to be connected, and therefore, a plurality of different bias systems can be supported. In addition, the life and display quality of the liquid crystal panel can be guaranteed without wasting current.

Further, by making the switching data and the selection data the display data and a series of serial data, it is possible to suppress the increase of terminals and to obtain the above-mentioned effects by only a slight circuit change.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a first exemplary embodiment of the present invention.

FIG. 2 is a diagram showing switching data and selection data and an on / off state of each transmission gate in the first embodiment.

FIG. 3 is a block diagram showing a configuration of a second embodiment.

FIG. 4 is a circuit diagram showing a specific configuration of a decoder in the second embodiment.

FIG. 5 is a diagram showing switching data and selection data and an on / off state of each transmission gate in the second embodiment.

FIG. 6 is a block diagram showing a configuration of a first conventional example.

FIG. 7 is a block diagram showing a configuration of a second conventional example.

FIG. 8 is a waveform diagram showing common and segment driver output waveforms in the case of 1/3 duty and 1/3 bias.

FIG. 9 is a waveform diagram showing common and segment driver output waveforms in the case of 1/3 duty and 1/2 bias.

FIG. 10 is a diagram showing a relationship between an input and an output of a decoder in the second embodiment.

[Explanation of symbols]

1 clock input terminal 2 data input terminal 3, 23, 31 shift register 4, 24, 32 latch circuit 7 segment driver 8 segment driver output waveform control circuit 9 segment driver output waveform generation circuit 10a, 10b, ..., 10n segment output Terminal 11 Common driver 12 Common driver output waveform control circuit 13 Common driver output waveform generation circuit 14a, 14b, 14c Common output terminal 15 Timing generation circuit 19, 20, 21, 27, 29 Bias voltage generation circuit 26, 34 Decoder 16a, 16b , 17a, 17b, 18 Transmission gate 28a, 28b, 28c, 28d Transmission gate 30a, 30b, 30c, 30d Transmission gate 271, 272, 291, 292 Resistance division circuit

Claims (6)

[Claims] 1. A timing generation circuit that generates a timing signal for display control, a segment driver that forms a segment driver output waveform based on display data and the timing signal, and a common driver output waveform that forms in accordance with the timing signal. A common driver, a plurality of bias voltage generating circuits for supplying a bias voltage for driving the liquid crystal to the segment driver and the common driver, each of which supplies a different amount of current, and selection data for selecting a current supply amount. A selection circuit for selecting one or more of the plurality of bias voltage generation circuits, and a switching circuit for switching a bias voltage value supplied from the bias voltage generation circuit to the segment driver and the common driver according to switching data for switching a bias method. And a liquid crystal characterized by Drive circuit. 2. A timing generation circuit that generates a timing signal for display control, a segment driver that forms a segment driver output waveform based on display data and the timing signal, and a common driver output waveform that forms in accordance with the timing signal. Common driver, a plurality of bias voltage generating circuits for supplying a bias voltage for driving the liquid crystal to the segment driver and the common driver through a bias voltage supply line, and different current supply amounts, and the bias voltage supply line. A switching circuit connected to the switching circuit for switching the bias voltage value supplied from the bias voltage generating circuit to the segment driver and the common driver according to the switching data for switching the bias system; and the switching data and the selection data for selecting the current supply amount. Decoding to decode And a selection circuit for selecting the current supply amount of the plurality of bias voltage generation circuits according to the decoded output of the decoding circuit. 3. The liquid crystal drive circuit according to claim 2,
Each of the plurality of bias voltage generation circuits is composed of a plurality of resistance division circuits, and a predetermined resistance division point is connected to the bias voltage supply line, and the selection circuit is inserted in the plurality of resistance division circuits. A plurality of gate circuits for switching a connection state of a resistance between a power supply voltage and the bias voltage supply line are included, and a current supply amount is selected by controlling opening / closing of the gate circuits by an output of the decoding circuit. LCD drive circuit. 4. The liquid crystal drive circuit according to claim 3,
The plurality of gate circuits are inserted between the predetermined resistance division point connected to the bias voltage supply line and the power supply voltage, and are opened and closed by the output of the decoding circuit to open the bias voltage supply line and the power supply voltage. A liquid crystal drive circuit characterized by changing a resistance value between the two. 5. The liquid crystal drive circuit according to claim 1,
A liquid crystal drive circuit further comprising a shift register for inputting the display data, the switching data, and the selection data, and a latch circuit for latching the contents of the shift register. 6. The liquid crystal drive circuit according to claim 3,
The liquid crystal driving circuit, wherein the display data is input as serial data, and the switching data and the selection data are data input as a series of serial data together with the display data.