JPH08204125A - Semiconductor circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] To realize a semiconductor circuit capable of improving the resistance to electrostatic discharge while maintaining the resistance to electrostatic discharge represented by the human body charging model and machine model. [Structure] A capacitor 9 is connected between a source electrode (power supply line 2) of a PMOS transistor 7 forming an input stage and a gate electrode (on the input terminal side), and a source electrode of an NMOS transistor 7 also forming an input stage. The capacitor 10 is connected between the (ground line 3) and the gate electrode (input terminal side). This makes it possible to maintain the effectiveness of the input protection circuit against electrostatic breakdown in the human body charging model or machine model, while maintaining the effectiveness of the input protection circuit and adding a capacitive element to the package charging model or device charging model by simple means. The breakdown voltage against electrostatic breakdown in the model can be improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor circuit provided with a protection circuit for preventing gate destruction of a transistor forming an input / output buffer.

[0002]

2. Description of the Related Art For faults caused by electrostatic breakdown due to electrostatic discharge at input / output terminals of semiconductor circuits, which are based on human body charging model or machine model, development and handling of protection circuits suitable for these With the progress of countermeasures against static electricity and the like, these effects have been reduced.

FIG. 13 is a circuit diagram showing a semiconductor circuit provided with an input protection circuit corresponding to a human body charging model or a machine model. In FIG. 13, 1 is an input terminal, 2 is a power supply line for the power supply voltage V _CC of the semiconductor circuit, 3 is a grounding ground line for the semiconductor circuit, 4 is a protective resistance element, and 5 is a diode-connected power supply voltage V _CC side. Is a p-channel MOS (hereinafter referred to as PMOS) transistor for protection, 6 is a protection n-channel MOS (hereinafter referred to as NMOS) transistor on the ground side, 7 is an input PMOS transistor, and 8 is an input NMOS transistor. .

In this circuit, an inverter circuit as an input buffer of the first stage is constituted by the PMOS transistor 7 and the NMOS transistor 8, and a high voltage application (hereinafter referred to as surge) for a short period due to static electricity or the like (hereinafter referred to as surge) causes the PMOS of the first input stage to be input. In order to prevent the gates of the transistor 7 and the NMOS transistor 8 from being destroyed, the charge due to the surge is protected by the protection PMOS transistor 5 or the NMOS.
The transistor 6 is configured to flow to the power supply line 2 or the ground line 3.

[0005]

By the way, MOSFE
As the package capacitance increases due to the thinning of the gate oxide film of T and the miniaturization of the package and the automation of the assembly process progresses, failure due to electrostatic breakdown represented by the package charging model (or device charging model) becomes a problem. Is coming.

However, the protective diodes (transistors 5 and 6) and the resistance element 4 provided for the above-mentioned human body charging model and machine model do not always function effectively because their mechanisms are different.
The gate oxide films of the PMOS transistor 7 and the NMOS transistor 8 in the first stage of input may be destroyed, resulting in a failure. Specifically, in the circuit of FIG. 13, the package surface S is charged to a high voltage by frictional static electricity, and discharge occurs when the terminal comes into contact with (grounded) metal. At this time,
A voltage applied to the gate oxide film of the input MOS transistors 7 and 8 is applied, but before the protection transistors 5 and 6 are clamped to a voltage lower than the withstand voltage of the gate oxide film, the voltage due to the surge is the withstand voltage of the gate oxide film. When applied in the above manner, the gate oxide film is destroyed, leading to a failure. FIG.
In FIG. 3, C _PV is a power line package capacitance, and C _PS is a ground line package capacitance.

Here, for simplification, in the circuit of FIG. 13, only the power supply line package capacitance and the input PMOS transistor 7 are considered as the package capacitance and the input MOS transistor, and the package charging is performed assuming that there is no protection circuit. Let us further consider the electrostatic breakdown in. At this time, with respect to the charging voltage V _P , the input P after discharging
Voltage V _ox applied to the gate oxide film of the MOS transistor 7
The maximum value V _{OXmax of} is expressed by the following equation. V _OXmax = {C _PKG / (C _PKG + C _OX )} V _P (1) However, in practice, due to the influence of the protective resistance element 4 or various parasitic elements not shown in FIG. Then, the state of formula (1) is reached. When the voltage V _OX becomes higher than the breakdown voltage of the gate oxide film, the transistor 7 causes gate breakdown. However, before the voltage V _OX reaches this withstand voltage,
For example, the protection transistor 5 operates and its source −
If the drain-to-drain voltage, that is, V _OX can be clamped at a voltage lower than the breakdown voltage of the gate oxide film, the transistor 7 will not cause gate breakdown.

The present invention has been made in view of the above circumstances, and an object thereof is to improve the resistance to electrostatic breakdown while maintaining the resistance to electrostatic breakdown represented by a human body charging model or a machine model. An object is to provide a semiconductor circuit that can be manufactured.

[0009]

In order to achieve the above object, the present invention provides a semiconductor circuit for inputting an external signal to a gate electrode of a metal insulating film semiconductor transistor,
A capacitive element is connected between the gate input line and the power supply line of the metal insulating film semiconductor transistor.

In the semiconductor circuit of the present invention, the first diode is connected between the input line of the external signal and the power supply line, and the gate input line of the metal insulating film semiconductor transistor and the power supply line are connected to each other. A second diode is connected in parallel with the capacitive element.

The present invention has a metal insulating film semiconductor transistor connected between a power supply line and an output terminal, and outputs a signal of a level corresponding to an input voltage to a gate electrode of the metal insulating film semiconductor transistor from a drain electrode. In a semiconductor circuit for outputting to a terminal, a capacitive element is connected between a drain electrode and a gate electrode of the metal insulating film semiconductor transistor.

[0012]

According to the semiconductor circuit of the present invention, the voltage applied to the gate electrode of the metal insulating film semiconductor transistor by the capacitive element is suppressed to a voltage lower than the gate breakdown voltage. Similarly, due to the second diode, the voltage applied to the gate electrode of the metal insulating film semiconductor transistor does not drop much below the voltage of the power supply line, and as a result, the voltage applied to the gate electrode of the metal insulating film semiconductor transistor is higher than the gate breakdown voltage. There is no potential difference.

Further, according to the semiconductor circuit of the present invention, the voltage applied to the gate electrode of the metal insulating film semiconductor transistor by the capacitive element can be suppressed to a voltage lower than the gate breakdown voltage even in the output stage.

[0014]

[Embodiment 1] FIG. 1 is a circuit diagram showing a first embodiment of a semiconductor circuit according to the present invention, and the same components as those in FIG. 13 showing a conventional example are denoted by the same reference numerals. That is, 1 is an input terminal, 2 is a power supply line for a power supply voltage V _CC of a semiconductor circuit, 3 is a grounding ground line for a semiconductor circuit, 4 is a protective resistance element,
Reference numeral 5 is a diode-connected PM for protection on the side of the power supply voltage V _CC
An OS transistor, 6 is a ground-side protection NMOS transistor, 7 is an input PMOS transistor, 8 is an input NMOS transistor, and 9 and 10 are protection capacitors.

In this circuit, a capacitor 9 is connected between the 7 source electrode of the PMOS transistor forming the input stage, that is, the power supply line 2 and the gate electrode, that is, the input terminal side (gate input line), and the input stage is also connected. Constituting NMO
A capacitor 10 is provided between the source electrode of the S transistor 7, that is, the ground line 3 and the gate electrode, that is, the input terminal side.
Is connected.

With this structure, the input P
C _OX in the equation (1) is increased by the capacitance C ₇ or C ₈ of the capacitor 7 or 8 without changing the characteristics such as the logical threshold value of the inverter composed of the MOS transistor 7 and the NMOS transistor 8. Is equivalent to Therefore, the maximum value V _OX of the voltage V _OX applied to the gate oxide film of the input PMOS transistor 7 or NMOS transistor 8 after discharging with respect to the charging voltage V _P
OXmax is reduced. As a result, it takes a long time for the voltage V _OX to reach the breakdown voltage of the gate oxide film. This time is longer than the time until an element that clamps an excessive voltage, such as the PMOS transistor 5 or the NMOS transistor 6 as a protection diode, operates.

As a result, when the package surface S is charged to a high voltage by frictional static electricity and a discharge occurs when the terminals come into contact with the metal, a voltage applied to the gate oxide films of the input MOS transistors 7 and 8 is applied. However, before the voltage V _OX reaches the withstand voltage of the gate oxide film, the protection PMOS transistor 5 or the NMOS transistor 6 operates and its source-drain voltage, that is, V _OX is lower than the withstand voltage of the gate oxide film. Clamp to. Therefore, the PMOS transistor 7 and the NMOS transistor 8 in the input stage do not cause the gate breakdown.

FIG. 2 shows the circuit characteristic of FIG. 1 described above, and Δt in the figure shows the time delay from when the clamp voltage is reached until when the clamp voltage is actually clamped. Maximum voltage V
If _{OXma x} is low, the gate voltage is clamped at a voltage less than the breakdown voltage.

As described above, according to the first embodiment, the capacitor 9 is provided between the source electrode (power supply line 2) of the PMOS transistor 7 forming the input stage and the gate electrode (input terminal side). N, which connects the
Since the capacitor 10 is connected between the source electrode (ground line 3) and the gate electrode (input terminal side) of the MOS transistor 8, the effectiveness of the input protection circuit against electrostatic breakdown in the human body charging model or machine model is maintained. While
There is an advantage that the withstand voltage against electrostatic breakdown in the package charging model or the device charging model can be improved by a simple means that does not require addition or modification of the process of adding a capacitive element.

The capacitors 9 and 11 are MO
By using a MOS capacitor element having the same gate oxide film as the S transistors 5 to 8 and formed at the same time,
Although a large capacitance can be obtained in a small area, it is not necessarily limited to this, and other methods such as junction capacitance or interlayer capacitance may be used as long as a necessary and sufficient capacitance can be secured.

Further, in the present example, the example in which the capacitors on the power supply side and the ground side are paired is shown. However, even if only one of the capacitors is connected to the surge corresponding to the positive side or the negative side, It goes without saying that it is effective.

[0022]

Second Embodiment FIG. 3 is a circuit diagram showing a second embodiment of the semiconductor circuit according to the present invention. The second embodiment differs from the above-mentioned first embodiment in that the resistance element 4 for protection is connected between the input terminal 1 and the connection point of the anode of the protection diode 5a and the cathode of the diode 6a. To
This connection point and the input stage PMOS transistors 7 and N
It is connected between the gates of the MOS transistors 8 and the connection point. Also in this circuit, the surge is absorbed by the diode 4 or the diode 5, that is, the electric charge is made to flow to the power supply line 2 or the ground line 3, and further, a low-pass filter including the protective resistance element 4 and the capacitor 9 or 10 is used, and the inverter of the input stage By blunting the voltage waveforms applied to the gates of the PMOS transistor 7 and the NMOS transistor 8 constituting the above, the gate oxide films of both transistors 7 and 8 are protected from destruction. This operation will be described below with reference to FIGS. 4 and 5.

FIG. 4 shows a test circuit of the input protection circuit corresponding to FIG. 3, and FIG. 5 shows voltage waveforms of essential parts in the circuit of FIG. In this test circuit, both the power supply line 2 and the ground line 3 are grounded during the test, and in FIG.
It is ND. In FIG. 4, 11 is a changeover switch, 12 is a test voltage of 1000 V, 13 is a capacitor having a capacity of 30 pF for storing a charge for test, and the other configurations are the same as those in FIG. The parts are represented by the same symbols. A is the terminal voltage of the capacitor 13, B is the voltage of the input terminal 1, and C is the PMOS transistor 7 and NM of the input stage.
The input voltage to the OS transistor 8 is shown in FIG.
The waveforms of B and C are shown.

At time t1, the changeover switch 11 is changed over to the input terminal 1 side of the IC. As a result, the electric charge stored in the capacitor 13 flows to the ground GND via the input terminal 1 and the protection diode 6a, and the waveform of the terminal voltage A of the capacitor 12 becomes the waveform A as shown in FIG. At this time, the waveform of the voltage B at the input terminal 1 also becomes the waveform B as shown in FIG. A waveform passed through a so-called low-pass filter (LPF) blunted by the resistance element 4 and the capacitors 9 and 10 so that the waveform of the voltage B at the input terminal 1 is not transmitted to the gates of the MOS transistors 7 and 8 at the input stage. Becomes a waveform C as shown in FIG. As can be seen from FIG. 5, the input stage PMOS transistor 7 and NM
The input voltage waveform C to the OS transistor 8 is the input terminal 1
The voltage peak is suppressed lower than the voltage B of the
The voltage stress applied to the gates of the OS transistor 7 and the NMOS transistor 8 is suppressed low.

In such a case, in order to improve the resistance to electrostatic breakdown, the characteristics of the protection diodes 5a and 6a are improved, the values of the resistance element 4 and the capacitors 9 and 10 are increased,
It is effective to increase the time constant of the LPF.

According to the second embodiment, the withstand voltage against electrostatic breakdown can be improved as in the case of the first embodiment.

[0027]

Third Embodiment FIG. 6 is a circuit diagram showing a third embodiment of the semiconductor circuit according to the present invention. The third embodiment is different from the second embodiment described above in that the input protection is performed between the gate electrode and the source electrode of the PMOS transistor 7 in the input stage so as to be in the forward direction from the gate electrode to the source electrode. The diode 20 is connected, and the input protection diode 21 is connected between the gate electrode and the source electrode of the NMOS transistor 8 so as to be in the forward direction from the source electrode to the gate electrode, and is resistant to electrostatic breakdown during package charging. Has been improved.

Hereinafter, it will be described with reference to FIGS. 7 to 10 that this configuration improves the resistance to electrostatic breakdown during package charging as compared with the configuration of FIG. FIG. 7 is a test circuit when the circuit of FIG. 3 is evaluated by the package charging model, and FIG. 8 shows voltage waveforms of the main parts in the circuit of FIG. In this test circuit, at the time of the test, the I-stage MOS transistors 7 and 8 are connected in parallel between the power line 2 and the ground line 3 in parallel.
It is equivalent to the circuit to which the internal impedance 22 of C is connected. In addition, in FIG. 7, reference numeral 23 denotes a changeover switch, the other configurations are the same as those in FIG. 6, and the same components are denoted by the same reference numerals. Further, B is the voltage of the input terminal 1, and C is the PMOS transistor 7 in the input stage.
And the input voltage to the NMOS transistor 8, D is the voltage of the ground line 3, E is the voltage of the power supply line 2, and B and B in FIG.
The waveforms of C, D and E are shown.

In this test circuit, when the changeover switch 23 is switched to the ground side at time t2, as shown in FIG. 7, the voltage B at the input terminal 1 and the input voltage C to the PMOS transistor 7 and the NMOS transistor 8 at the input stage are obtained. Is decreasing. The voltage D of the ground line 3 drops through the diode 6a, and the voltage E of the power line 2 also drops through the internal impedance. At this time, the voltage V _OX may be applied to the gate oxide film of the MOS transistor 7 or 8 in the input stage due to the difference in time constant, and it is considered that electrostatic breakdown occurs.

On the other hand, FIG. 9 shows a test circuit when the circuit of FIG. 6 is evaluated by the package charging model.
Reference numeral 0 indicates a voltage waveform of a main part in the circuit of FIG.
This test circuit has the same configuration as the circuit of FIG. 7 except that the input protection diodes 20 and 21 are connected, and the same components are denoted by the same reference numerals.
Further, B is the voltage of the input terminal 1, C is the input voltage to the PMOS transistor 7 and the NMOS transistor 8 in the input stage, D is the voltage of the ground line 3, and E is the voltage of the power supply line 2, respectively. The voltage waveform is shown.

As shown in FIG. 10, the gates of the PMOS transistor 7 and the NMOS transistor 8 in the input stage are
Since the input protection diodes 20 and 21 are respectively connected between the sources, the input voltage C to the PMOS transistor 7 and the NMOS transistor 8 in the input stage is higher than the voltage D of the ground line 3 and the voltage E of the power supply line 2. It does not fall. As a result, a high potential difference is not applied to the gate oxide film of the MOS transistor 7 or 8 in the input stage. That is, the provision of the input protection diodes 20 and 21 greatly improves the resistance to electrostatic damage due to package charging.

It is self-evident that the input protection diodes 20, 21 are similar to the diodes 5a, 6a.
Causes a reverse bias in normal IC operation and causes no inconvenience. In addition, it does not adversely affect the electrostatic breakdown voltage in the human body model and the mechanical model. Further, since the purpose of the input protection diodes 20 and 21 is not to apply a high voltage to the gate oxide film, in addition to the diode by the PN junction, a diode-connected bipolar transistor,
A diode-connected MOS transistor, a Zener diode, or any other device having a voltage limiting function can be used instead.

Further, in the present example, the example in which the diodes on the power supply side and the ground side are paired is shown. However, even if only one of the diodes is connected to the surge corresponding to the positive side or the negative side, respectively. It goes without saying that it is effective.

[0034]

Fourth Embodiment FIG. 11 shows a fourth semiconductor circuit according to the present invention.
3 is a circuit diagram showing an embodiment of FIG. The fourth embodiment shows a semiconductor circuit provided with a protection circuit for an output circuit, unlike the above-described first embodiment, and configures an output buffer with a withstand voltage against electrostatic breakdown in a package charging model of the output circuit. This is improved by connecting a capacitor between the gate of the MOS transistor and the output terminal.

In FIG. 11, 31 is an output terminal and 32 is an output terminal.
Output buffers, 33 and 34 are output protection capacitors, 3
Reference numerals 5 and 36 denote gate circuits, respectively. Also, S
Is the package surface, C_PV, C_PV0Is the power line package
Quantity, C_PS, C _PS0Indicates the ground line package capacitance
are doing.

The output buffer 32 has PMs whose drains are connected to each other and whose connection points are connected to the output terminal 31.
OS transistor 32a and NMOS transistor 3
2b. The protection capacitor 33 is connected between the drain electrode and the gate electrode of the PMOS transistor 32a, and the NMOS transistor 32a
A protective capacitor 34 is connected between the drain electrode and the gate electrode of b. Furthermore, the gate electrode of the PMOS transistor 32a of the output buffer 32 is connected to the output of the gate circuit 35, and the gate electrode of the NMOS transistor 32b is connected to the output of the gate circuit 36.

The gate circuit 35 is composed of an inverter in which the gate electrodes and drain electrodes of the PMOS transistor 35a and the NMOS transistor 35b are connected to each other, and the gate circuit 36 similarly includes the gates of the PMOS transistor 36a and the NMOS transistor 36b. It is composed of an inverter in which electrodes and drain electrodes are connected to each other.

The source electrode of the PMOS transistor 32a of the output buffer 32 is connected to the power supply line 2b,
The source electrode of the NMOS transistor 32b is the ground line 3b.
It is connected to the. The source electrodes of the PMOS transistor 35a of the gate circuit 35 and the PMOS transistor 36a of the gate circuit 36 are connected to the power supply line 2a,
The source electrodes of the NMOS transistor 35b of the gate circuit 35 and the NMOS transistor 36b of the gate circuit 36 are connected to the ground line 3a. In this output circuit, in order to prevent noise on the power supply line or the ground line generated when the output buffer 32 operates from affecting other internal circuits and causing a malfunction, the power supply line and the ground line are internally provided. Separated from those for circuits inside the semiconductor circuit.

Here, when electrostatic discharge represented by the package charging model occurs at the output terminal 31, the PMOS transistor 32a and the NMO of the output buffer 32 are formed.
Gate circuit 3 for driving the S transistor 32b
In the MOS transistors used as the transistors 5 and 36, for example, a parasitic bipolar operates between the source and the drain so that a current flows, so that the gate oxide film is formed between the gate and the drain of the PMOS transistor 32a or the NMOS transistor 32b of the output buffer 32. High voltage enough to destroy However, with this configuration,
The protection capacitor 33 is connected between the drain electrode and the gate electrode of the PMOS transistor 32a, and
Since the protective capacitor 34 is connected between the drain electrode and the gate electrode of the transistor 32b, the voltage applied to the gate oxide film drops to a low voltage that does not destroy the gate oxide film. That is, the breakdown voltage against electrostatic breakdown represented by the package charging model is improved.

[0040]

Fifth Embodiment FIG. 12 shows a fifth embodiment of the semiconductor circuit according to the present invention.
3 is a circuit diagram showing an embodiment of FIG. The fifth embodiment differs from the fourth embodiment described above in that the PM of the gate circuit 35 is
The PMOS of the output buffer 32 of the OS transistor 35a
The NMOS transistor 35c is connected between the connection point with the gate of the transistor 32a and the NMOS transistor 35b, and the PMOS transistor 36a of the gate circuit 36 is connected.
The NMOS transistor 36c is connected between the connection point of the output buffer 32 with the gate of the NMOS transistor 32b and the NMOS transistor 36b.

The other structure is the same as that of the above-described fourth embodiment, and the same effect as that of the fourth embodiment can be obtained.

The gate circuits 35 and 36 can be of various types such as NAND type or NOR type.

[0043]

As described above, according to the semiconductor circuit of the present invention, the electrostatic breakdown represented by the package charging model is maintained while maintaining the resistance to electrostatic breakdown represented by the human body charging model or the machine model. There is an advantage that resistance to can be improved.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a semiconductor circuit according to the present invention.

FIG. 2 is a diagram for explaining the circuit characteristics of FIG.

FIG. 3 is a circuit diagram showing a second embodiment of the semiconductor circuit according to the present invention.

FIG. 4 is a diagram showing a test circuit of an input protection circuit corresponding to FIG.

5 is a diagram showing a voltage waveform of a main part in the circuit of FIG.

FIG. 6 is a circuit diagram showing a third embodiment of the semiconductor circuit according to the present invention.

FIG. 7 is a diagram showing a test circuit when the input protection circuit corresponding to FIG. 3 is evaluated by a package charging model.

8 is a diagram showing a voltage waveform of a main part in the circuit of FIG.

FIG. 9 is a diagram showing a test circuit when the input protection circuit corresponding to FIG. 6 is evaluated by a package charging model.

10 is a diagram showing a voltage waveform of a main part in the circuit of FIG.

FIG. 11 is a circuit diagram showing a fourth embodiment of the semiconductor circuit according to the present invention.

FIG. 12 is a circuit diagram showing a fifth embodiment of the semiconductor circuit according to the present invention.

FIG. 13 is a circuit diagram showing a conventional semiconductor circuit including an input protection circuit.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Input terminal 2 ... Power supply line 3 ... Grounding wire 4 ... Protective resistance element 5 ... Protecting PMOS transistor 6 ... Protecting NMOS transistor 7 ... Input PMOS transistor 8 ... Input NMOS transistor 9, 10 ... Protecting capacitor 20 , 21 ... Input protection diode 31 ... Output terminal 32 ... Output buffer 33, 34 ... Output protection capacitor 35, 36 ... Gate circuit S ... Package surface C _PV , C _PV0 ... Power line package capacitance C _PS , C _PS0 ... Ground Wire package capacity

Claims (3)

[Claims] 1. A semiconductor circuit for inputting an external signal to a gate electrode of a metal insulating film semiconductor transistor, wherein a capacitive element is connected between a gate input line of the metal insulating film semiconductor transistor and a power supply line. Semiconductor circuit. 2. A first circuit between an external signal input line and a power line.
2. The semiconductor circuit according to claim 1, wherein said diode is connected, and a second diode is connected in parallel to said capacitance element between the gate input line of said metal insulating film semiconductor transistor and a power supply line. 3. A metal insulating film semiconductor transistor connected between a power supply line and an output terminal, wherein a signal having a level corresponding to an input voltage to a gate electrode of the metal insulating film semiconductor transistor is output from the drain electrode to the output terminal. A semiconductor circuit for outputting, wherein a capacitive element is connected between the drain electrode and the gate electrode of the metal insulating film semiconductor transistor.