JPH08204553A - Abnormal clock detection circuit - Google Patents

Abstract

PURPOSE: To provide an abnormal clock detection circuit capable of detecting the break and the pulse increase of an input clock signal. CONSTITUTION: An input clock signal A is inputted to an up/down counter circuit 4 through an input counter circuit 1 as a count-up signal E and has the phase and the frequency synchronized by a PLO circuit 2, and this synchronized signal C is inputted to the up/down counter circuit 4 through an output counter circuit 3 as a count-down signal F, and an alarm signal is outputted from an alarm circuit 5 based on the counted result. Since the signal is continuously counted down in the case of the break of the clock and is continuously counted up in the case of the increase of clock pulses in this constitution, both of the break of the clock and the increase of clock pulses can be detected.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an abnormal clock detecting circuit, and more particularly to an abnormal clock detecting circuit for detecting a bit break in a clock receiving circuit.

[0002]

2. Description of the Related Art A conventional abnormal clock detecting circuit is disclosed in Japanese Patent Application No. 4-104615. FIG. 3 is a block diagram of this conventional abnormal clock detection circuit. The conventional abnormal clock detection circuit counts 1 / n (n is a positive integer of 2 or more) of the number of clocks of the input clock signal and outputs it as an input phase comparison signal;
A phase-locked oscillator circuit (PLO) that generates a clock signal with phase synchronization and frequency synchronization with the input clock signal by inputting the output phase comparison signal and the input phase comparison signal formed based on its own output ) 51,
One of the clock signals output from the phase-locked oscillator circuit 51
An output counter circuit 52 that counts / n and outputs as an output phase comparison signal, and a count of the input clock signal that is set by the input clock signal and reset by the output phase comparison signal. Alarm circuit 5 that determines the disconnection state and outputs an alarm signal
It was equipped with 3.

Since the number of input clocks counted by the alarm circuit 53 decreases when a clock loss of a certain period or more occurs, the decrease of the count is detected to determine the clock loss.

[0004]

However, although the conventional abnormal clock detection circuit can detect the complete disconnection state of the input clock signal, it cannot detect the pulse increase state of the input clock signal. It was

SUMMARY OF THE INVENTION An object of the present invention is to provide an abnormal clock detection circuit capable of detecting not only a complete disconnection state of an input clock signal but also a pulse increase state.

[0006]

In order to solve the above-mentioned problems, the present invention provides a phase-locked oscillating circuit that generates a signal that is phase-locked and frequency-locked with an input clock signal, and counts based on the input clock signal. An up-down counter circuit that counts up based on an output clock signal output from the phase-locked oscillator circuit; and an alarm circuit that generates an alarm signal based on the count result of the up-down counter circuit Is characterized by.

[0007]

When the input clock signal is normal, the count-up signal and the count-down signal are alternately input to the up-down circuit, so that the up-down counter circuit alternately outputs the numerical values of 0 and -1.

On the other hand, when the input clock signal becomes abnormal, the count-up signal shows an abnormal count according to the input clock signal, but the count-down signal does not change because it is controlled by the phase-locked oscillator circuit.

Therefore, when the input clock signal is disconnected, the up / down circuit continuously counts down, and when the input clock signal has increased pulses, it continuously counts up.

An alarm circuit detects this continuous up or down and outputs an alarm signal.

[0011]

Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a configuration diagram of an embodiment of an abnormal clock detection circuit according to the present invention.

The abnormal clock detection circuit counts the input clock signal A by 1 / m (m is a positive integer of 2 or more), outputs the count output as the input phase comparison signal B, and outputs the input clock signal A by k. (K is a positive integer including 1)
The input counter circuit 1 that divides and outputs the count-up signal E, and the output phase comparison signal D and the input phase comparison signal B that are formed based on its own output are input and phase comparison is performed. A phase-locked oscillator circuit (hereinafter referred to as a PLO circuit) 2 that generates an output clock signal C that is phase-locked and frequency-locked with an input clock signal A based on the difference, and 1 / n (where n is the output clock signal C). Two
The above positive integer) is counted, and the output clock signal C is frequency-divided to the same frequency as the count-up signal E by j (j is a positive integer including 1) while outputting the output as the output phase comparison signal D. The output counter circuit 3 which outputs as the countdown signal F, the updown counter circuit 4 which counts up or down by the countup signal E and the countdown signal F, and either one of the countup and the countdown is continuously performed. And an alarm circuit 5 for generating an alarm signal G.

Next, the operation of this abnormal clock detection circuit will be described.

The input counter circuit 1 receives the input clock signal A and is an input comparison signal B which is the 1 / m count number of the input clock signal A which is the phase comparison reference of the PLO circuit 2.
And output to the PLO circuit 2.

The output counter circuit 3 receives the output clock signal C output from the PLO circuit 2 and outputs 1/1 of the output clock signal C so that it has the same frequency as the input phase comparison signal B.
The output phase comparison signal D of n counts is converted and output to the PLO circuit 2.

The PLO circuit 2 compares the phases of the input phase comparison signal B and the output phase comparison signal D, and outputs the output clock signal C phase-synchronized and frequency-synchronized with the input clock signal A based on the phase comparison difference. Output.

The up-down counter circuit 4 has a count-up signal E output from the input counter circuit 1 and an output counter circuit 3 having the same frequency as the count-up signal E.
The countdown signal F output from is input to count up or count down. The up / down counter circuit 4 receives the output phase comparison signal D and resets the up / down counter circuit 4.

The alarm circuit 5 detects an abnormality in the input clock signal A based on the count signal H output from the up / down counter circuit 4 and outputs an abnormality signal G.

FIG. 2 is a timing chart showing the operation of the abnormal clock detection circuit. Note that A to H in the figure correspond to the signal names described above.

When the input clock signal A is normal as shown by A in the figure, the up / down counter circuit 4
Indicates that up and down are always repeated at the same frequency as indicated by H (1) in the figure, and the counter does not count beyond ± 1.

On the other hand, when the input clock signal A becomes abnormal as indicated by A'in the figure, the up / down counter circuit 4
Is a continuous up as shown in H (2) in the figure,
The down will continue and the balance will be lost.

When the count number of the input clock signal A increases, that is, when a clock signal such as A (1) of A'in the figure is generated, the count-up signal E is generated.
Since the number of counts of 'increases, the numbers that should be alternately counted as 0 and -1 are counted up as +1 and +2.

On the other hand, when the input clock signal A is cut off, that is, when the clock is not generated as in A (2) of A'in the figure, the countdown signal F alone counts -1, The countdown is -2, -3.

Therefore, if a count value of ± 2 or more is input from the up / down counter circuit 4 to the alarm circuit 5 before the output phase comparison signal D, which is the reset signal of the up / down counter circuit 4, is input. , The alarm circuit 5 is determined to be abnormal and the alarm signal G is output.

Although the fluctuation of the countdown signal F depends on the fluctuation of the output clock signal C, the output clock signal C of the PLO circuit 2 is usually highly accurate (frequency fluctuation and phase fluctuation are small) and the input clock signal C is small. Even if a signal such as A ′ is generated instantaneously, the output clock signal C is hardly affected, and as a result, the countdown signal F is maintained.

[0026]

According to the present invention, the count-up signal output based on the input clock signal and the count-down signal that is phase-synchronized and frequency-synchronized with the input clock signal are input to the up-down counter circuit. Since it is configured to count, it is possible to continuously count down when the input clock pulse is disconnected and continuously count up when the input clock pulse is increased.

Therefore, by detecting this continuous down or up, it is possible to detect not only the disconnection state of the input clock signal but also the pulse increase state.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment of an abnormal clock detection circuit according to the present invention.

FIG. 2 is a timing chart showing the operation of the abnormal clock detection circuit.

FIG. 3 is a configuration diagram of a conventional abnormal clock detection circuit.

[Explanation of symbols]

 1 Input Counter Circuit 2 Phase Synchronous Oscillation Circuit (PLO) 3 Output Counter Circuit 4 Up-Down Counter Circuit 5 Alarm Circuit

Claims (3)

[Claims] 1. A phase-locked oscillator circuit that generates a signal that is phase-locked and frequency-locked with an input clock signal, and an output clock that is counted up based on the input clock signal and that is output from the phase-locked oscillator circuit. An abnormal clock detection circuit comprising: an up-down counter circuit that counts down based on a signal; and an alarm circuit that generates an alarm signal based on the count result of the up-down counter circuit. 2. The input clock signal is counted by 1 / m (m is a positive integer of 2 or more) and the count output is output as an input phase comparison signal while the input clock signal is k (k
Is a positive integer including 1) and an input counter circuit for dividing and outputting as a count-up signal, and an input phase comparison signal formed based on its own output and the input phase comparison signal are input to perform phase comparison. And a phase-locked oscillation circuit that generates an output clock signal that is phase-locked and frequency-locked with the input clock signal based on the phase comparison difference, and 1 / n (n is a positive value of 2 or more) for the output clock signal. Counting) and outputting the output as the output phase comparison signal while dividing the output clock signal by the same frequency as the count-up signal by j (j is a positive integer including 1) and outputting it as a countdown signal. Output counter circuit, and an up / down counter that counts up or down by the count-up signal and the count-down signal. Pointer circuit and abnormal clock detection circuit according to claim 1, characterized in that it comprises a warning circuit which either the count-up or count-down is detected from being performed continuously generates an alarm signal. 3. The abnormal clock detection circuit according to claim 1, wherein the up / down counter circuit is reset by the output phase comparison signal.