JPH0820947B2 - Data processing device - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to a data processing device.

Prior Art FIG. 3 shows a conventional data processing device.
Reference numeral 1 is a computing device that performs computation. Reference numeral 102 is a bus control device for fetching data from the outside. An output data bus 103 transfers the output data of the arithmetic unit 101 and the bus control unit 102. Reference numeral 104 is a register file for inputting data on the output data bus 103. Reference numeral 105 denotes a flag information generation device that reads data from the output data bus 103 and generates information depending on the data for flag generation. Reference numeral 106 denotes a flag generation control device that generates a flag from the information generated by the flag information generation device 105 and the information that depends on the calculation for flag generation generated by the arithmetic operation of the arithmetic device 101.

The operation of the data processing apparatus configured as described above will be described below. First, the operation of an instruction (hereinafter referred to as a load instruction) for transferring data from an external memory to a general-purpose register inside the data processing device will be described. The bus controller 102 takes in data from the outside and outputs the data to the output data bus 103. And output data bus 103
The register file 104 reads the above data and writes it to a general-purpose register. At the same time, the flag information generator 105
Generates information for flag generation from the data of the output data bus 103, the flag generation control device 106 generates a flag, and the execution of the instruction ends. Next, the operation of an instruction for adding data and writing it to the register (hereinafter referred to as an addition instruction) is shown.
The data calculated by the arithmetic unit 101 is fetched and added, and the addition result is output to the output data bus 103. Then, the addition result on the output data bus 103 is written in the register.
Also in this case, the flag information generation device 105 generates information dependent on the data for flag generation from the addition result on the output data bus 103 in the same manner as the load instruction, and the flag generation control device 106 stores the information. The flag is generated from the information depending on the calculation for flag generation generated by the arithmetic operation of the arithmetic unit 101, and the execution of the instruction is completed.

However, in this configuration, instructions, especially highly functional instructions, are executed at high speed. That is, even if an operand fetch and a comparison instruction with no data storage are executed at the same time, the output data bus 10
3 has operand fetched data, the flag information generation device 105 reads the operand fetched data and generates information for flag generation, and the flag generation control device 106 generates a flag based on that information, so operand fetch and comparison instructions Had the problem that they could not be executed simultaneously.

In view of such a point, the present invention provides a data processing apparatus capable of executing parallel and parallel operations by only slightly increasing hardware and performing operand fetches that do not need to reflect flags and operations that do not need to write operation results and need only reflect flags. The purpose is to do.

Means for Solving the Problems The present invention provides one or a plurality of arithmetic units for performing an operation, an output data bus for transferring output data of the arithmetic unit, an operand fetch bus for transferring operand data, and the output. A data selection device for selecting a data bus and the operand fetch bus; an output data flag information generation device for generating data-dependent information for reading the data of the output data bus from the read data; An operand data flag information generation device for generating information depending on data for reading a flag from the data of the operand fetch bus, and an output from the output data flag information generation device and the operand data flag A flag information selection device for selecting an output from the information generation device; A flag for inputting information dependent on the data for flag generation selected by the information selection device and information dependent on the operation for flag generation generated by the arithmetic operation of the arithmetic device and generating a flag from the information It is a data processing device provided with a generation control device.

According to the present invention having the above-described structure, in the operand fetch, the data selection device selects the operand fetch bus and writes the operand fetched data in the register in the register file, and at the same time, the flag information selection device generates the operand data flag information. You can select a device and generate a flag. Further, in the operation execution, the data selection device selects the output data bus and writes the result of the operation executed by the operation device into the register in the register file, and at the same time, the flag information selection device selects the output data flag information generation device. Can generate flags. In the operand fetch that does not reflect in the flag, the data selection device selects the operand fetch bus and writes the operand fetched data to the register in the register file, and at the same time, the flag information selection device is the output data flag information generation device. It is possible to reflect only the flag of an operation that does not require writing the operation result executed by the operation device by selecting. Therefore, it is possible to execute an operand fetch that does not need to reflect the flag and an operation that does not need to write the operation result and only reflect the flag in parallel, and it is possible to reduce the execution cycle of instructions such as high-performance instructions and speed up. .

Practical Example FIG. 1 is a block diagram of a data processing apparatus of the present invention. In FIG. 1, reference numeral 1 is an arithmetic unit for performing arithmetic operations. An output data bus 2 transfers the output data of the arithmetic unit 1. Reference numeral 3 is a bus control device for controlling the fetching of data from the outside. Reference numeral 4 is an operand fetch bus for transferring the data of the bus controller 3. Reference numeral 5 is a data selection device for selecting the output data bus 2 and the operand fetch bus 4. Reference numeral 6 is a register file for inputting the data selected by the data selection device 5. Reference numeral 7 is an output data flag information generation device that reads data from the output data bus 2 and generates information depending on the data for flag generation from the data. Reference numeral 8 denotes an operand data flag information generation device for reading data from the operand fetch bus 4 and generating information depending on the data for flag generation from the data. Reference numeral 9 is a flag information selection device for selecting an output from the output data flag information generation device 7 and an output from the operand data flag information generation device 8. Reference numeral 10 is a flag for inputting the information dependent on the data for flag generation selected by the flag information selection device 9 and the information dependent on the operation for flag generation generated by the arithmetic operation of the arithmetic unit 1 to generate a flag. It is a generation control device.

The operation of the present embodiment configured as described above will be described below. In the load instruction, the bus controller 3 takes in data from the outside and outputs the data to the operand fetch bus 4. Then, the data selection device 5 selects the operand fetch bus 4 side, and the register file 6 reads the data and writes it in the register. At the same time, the operand data flag information generation device 8 reads the data on the operand fetch bus 4 and generates information depending on the data for reflecting the flag. Then, the flag information selection device 9 selects the operand data flag information generation device 8 side, the flag generation control device 10 generates a flag from the information, and the execution of the instruction ends. In the addition instruction, the arithmetic unit 1 takes in the data, adds it, and outputs the addition result to the output data bus 2. Then, the data selection device 5 selects the output data bus 2 side and the addition result is registered in the register file 6
Writes to the read register. At the same time, the output data flag information generation device 7 reads the data on the output data bus 2 and generates information depending on the data for flag generation. Then, the flag information selection device 9 selects the output data flag information generation device 7 side, and the flag generation control device 10 depends on the data and the operation-dependent information generated in the arithmetic device 1 for flag generation. The flag is generated and the execution of the instruction ends.

Since a high-performance instruction can be expanded into a plurality of basic instructions, one high-function instruction has a plurality of operand fetches and operation executions. In addition, the operand fetch that appears during the development of a high-performance instruction may not need to reflect the flag, and some operation execution instructions do not have to write the operation result like the comparison instruction and do the operation and only need to reflect the flag. There is something. Therefore, when both are executed simultaneously, the bus control device 3 takes in data from the outside and outputs the data to the operand fetch bus 4, the data selection device 5 selects the operand fetch bus 4 side, and the register file 6 operates the operands. Write the fetched data in the read register. In the same cycle, the arithmetic unit 1 takes in data, performs arithmetic operation, outputs the arithmetic result to the output data bus 2, and the output data flag information generation unit 7 reads the data on the output data bus 2 to generate a flag. Generate data-dependent information. Then, the flag information selection device 9 selects the output data flag information generation device 7 side, and the flag generation control device 10 depends on the information depending on the calculation result and the calculation for generating the flag generated in the calculation device 1. Generate flags from information. As described above, if there is an operand fetch in which a flag is not reflected in a high-performance instruction or the like and an operation execution in which an operation result is not written and only a flag is reflected, the two can be executed at the same time.

From the above, in the case of a high-performance instruction, the number of instruction execution cycles can be reduced and the instruction execution speed can be increased.

For example, compare the data (src1) on the memory with the content of R0 as the start address with the data (src2) on the memory with the content of R1 as the start address byte by byte.
An instruction that increments the address by 1 byte and repeats the comparison as long as the src2 is the same (hereinafter referred to as a string compare instruction)
There is. However, when src1 and src2 are not equal as the end condition of this repeated comparison, when src1 and R3 contents (end condition comparison value) are equal, and when R2 contents (number of data to be compared) become 0, 3 If there is one, and this condition is met, the comparison will end. FIG. 4 shows an explanatory diagram of the development of the microcode when the above string compare instruction is executed by the configuration of the conventional data processing device. Each cycle will be described below in sequence. However, one line of the microcode expansion in the figure corresponds to an execution cycle. First, in the first cycle, the arithmetic unit 101 subtracts 1 from the contents of R2 and the R2 in the register file 104 is transferred via the output data bus 103.
Write in. Next, in the second cycle, the bus controller 102 fetches the data in the memory whose address is the content of R0, and t
Write to mp1 (work register in register file 104). Similarly, the controller 102 fetches the data on the memory having the content of R1 as an address and writes it in tmp2 (work register in the register file 104). In the fourth cycle, the arithmetic unit 101 increments the content of R0 by 1, outputs it to the output data bus 103, and writes it to R0 of the register file 104. Similarly, in the fifth cycle, the arithmetic unit 101 increments the content of R1 by 1 and writes it to R1 via the output data bus 103. In the sixth, seventh, and eighth cycles, the arithmetic unit 101 performs subtraction and outputs it to the output data bus 103, and the flag information generation unit 105 generates the information dependent on the data for flag generation from the data and the flag generation control unit. The termination condition is checked by generating a flag from the information depending on the data and the information depending on the calculation for flag generation from the arithmetic unit 101. If the end condition is satisfied here, branch to label1 to end the instruction, and if not satisfied, lo
Branch to op and repeat the comparison. If the string comparison continues in this way, the microcode is looping and executing. Since the execution cycle in the loop is 9, if the instruction is looped n times before the end, the execution cycle of the instruction becomes 9n.

Next, FIG. 2 shows an explanatory diagram of the microcode expansion when the same string compare instruction is executed with the configuration of the above embodiment. First, in the first cycle, the arithmetic unit 1 subtracts 1 from the content of R2 and outputs it to the output data bus 2, the data selection unit 5 is selected on the output data bus 2 side, and the data is written to R2 in the register file 6. Be done. In the second cycle, the bus control device 3 fetches data from the outside and outputs it to the operand fetch bus 4, and the data selection device 5 selects the operand fetch bus 4 side and selects the register file 6
Write to the work register (tmp1). At the same time, the arithmetic unit 1 subtracts R2 from 0 and outputs the result to the output data bus 2. The output data flag information generation unit 7 reads the data and generates information dependent on the data for flag generation, The flag information selection device 9 selects the output data flag information generation device 7 side, and the flag generation control device 10 determines from the information dependent on this data and the information dependent on the operation for flag generation output from the arithmetic device 1. Generate a flag and check the end condition from this. Similarly, in the third cycle, the data fetched from the operand is written in the work register (tmp2) by selecting the data selection device 5 on the side of the operand fetch bus 4. In the same cycle, the arithmetic unit 1 subtracts the contents of tmp1 and the contents of R3 and outputs them to the output data bus 2, and the flag information selection unit 9 is set to the output data flag information generation unit 7 side so that the operation result is flagged. Is generated and the end condition is checked. In the fourth and fifth cycles, the arithmetic unit 1 performs addition in the same manner as in the first cycle, and the data selection unit 5
Is set to the output data bus 2 side and written in the register in the register file 6. In the sixth cycle, the end condition is checked, and if the end condition is satisfied, the process ends. If it does not, the process branches to loop and repeats the comparison. As described above, in this embodiment, the operand fetch not reflecting the flag and the operation execution not writing to the register but only reflecting the flag can be executed at the same time. Can be checked at the same time as the operand fetch. The second and third cycles of FIG. 2 are the cycles in which the operand fetch and the end condition are checked at the same time. As a result, the number of cycles in the microcode expansion loop is reduced by 2 cycles compared to the conventional one, and the instruction execution cycle becomes 7n. Therefore, the instruction can be executed 2n cycles faster than the conventional instruction execution, and the effect is great especially when the number of repetitions is large.

Further, according to the present invention, even if a plurality of arithmetic devices are connected to the output data bus, only one device for generating information for flag generation depending on the data of the operation result is connected to the output data bus. This effect is great because it can be realized only by increasing the hardware.

As described above, according to the present invention, in the case of an operand fetch, in the case of an operand fetch, the flag information selection device is selected as the operand fetch bus and the operation is executed. By selecting the flag information selection device for the output data bus, it is possible to reflect the flag along with the operand fetch and the operation execution.
For operand fetches that do not need to reflect the flags that appear in high-function instructions, the fetched data is written to the register by selecting the data selection device on the operand fetch bus, and at the same time the operation result is written. By executing a non-operation in the arithmetic unit and selecting the flag information selection unit for the output data bus,
The selection result can be reflected in the flag at the same time as the operand fetch. That is, it is possible to execute an operand fetch that does not need to reflect a flag and an operation that does not need to write an operation result in parallel, reduce the instruction execution cycle, and speed up the instruction execution. In particular, when the operand fetch is in a loop of an instruction that is repeatedly executed, such as a high-performance instruction, the effect becomes large. Moreover, in the present invention, even if a plurality of arithmetic devices are connected to the output data bus, only one device that generates information for flag generation depending on the data of the operation result is connected to the output data bus. The practical effect is great because it can be realized with a slight increase in hardware.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is an explanatory diagram of the expansion of microcode when executing a high-performance instruction in the above embodiment, and FIG. 3 is a conventional data processing device. FIG. 4 is a diagram showing the construction of a microcode when a high-performance instruction is executed in a conventional data processing device. 1 ... Arithmetic unit, 2 ... Output data bus, 3 ... Bus control unit, 4 ... Operand fetch bus, 5 ... Data selection unit, 6 ... Register file, 7 ... Output data flag information Generation device, 8 ... Operand data flag information generation device, 9 ... Flag information selection device, 10 ... Flag generation control device, 101 ... Arithmetic device, 102 ... Bus control device, 103 ... Output data bus , 104 ... register file, 105 ... flag information generation device, 106 ... flag generation control device.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Tsunezo Adachi 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (56) References JP 61-100836 (JP, A) JP 58- 60355 (JP, A) JP-A-2-100134 (JP, A)

Claims (1)

[Claims] 1. One or more arithmetic units for performing arithmetic operations,
An output data bus for transferring output data of the arithmetic unit, an operand fetch bus for transferring operand data, a data selection device for selecting the output data bus and the operand fetch bus, and the data selection device. A register file that stores the selected data,
A flag information generation device for output data, which generates information depending on the data for reading the data of the output data bus from the read data, and data for the flag generation from the read data of the operand fetch bus Operand information flag information generating device for generating information dependent on the flag, a flag information selecting device for selecting an output from the output data flag information generating device and an output from the operand data flag information generating device, and the flag Flag generation for inputting information dependent on data for flag generation selected by the information selection device and information dependent on calculation for flag generation generated by the arithmetic operation of the arithmetic device, and generating a flag from the information In the case of operand fetch, the data selection device includes a control device A bus for data selection, the flag information selection device selects the flag information generation device for operand data to generate a flag at the same time as the operand fetch, and when executing an operation, the data selection device selects the output data bus and The flag information selection device selects the output data flag information generation device to generate a flag while executing an operation, and in the case of an operand fetch that does not reflect the flag, the data selection device selects an operand fetch bus to select the flag information. A data processing device, wherein the device can select the output data flag information generating device and simultaneously execute operand fetch and operation flag reflection.