JPH08211129A - Abnormality monitor built in semiconductor ic test equipment - Google Patents

Abstract

PURPOSE: To build an abnormality monitor in a semiconductor IC tester for monitoring the abnormality entirely including the abnormality of a built-in detection block. CONSTITUTION: Reference clock of the abnormality monitor is provided as a clock signal generator 21 and each semiconductor IC test equipment is provided with a detection block. Abnormality signal from the detection block is transmitted on a signal system, i.e., a data bus, of the test equipment. A sensor 1 is provided in combination with an AND gate 31 while a sensor 2 is provided in combination with an AND gate 32 and a one-shot flip-flop 71 receiving the output from the final AND gate in a detection block is provided while setting a time constant. Upon occurrence of an abnormality, the CPU in the test controller unit 91 of the semiconductor IC tester is interrupted by a trigger delivered from the one-shot flip-flop 71 and the test controller unit 91 takes scheduled preventive measures.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an abnormality monitoring device built in a semiconductor IC test apparatus for incorporating a detection block therein and monitoring an abnormality of the entire semiconductor IC test apparatus including an abnormality of the detection block.

[0002]

2. Description of the Related Art A semiconductor IC tester (hereinafter referred to as a tester) has many built-in electronic unit devices, and the electronic unit device has many built-in boards (hereinafter referred to as boards) on which ICs and other electronic components are mounted. When the tester is operated, the amount of heat generated by the board is large. For example, at room temperature of 20 ° C, the room temperature in the tester housing rises to 40 ° C even by forced air cooling. The failure rate increases and the allowable operating temperature of electronic parts does not exceed, but during long-term use,
It was also a problem that affected the reliability of the tester. In order to respond to the high reliability of the tester, it was necessary to detect and inform the abnormality of the tester early.The abnormality of the tester means that the refrigerant leaks from the heat exchanger, dew condensation occurs, the temperature of a specific part of the power supply is high, Is not rotating, the door is not closed, etc., there has been an anomaly monitoring / sensing device for early detection and notification of overall anomalies for the maintenance of these testers.
That is, the detection blocks that detect anomalies are scattered at various locations on the electronic unit device of the tester, and the detection blocks are connected to the data buses at the various locations of the electronic unit device of the tester to connect the data bus. It was used as a system for abnormal signal transmission.

Referring to FIG. It is a perspective view which notched a part of tester housing | casing of a prior art. A detection block 9 composed of an OR gate for detecting an abnormality and a sensor,
10, 11, 12, 13, 14, 15, 16, 17 as a whole unit 101, 102, 103, 104, 10
5, 106, 107 and AC controller unit 9
For example, the unit 101 is a power supply unit, 104 is a pattern generator unit,
Reference numeral 105 is a fan unit, and 106 is a timing generator unit or the like. Tester controller
The data bus 120 extending from the unit 91 to each place of each unit was used as a system for transmitting an abnormal signal of each detection block. For example, if one of the detection blocks detects an abnormality, the tester controller unit 91 makes a judgment by the data bus 120, and if an instruction to turn off the power is issued, the AC controller unit 92 executes off according to the instruction.

Referring to FIG. It is a block diagram of a prior art abnormality monitoring device. When the signals of the sensors 7 and 8 of each detection block enter the OR gate 47 through the output of the OR gate 46 using the data bus 120, the detected OR gate 47 uses the data bus 120 to output the tester controller. -It is a configuration that interrupts the unit 91.
The detection block is asynchronous with the basic clock signal of the tester, and a plurality of detection blocks connected in series in the tester are arranged at various places. For example, as soon as the sensor 8 of the detection block detects an abnormality, it enters the OR gate 47 and interrupts the tester controller unit 91 using the data bus 120 through the OR gate of the detection block in the middle, and the tester controller unit 91 is interrupted. 91
Makes judgments and takes planned actions. If the OR gate 47 is broken when a signal is input to B by using the data bus 120 at the previous stage, the signal detected at the stage before B is interrupted there and the essential tester controller unit. There was a problem that I could not reach 91, but I did a regular maintenance to guarantee it. There is a problem that the power supply is turned off although the detection block is affected by electric noise from the outside and the tester is not abnormal.

[0005]

A circuit is required that is always found even if each detection block fails and an abnormal signal is input to the tester controller unit. Since a sensor with good sensitivity is affected by electrical noise from the outside, a circuit for distinguishing an internal abnormality from an external abnormality was necessary. An object of the present invention is to provide an abnormality monitoring device configured to constantly send a clock signal to a detection block and determine an abnormality when the clock signal does not come out normally from the output of each detection block.

[0006]

In order to achieve the above object, in the present invention, the detection block has a circuit configuration in which an AND gate and a sensor are combined. While the clock signal is always sent to the detection block and the clock signal is normally input and output, the output of the detection block indicates that the clock signal is output as it is and there is no abnormality, and the abnormality signal is sent from the sensor of the detection block. And the output of AND gate becomes high level and AND gate is closed, the trigger of the one-shot flip-flop is stopped, and the CPU of the tester controller unit
It has a circuit configuration that can monitor interrupt abnormalities. Since the sensitive sensor is affected by external electric noise, the one-shot flip-flop 71 is provided with a time constant in order to limit the duration of noise and distinguish external noise from internal noise.

[0007]

EXAMPLE FIG. 1 will be described. FIG. 1 is a block diagram of an abnormality monitoring device according to an embodiment. The circuit configuration of the detection block is a combination of AND gates 31 and 32 and sensors 1 and 2. A plurality of detection blocks are arranged in each unit and connected to the one-shot flip-flop 71 using the data bus 120. The detection block is provided so that the signal of the clock signal generator 21 can be input to the AND gate 31, and the detection block is the output of the sensor 1 and the clock signal generator 21.
The AND gate 31 for inputting the signal of is provided, and the detection block of the next stage is provided with an input using the data bus 120 for the output of the AND gate 31 and an AND gate 32 for inputting the output of the sensor 2, The output of the AND gate 32 is input to the AND gate of the detection block in the next stage by using the data bus 120. A plurality of detection blocks are connected in series to the data bus 120 of the tester, and the output of the last stage of the detection block is input to the one-shot flip-flop 71 of the re-trigger. The one-shot flip-flop 71 has a circuit configuration in which the output of the one-shot flip-flop 71 can be input to the CPU of the tester controller unit 91. The output D of the one-shot flip-flop 71 becomes a low level within 20 ms after the falling signal is input to the C of the one-shot flip-flop 71. When the falling signal is input, the output D of the one-shot flip-flop 71 is maintained in the low level state.

FIG. 2 is a timing chart of a normal state and an abnormal state of the abnormality monitoring device of one embodiment. The timing chart of the normal state in FIG. 2 will be described. The cycle of the clock signal generator 21 is set to 5 ms, for example. A represents the input signal 5 ms of the detection block. B represents an abnormal signal output from the sensor 2 of the detection block. Since it is in a normal state, there is no output from the sensor 2 of the detection block. C represents the trigger input of the re-trigger one-shot flip-flop 71. D represents the output of the re-trigger one-shot flip-flop 71 set to a time constant of 20 ms, for example.

The timing chart of the abnormal state shown in FIG. 2 will be described. A represents an input signal of the detection block, for example, 5 ms. As a result of the sensor 2 detecting an abnormality and setting the input B of the AND gate 32 to a high level to close the AND gate 32, the trigger of the re-trigger one-shot flip-flop 71 is stopped. Since the one-shot flip-flop 71 is set to, for example, 20 ms, the result is, for example, 20 m from the last trigger input.
After s, it becomes a high level state and interrupts the CPU.
If the trigger input C of the re-trigger one-shot flip-flop 71 is stopped for some reason, the output D of the one-shot flip-flop 71 becomes a high level state, for example, 20 ms after the last trigger is input, When the trigger is returned to C of the one-shot flip-flop 71 within 20 ms, which interrupts the CPU of the controller unit 91, the D of the one-shot flip-flop 71 becomes a low level state.

FIG. 4 is a block diagram of an abnormality monitoring device according to a modified embodiment A for explaining FIG. 3. The detection block is provided with the sensor 3 and the diagnostic circuit 130, and the output of the sensor 3 and the diagnostic circuit 130 are provided.
The OR gate 41 for inputting the output of the OR gate 41 is provided, and the AND gate 33 for inputting the signal of the clock signal generator 21 and the output of the OR gate 41 is provided. The output of the AND gate 33 uses the data bus 120. Input to the AND gate 34 of the detection block in the next stage. The detection block in the next stage is provided with the sensor 4 and the diagnostic circuit 131, provided with an OR gate 42 for inputting the output of the sensor 4 and the output of the diagnostic circuit 131, and inputs the output of the AND gate 33 and the output of the OR gate 42. A possible AND gate 34 is provided, and the output of the AND gate 34 is input to the AND gate of the detection block of the next stage using the data bus 120. A plurality of detection blocks are connected in series to the data bus 120 of the tester, and the output of the last stage of the detection block is input to the re-trigger one-shot flip-flop 71. The one-shot flip-flop 71 has a time constant. The output of the one-shot flip-flop 71 is input to the CPU of the tester controller unit 91.

The self-diagnosis circuit of FIG. 3 will be described. The diagnostic circuit of each detection block is sequentially activated from the tester controller unit 91 to perform self-diagnosis. A one-shot flip-flop 72 is provided, the input of the one-shot flip-flop 72 is connected to the same point as the input of the one-shot flip-flop 71, and the time constant of the re-trigger one-shot flip-flop 72 is, for example, 6 m.
One-shot flip-flop 7
The SR flip-flop 73 for inputting the output of 2 is provided, and the output of the SR flip-flop 73 is connected to the tester controller unit 91. The SR flip-flop 73 is reset by the tester controller unit 91. You can do it.

FIG. 4 is a timing chart of a self-diagnosis state, a normal state and an abnormal state. The self-diagnosis state of FIG. 4 will be described. For example, the signal of the clock signal generator 21 is set to have a period of 5 ms, for example. E represents the input signal 5 ms of the detection block. H activates the diagnostic circuit 130 from the tester controller unit 91 to generate a trigger of 6 ms, for example. F inputs a 6 ms trigger to the AND gate 34 and outputs a 6 ms trigger from the AND gate 34. I is clock input from all stages E and F 6m
The one-shot flip-flops 71 and 7 for re-triggering the output of the AND gate 34 to which the s trigger signal is input.
2, the time constant of the re-trigger one-shot flip-flop 71 is, for example, 20 ms, and the period of the input trigger is within 20 ms so that it is not output to J. It is the re-trigger one-shot flip-flop 71. Since the time constant of is 20 ms, the trigger is restored within 20 ms, so the low level state is maintained. K has a time constant of 6 m
Diagnostic one-shot flip-flop 7 set to s
2 output is shown. One-shot flip-flop 72
Triggers at the falling edge of the input signal from I and outputs a LOW level signal to the output K for 6 ms.
When the next falling edge is input within 6 ms, the LOW level is maintained. In the example, the falling edge from I is 10
There is a break for ms, in this case the one-shot flip-flop 72 outputs a LOW level to the output K for 6 ms from the input of the last falling edge, and then outputs a HIGH level. When the input of the falling edge from I resumes, K outputs the LOW level again. L is an output of the set / reset flip-flop 73, which is brought to a high level state by a trigger from the output K of the one-shot flip-flop 72, and an interrupt occurs in the CPU of the tester controller unit 91. This confirms that the abnormality monitoring device is operating normally and resets it.

The normal state of FIG. 4 will be described. The cycle of the clock signal generator 21 is set to 5 ms, for example. G represents the input signal 5 ms of the detection block. H represents an abnormal signal output from the sensor 4, and there is no output from the detection block because it is in a normal state. F indicates that the output from the OR gate 42, which is the input of the AND gate 34, is at the low level. I represents a trigger input of the re-trigger one-shot flip-flop 71 with a period of 5 ms. J represents the output of the re-triggered one-shot flip-flop 71 having a time constant of 20 ms, for example. K has a time constant of 6 m, for example
s re-trigger one-shot flip-flop 7
Represents the output of 1. L represents the output of the set / reset flip-flop 73.

The abnormal state of FIG. 4 will be described. The cycle of the clock signal generator 21 is set to 5 ms, for example. E represents the input signal 5 ms of the detection block. G represents a state in which the sensor 4 outputs an abnormal signal. F represents a state in which an abnormal signal is input to the OR gate 42, which is the input of the AND gate 34, and the output is at a high level. I is a trigger input of the re-trigger one-shot flip-flop 71 and represents a high level state. J is a time constant of, for example, 20 ms, the re-trigger flip-flop 71 becomes high level after 20 ms, and the CP of the tester controller unit 91 becomes CP.
It means to interrupt U. The input of the one-shot flip-flop 72 is the one-shot flip-flop 7.
Since it is the same as the input of 1, the output of the one-shot flip-flop 72 to which the output in the high level state is input is the output K.
Becomes a high level state, SR flip-flop 7
3 is in a set state and occludes the CPU of the tester controller unit 91, but since it is for self-diagnosis, it is not judged to be abnormal even if it becomes a high level state in this system.

FIG. 5 is a block diagram of an abnormality monitoring device of the modified B embodiment. FIG. 5 of the abnormality monitoring device for performing automatic / self-diagnosis will be described. The detection block is the sensor 3 and the diagnostic circuit 13.
0, an OR gate 41 for inputting the output of the sensor 3 and the output of the diagnostic circuit 130, a frequency divider 51 for periodically activating the diagnostic circuit 130, and a signal of the clock signal generator 21 and OR An AND gate 33 that can input the output of the gate 41 is provided, and the output of the AND gate 33 is input to the AND gate 34 of the detection block in the next stage using the data bus 120. The detection block in the next stage is provided with a sensor 4 and a diagnostic circuit 131, an OR gate 41 for inputting the output of the sensor 4 and the output of the diagnostic circuit 131, and a frequency divider 52 for periodically activating the diagnostic circuit 131. , AND gate 34 that can input the output of AND gate 33 and the output of OR gate 42 is provided.
The output of 4 is input to the AND gate of the detection block of the next stage by using the data bus 120. A plurality of detection blocks are provided by connecting to the data bus 120 of the tester in series,
The output of the last stage of the detection block is provided with re-triggered one-shot flip-flops 71 and 72. The one-shot flip-flops 71 and 72 have a time constant and the output of the one-shot flip-flop 71 is input. The OR gate 45 is provided, and the tester controller unit 91 for inputting the output of the OR gate 45 is provided. Re-trigger one-shot flip-flop 72
A tester controller unit for inputting the output of the OR gate 45 to the OR gate 45 by setting the time constant of the re-trigger one-shot flip-flop 75 Connect with 91.

FIG. 6 will be described. It is a timing chart of the abnormality monitoring device of the modification B embodiment. The automatic / self-diagnosis status will be explained. The signal of the clock signal generator 21 is, for example, 5
Set to ms. E represents the input signal 5 ms of the detection block. H indicates that the diagnostic circuit 131 is activated by the frequency divider 52 at intervals of, for example, 50 ms and a trigger of, for example, 5 ms is generated. F synchronizes with H and inputs a 5 ms trigger and outputs a 5 ms trigger. I is 50 ms when the output of the AND gate 34 to which a 5 ms trigger is input is input to the re-trigger one-shot flip-flops 71 and 72.
Output at intervals of. K is the output of the one-shot flip-flop 72, and the time constant is 6 m after the trigger from I is cut off.
After s, a 4 ms trigger is output at 50 ms intervals. M
Inputs a 4 ms trigger to the re-trigger one-shot flip-flop 72, but since the time constant is 100 ms, the output maintains a low level state. The low-level state from the preceding stage is input to N, and the OR gate 45 is also maintained at the low-level state. If this state is maintained, it indicates that the abnormality monitoring device is operating normally. Explain abnormal condition of automatic / self-diagnosis. For example, M periodically activates the diagnostic circuit 131 at intervals of, for example, 50 ms. If there is no output at H and there is no output, the time constant of the re-triggered one-shot flip-flop 75 is 100 ms, for example. 100 ms after the last trigger of 4 ms of the output K of
After that, the trigger of the one-shot flip-flop 73 is stopped and becomes a high level state. N is OR gate 45
Tells the CPU of the tester controller unit 91 of the high level state of the preceding stage to indicate the abnormal state of the automatic self-diagnosis.

[0017]

Since the present invention is configured as described above, it has the following effects. When an unspecified detection block fails, if the clock signal does not reach the detection block of the next stage, it becomes a high level from the point when the time constant of the one-shot flip-flop is exceeded and the trigger stops and the tester The CPU of the controller unit is interrupted by an abnormal signal, and the abnormality of the tester can be monitored. It has become possible to diagnose and monitor the abnormality monitoring device manually and automatically. Even if external noise is mixed in the path from the sensor to the one-shot flip-flop for abnormality detection, or if the trigger input of the one-shot flip-flop is disturbed, the disturbance is within the time constant of the one-shot flip-flop. Once recovered, it will not be detected as an anomaly.

[Brief description of drawings]

FIG. 1 is a block diagram of an abnormality monitoring device according to an embodiment of the present invention.

FIG. 2 is a timing chart of a normal state and an abnormal state of the abnormality monitoring device according to the embodiment of the present invention.

FIG. 3 is a block diagram of an abnormality monitoring device of a modified example A of the present invention.

FIG. 4 is a timing chart of a self-diagnosis state, a normal state, and an abnormal state of the abnormality monitoring device of the modified example A of the present invention.

FIG. 5 is a block diagram of an abnormality monitoring device of a modified example B of the present invention.

FIG. 6 is a timing chart of an automatic / self-diagnosis state and an abnormal state of the abnormality monitoring device of the modified example B of the present invention.

FIG. 7 is a block diagram of an abnormality monitoring device according to an embodiment of the prior art.

FIG. 8 is a perspective view in which a part of a tester housing according to an embodiment of the related art is cut away.

[Explanation of symbols]

 1, 2, 3, 4, 7, 8 sensor 9, 10, 11, 12, 13 detection block 14, 15, 16, 17 detection block 21 clock signal generator 31, 32, 33, 34 AND gate 41, 42 , 45, 46, 47 OR gate 51, 52 frequency divider 71, 72, 75 one-shot flop flop 73 SR flop flop 91 tester controller unit 92 AC controller unit 101 power supply unit 104 pattern Generator unit 105 Fan unit 106 Timing generator unit 102, 103, 107 unit 120 Data bus 130, 131 Diagnostic circuit

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[Procedure amendment]

[Submission date] February 20, 1996

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] Claim 2

[Correction method] Change

[Correction content]

[Procedure Amendment 2]

[Document name to be amended] Statement

[Name of item to be corrected] Claim 3

[Correction method] Change

[Correction content]

Claims (3)

[Claims] 1. A tester controller unit (9
1) and a data bus (120) for transmitting a signal thereto, and in an abnormality monitoring device for detecting an abnormality in the entire semiconductor IC test device, a clock signal generator (21) serving as a reference clock of the abnormality monitoring device A signal is provided to the AND gate (31, 32) so that the sensor (1, 2) and the AND gate (31, 32) are combined to provide a detection block, and the AND gate (31) is provided with the sensor (1 ) And the output of the clock signal generator (21) are connected so that the output of the AND gate (31) is connected to the AND gate (3).
2) is connected using a data bus (120) to input, and the output of the sensor (2) is input to AND gate (3).
2) and the output of the AND gate (32) is connected to the AND gate of the detection block in the next stage using the data bus (120) and connected to the last AND gate of the detection block. One-shot flip-flop (7
1) The time constant is set and provided, and the output of the one-shot flip-flop (71) is connected so as to be input to the tester controller unit (91). Semiconductor IC
Abnormality monitor built into the test equipment. 2. In addition to the constituent means according to claim 1, an OR circuit for providing an output of the sensor (3) and an output of the diagnostic circuit (130) with a sensor (3) and a diagnostic circuit (130) provided in the detection block. A gate (41) is provided, and the signal of the clock signal generator (21) and the OR gate (4) are provided.
An AND gate (33) for inputting the output of 1) is provided,
The output of the AND gate (33) is input to the AND gate (34) of the next stage using the data bus (120). The sensor (4) and the diagnostic circuit (13) are input to the detection block of the next stage.
1) is provided, the output of the sensor (4) and the diagnostic circuit (131)
An OR gate (42) for inputting the output of the AND gate is provided, and the output of the AND gate (33) and the OR gate (42)
An AND gate (34) for inputting the output of the detection block is provided, and the output of the AND gate (34) is input to the AND gate of the detection block of the next stage using the data bus (120). The output of the data bus (12
0) using one-shot flip-flop (71,
The data bus (120) is connected so that the command for self-diagnosis of the tester controller unit (91), which is input to 72), is input to the diagnostic circuit (130, 131), and the time constant is set. One-shot flip-flop (7
2) is connected to the SR flip-flop (75), and is connected to the tester controller unit (91) for inputting the output of the SR flip-flop (73). Semiconductor IC characterized by
Abnormality monitor built into the test equipment. 3. A clock signal generator (21) comprising a frequency divider (51, 52) for periodically activating a diagnostic circuit (130, 131) in addition to the constituent means according to claim 1.
Is connected so as to be input to the diagnostic circuit (130, 131), and a one-shot flip-flop (73) for inputting the output of the one-shot flip-flop (72) is provided, and the output of the OR gate (45) is provided. Tester controller
A semiconductor IC characterized in that it has the above-mentioned configuration, which is connected so as to be input to a unit (91).
Abnormality monitor built into the test equipment.