JPH08211363A - Active matrix panel - Google Patents

Abstract

PURPOSE: To provide a small-sized high-speed active matrix panel by performing image processing, particularly one for noise removal without imposing any burden on the MPU. CONSTITUTION: The panel is constituted from a first transparent substrate to which plural gate lines 103, plural source lines 102, and a thin-film transparent transistor are connected and which has pixels arranged in a matrix; a second transparent substrate disposed oppositely to the first transparent substrate; a liquid crystal interposed between the first and second substrates; and at least either of gate line driver circuit 123 and source line driver circuit 124 composed from a complementary, P-type or N-type thin film transistor and a processing circuit which is composed of a P-type, N-type or complementary thin film transistor and processes the pixel data to supply them to the source lines.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix panel using thin film transistors.

[0002]

2. Description of the Related Art FIG. 12 is a block diagram of a conventional liquid crystal display device. As disclosed in JP-A-1-289917, in the active matrix panel 11, the source line driver circuit 12, the gate line driver circuit 13, and the pixel matrix 14 are formed on the same substrate.

The source line driver circuit 12 is composed of a shift register 15 and a sample hold circuit 16 composed of thin film transistors, and is connected to the pixel matrix 14 by a source line 17. The gate line driver circuit 13 is composed of a shift register 18 and a buffer circuit 19, and is connected to the pixel matrix 14 by a gate line 20. The pixel matrix 14 has a source line 17
Pixels 22 are formed at intersections between the gate lines 20 and the gate lines 20, and the pixels 22 are composed of thin film transistors 23 and liquid crystal cells 24.

FIG. 13 is a system block diagram of image data processing of a conventional liquid crystal display device, which is stored in a storage device (Random-Access-Memory) using software by a microcomputer (ultra-small arithmetic processing device). The system which performs the data processing of the image data which was performed is shown. As shown in FIG. 13, in the liquid crystal display device 31, via the DA conversion circuit 32,
A data bus 35 connects a storage device 33 for storing image data and an image processing system 34 including a microcomputer to enable input / output. Further, the liquid crystal display device 31, D
A control signal is input to the A conversion circuit 32 from the image processing system 34 through the control signal line 38. Further, the output of the image processing system 34 is connected to the storage device 33 by an address bus 36 and a control signal line 37, respectively.

When displaying an image, a program is created in advance for the image processing contents in C language or the like, the image processing system 34 compiles the program, and the storage device 33 is controlled based on the contents. , The stored image data is read and image processing is performed. Then, the processed image data is written in the storage device 33 again.
Alternatively, via the DA conversion circuit 32, the liquid crystal display device 31
Output to and display. That is, the active matrix type liquid crystal display device has only a display function.

[0006]

However, since the conventional active matrix panel has only the function of displaying image data, the following problems occur. (1) Miniaturization of display devices and systems is hindered. Conventionally, as shown in FIG. 12, the active matrix panel has only a circuit for driving each pixel of the pixel matrix,
The circuitry for displaying the pixel matrix, and in particular for accessing the image processing computing system, is external to the active matrix panel. In recent years, the amount of image data has become huge and complicated data processing has been performed, so that the amount of external calculations has become large, and it is difficult for the MPU to follow the calculations. Therefore, in order to reduce the load on the MPU, an external arithmetic unit is exclusively incorporated in the semiconductor integrated circuit to solve the problem. However, since the number of parts of the image display device including the image processing increases, miniaturization of the system is hindered.

(2) Further, there is a useless area on the panel. Since the conventional active matrix panel is composed of pixel, gate line, and source line driver circuits, there is an empty region on the panel. If external parts can be placed in the empty area, the physical space forming the display system can be further contributed to miniaturization if possible.

(3) The high-speed operation of the image processing system is hindered. MPU of system other than panel to control pixels
It is necessary to operate the (ultra-compact processor), but the image processing technology has become complicated year by year, and the software for it has become complicated and huge. Therefore, the processing time of the data of the MPU is long, but the time for accessing the storage device is also long. This is because the MPU occupies the data bus especially for accessing the storage device. In order to solve this, it is effective to prepare dedicated hardware and perform parallel processing, but the number of parts increases. Therefore, giving priority to reducing the number of parts rather than providing a parallel processing system sacrifices the high-speed operation of the system and imposes a burden on the MPU. An object of the present invention is to solve the above-mentioned problems (1) to (3), to provide an active matrix panel capable of speeding up image processing and downsizing the apparatus.

[0009]

In order to achieve the above object, an active maritrix panel according to the present invention has a plurality of gate lines, a plurality of source lines and thin film transistors connected to each other and arranged in a matrix. A first transparent substrate having pixels, a second transparent substrate facing the first transparent substrate, and interposed between the first transparent substrate and the second transparent substrate. In an active matrix panel having a liquid crystal and at least one of a gate line driver circuit and a source line driver circuit, which is composed of a P-type, N-type or complementary thin-film transistor, a P-type, N-type or complementary thin-film transistor is used. And a processing circuit for processing the image data supplied to the source line, (1) P-type or N-type or complementary thin type Reference clock generation circuit composed of film transistor (2) Counter circuit composed of P type or N type or complementary thin film transistor (3) Frequency divider circuit composed of P type, N type or complementary thin film transistor (4) P type or N Circuit for transmitting a signal from the outside to the active matrix panel composed of thin film transistors of complementary type or complementary type (5) Transmission circuit for transmitting a signal from the active matrix panel composed of thin film transistors of P type or N type or complementary type to the outside (6) Bidirectional transmission circuit for transmitting signals from the active matrix panel made of P-type, N-type or complementary type thin film transistors to the outside and from the outside to the inside of the active matrix panel. The processing circuits are the circuits (1) to (6) described above. At least two It has a circuit of.

In the above structure, the thin film transistor forming the circuit may be, for example, a MOS transistor using a silicon thin film.

[0011]

In the active maritrix panel according to the present invention having the above-mentioned configuration, the image data is read from the plurality of external storage devices storing the image data in the processing circuit, processed, and processed. The image data is transmitted to the pixel and displayed. That is, the active maritrix panel according to the present invention not only drives the pixel matrix, but also executes an operation to transmit a signal to the outside and also controls an external device such as a storage device. In this way, it is possible to calculate image data, directly access a plurality of storage devices, and perform data processing to be displayed on the pixel matrix with as few components as possible without particularly relying on the MPU.

[0012]

The present invention will be described in detail with reference to the embodiments shown below. [Embodiment 1] In Embodiment 1, a method of mask processing (reduction of screen noise) is taken as a concrete image processing. This mask processing is, for example, processing required when image data is generated from an image reading device (handy scanner or the like), correction of the image, particularly removal of isolated point noise.

FIG. 1 is a block diagram of an active matrix panel of Example 1, and the circuits shown below are formed on the same transparent substrate. In the active matrix panel 101, N source lines 102 and M gate lines 103 are arranged in a grid pattern, and the pixels 104 are the source lines 1.
02 and the gate line 103 are connected to each other. In this state, N pixels 104 are arranged horizontally (in the X-axis direction) and M pixels vertically (in the Y-axis direction) to form an N × M matrix. Arbitrary pixel 1 by specifying (x, y)
04 can be specified.

The source line 102 is a sample hold circuit 1
05 to the source driver circuit 124,
The gate line 103 is connected to the output of the gate driver circuit 123. Further, a clock line 106 and a start line 107 are connected to the input of the gate driver circuit 123, a video line 108 is connected to the input of the sample hold circuit 105, and a clock line 109 and a start line 110 are connected to the source driver circuit 124. Are connected respectively. The gate driver circuit 123 and the source driver circuit 124 are each formed of a P-type, N-type, or complementary thin film transistor.

Further, a circuit for designating the address of the pixel 104 to be masked is provided, and the output of the reference clock generation circuit 125 for generating the reference clock by the reference clock line 126 counts the X coordinate. It is connected to an X-axis counter circuit 111, a Y-axis counter circuit 112 for counting Y coordinates, and a storage device control circuit 113 for generating a clock signal for controlling reading / writing to an external storage device. The outputs of the X-axis counter circuit 111 and the Y-axis counter circuit 112 are the coordinate conversion circuit 11 to which the address holding circuit 116 is connected.
5, the address buffer 118, and the address bus 119 are sequentially connected and output to an external control unit. Further, the output of the storage device control circuit 113 is connected to the control unit outside the active matrix panel 101 by the averaging start signal line 128 via the clock buffer 127. The X-axis counter circuit 111, the Y-axis counter circuit 112, the storage device control circuit 113, the coordinate conversion circuit 115, and the address holding circuit 116 are respectively P-type.
, N-type, or complementary thin film transistors.

Further, a data operation circuit 114 is provided for performing image processing, and the data operation circuit 114 has a readable / writable input / output control circuit 117,
The input / output switching signal line 120, the bidirectional buffer 121, and the data bus 122 are sequentially connected so that they can be input / output. The data bus 122 is connected to the active matrix panel 101.
It is connected to an external control unit. Here, the data arithmetic circuit 114 and the input / output control circuit 117 are P type and N type, respectively.
Type or complementary type thin film transistor.

FIG. 2 is a block circuit diagram of an image processing system for a liquid crystal display device. A storage device 201 for storing image data and an MPU 202 for controlling the entire device are provided outside the active matrix panel 101. Is provided. The output of the active matrix panel 101 and the output of the MPU 202 are connected to the storage device 201 by the address bus 119. In addition, the active matrix panel 10 is connected by the data bus 122.
1 bidirectional buffer 121, storage device 201, MPU 2
02 are connected so that they can be input and output. Further, a DA converter 203 is connected to the data bus 122,
The converter 203 is connected to the active matrix panel 101 by the video signal line 108. Further, the storage device control line 204 connects the active matrix panel 101 to the storage device 201 and MPU 202, respectively. Further, the active matrix panel 101 and the MPU 20 are connected by the control signal line 205.
2 and are connected.

3 and 4 show a configuration example of the bidirectional buffer 121. In FIG. 3, the output pin 301 has a drain electrode of the P-type transistor 302 and an N-type transistor 3 at the output pin 301.
03 is connected to the source electrode of the N-type transistor 303, the gate electrode of the P-type transistor 302 is connected to the NAND circuit 304, and the gate electrode of the N-type transistor 303 is NOR.
The circuit 305 is connected. The input pin 309 is connected to one of the input ends of the NAND circuit 304, and the other end is I.
The NVERT circuit 306 is connected. Also, NOR
The input pin 309 is connected to one of the input ends of the circuit 305, and the INVERT circuit 307 is connected to the other. The output of the INVERT circuit 307 is INVER.
The output state control pin 308 is also connected to the IN circuit 307.

Further, in FIG. 4, the bidirectional pin 401 is connected to the output end of the tri-state buffer 402 and the input end of the input buffer 403, respectively. The inputs of the input pin 404 and the input / output switching pin 405 are connected to the tri-state buffer 402, respectively, and the input buffer 4
03 is connected to the output of the input pin 406.

In the mask processing, when the signal from the averaging start signal line 128 becomes H level, the X-axis counter circuit 111 and the Y-axis are synchronized with the clock signal generated by the reference clock generation circuit 125. Counter circuit 112
And the (x, y) coordinates are from (2, 2) to (3,
2), (3, 3). ． ． Are sequentially counted.

When the signal on the averaging start signal line 128 becomes L level, the X-axis counter circuit 111 and the Y-axis counter circuit 112 stop counting the coordinates, and the coordinates (x, y) are determined. In the coordinate conversion circuit 115, coordinates (x, y)
The address A (x, y) of the pixel 104 is determined based on the above, and the image data D (x, y) of the pixel 104 of this address A (x, y) is masked.

FIG. 5 shows a step diagram of the mask processing algorithm. The address A (x, y) determined by the coordinate conversion circuit 115 is temporarily stored in the address holding circuit 116 and is also output to the storage device 201 by the address buffer 118 and the address bus 119. The storage device 201 reads the image data D (x, y) from the MPU 202 and outputs it to the data operation circuit 114. Note that density data is used as the image data.

Then, as shown in FIG.
Addresses A (x- of eight pixels 104 around (x, y)
1, y-1), A (x, y-1), A (x + 1, y-1), A (x-1,
y), A (x + 1, y), A (x-1, y + 1), A (x, y + 1),
A (x + 1, y + 1) is generated, and the image data D corresponding to these nine addresses A (x, y) is generated from the storage device 201.
(X, y), D (x-1, y-1), D (x, y-1), D (x + 1, y
-1), D (x-1, y), D (x + 1, y), D (x-1, y + 1
), D (x, y + 1), and D (x + 1, y + 1) are sequentially read and output to the data operation circuit 114. In the data operation circuit 114, the above-mentioned image data D (x, y) are sequentially added, the operation result is divided by 9 which is the total number of the image data D, and the address A (x, y) is averaged. The obtained image data D ′ (x, y) is obtained.

From the storage device control circuit 113 to the storage device 20
When a write signal is input to 1, the address buffer 1
18, the address A (x, y) is input from the address holding circuit 116 to the storage device 201 via the address bus 119, and is stored therein. At the same time, the data bus 122
After that, the averaged image data D ′ (x, y) is input from the data calculation circuit 114 to the storage device 201 and stored therein. As shown in FIG. 7, the above processing is performed on the address A.
The pixel processing of (2, 2) to (N-1, M-1) is performed, and the masking process is performed on the entire screen.

In order to execute the algorithm shown in FIG. 5, the storage device control circuit 113 is set to the read state and the input / output control circuit 117 causes the data bus buffer 1 to operate.
The input / output of the bidirectional buffer 121 of 22 may be switched.

In this algorithm, the image data D (x, y) is simply averaged, but the image data D (x, y) may be weighted. FIG. 8 shows a step diagram of an algorithm for weighting the image data D (x, y) in order to emphasize the averaged image data D ′ (x, y).

The address A (x, y) determined by the coordinate conversion circuit 115 is output to the address holding circuit 116 and temporarily stored, and at the same time, the address buffer 11 is stored.
8, output to the storage device 201 via the address bus 119. The storage device 201 stores the image data D from the MPU 202.
(X, y) is read out and output to the data operation circuit 114. In the data calculation circuit 114, the image data D
Image data D weighted by multiplying (x, y) by 8
Get (x, y). 8 Image data D to be added later
It is the total number of (x, y).

Then, as shown in FIG.
Addresses A (x- of eight pixels 104 around (x, y)
1, y-1), A (x, y-1), A (x + 1, y-1), A (x-1,
y), A (x + 1, y), A (x-1, y + 1), A (x, y + 1),
A (x + 1, y + 1) is generated, and the image data D corresponding to these nine addresses A (x, y) is generated from the storage device 201.
(X, y), D (x-1, y-1), D (x, y-1), D (x + 1, y
-1), D (x-1, y), D (x + 1, y), D (x-1, y + 1
), D (x, y + 1), and D (x + 1, y + 1) are sequentially read and output to the data calculation circuit 114 to weight the image data D (x, y). Are sequentially added to. This calculation result is divided by 16 to obtain the averaged image data D ′ (x, y) of the address A (x, y).

[Second Embodiment] In the first embodiment, there is only one storage device outside the active matrix panel 101. In this case, since the original image data is overwritten, the effect of the mask processing cannot be confirmed, which is inconvenient.

In the second embodiment, two storage devices are provided outside the active matrix panel 101 to store both the image data before the mask processing and the image data after the mask processing.

FIG. 9 shows a block diagram of the image processing system of the second embodiment. The structure of the active matrix panel is the same as that of the first embodiment shown in FIG. 1, and the same symbols as those in FIGS. 1 and 2 indicate the same members. Outside the active matrix panel 101, two storage devices A501 and B502 for storing image data and an MPU 503 for controlling the entire device are provided. The outputs of the active matrix panel 101 and MPU 503 are connected to the storage device A 501 and the storage device B 502 by the address bus 119. In addition, the data bus 12
2, the active matrix panel 101, the storage device A 501, the storage device B 502, and the MPU 503 are connected so that input / output is possible. Further, the DA converter 504 is connected to the data bus 122, and the DA converter 504 is connected by the video signal line 108. It is connected to the active matrix panel 101. Further, by the storage device control line 505,
Active matrix panel 101, storage device A50
1, the storage device B502, and the MPU 503 are connected to each other. Further, the active matrix panel 101 and the MPU 503 are connected by the control signal line 506.

When the mask processing is performed, the algorithm of the first embodiment shown in FIG. 5 or 8 is used, and the storage device A50 is used.
1 is subjected to mask processing, and the masked image data is stored in the storage device B502.
To memorize.

[Third Embodiment] In the first and second embodiments, an example in which the mask processing is performed on the entire display screen is shown. In the third embodiment, the processing time is further shortened by not performing processing on image data that does not require masking.

FIG. 11 shows a block diagram of the active matrix panel of this embodiment. The same reference numerals as those in FIG. 1 indicate the same members, and only the circuit for designating the address of the pixel is modified.

Mask processing start / end signal line 6 in the X-axis direction
01, Y-axis direction mask processing start / end signal line 602,
The output of the mask processing start signal line 603 is the subtraction circuit 60.
4 is connected. The output of the subtraction circuit 604 is connected to the X-axis counter circuit 111, the Y-axis counter circuit 112, and the coordinate conversion circuit 115. The subtraction circuit 604 and the coordinate value generation circuit 605 are each composed of a P-type, N-type or complementary type thin film transistor. Here, the pixel configuration of the active matrix panel is N × M pixels of X-axis direction pixels and Y-axis direction pixels, as in the first embodiment. Also, the following i, j, k, l are 1 <i, k <N,
1 <j and l <M are satisfied.

When performing the mask processing, the subtraction circuit 604
, A masking process start signal is input from the masking process start signal line 603, and the start coordinates for performing the masking process from the X-axis masking process start / end signal line 601 and the Y-axis direction masking process start / end signal line 602 (I, j)
And the end coordinates (k, l) are input. In the subtraction circuit 604, the X-axis counter end value (p = k−1 + 1) and Y
The axis counter end value (q = 1-j + 1) and are calculated,
The count value of the X-axis counter circuit 111 is controlled to be reset with the p value, and the count value of the Y-axis counter circuit 112 is controlled to be reset with the q value. Therefore, the X-axis counter circuit 111 is a p-adic counter circuit and the Y-axis counter circuit 112 is a q-adic counter circuit.

The coordinate value generation circuit 605 calculates (i + X-axis counter value, j + Y-axis counter value) and generates an address A (x, y) in the masking range. Pixel 1 at each of those generated addresses A (x, y)
By executing the algorithm of the first embodiment on 04, the mask processing is performed only on the pixels 104 in the range shown in FIG.

In order to store both the image data before the masking process and the masked data,
Two or more storage devices may be provided as in the configuration of the second embodiment.

[0039]

According to the present invention, a circuit having a logical function such as data processing is formed on the same substrate by thin film transistors in the active matrix panel, so that the MPU outside the active matrix panel is not burdened. Image processing such as noise removal can be performed at high speed. In addition, downsizing of the device can be realized.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an active matrix panel according to a first embodiment.

FIG. 2 is a block circuit diagram of an image processing system of a liquid crystal display device.

FIG. 3 is a circuit diagram of a bidirectional buffer.

FIG. 4 is another circuit diagram of the bidirectional buffer.

FIG. 5 is a step diagram of a mask processing algorithm.

FIG. 6 is an explanatory diagram of correspondence between pixel addresses and image data.

FIG. 7 is an explanatory diagram of a range where a mask process is performed.

FIG. 8 is a step diagram of another mask processing algorithm.

FIG. 9 is a block diagram of an image processing system according to a second embodiment.

FIG. 10 is an explanatory diagram in which a mask process is performed on a part of the display screen.

FIG. 11 is a configuration diagram of an active matrix panel of Example 3.

FIG. 12 is a configuration diagram of a liquid crystal display device of a conventional example.

FIG. 13 is a system block diagram of image data processing of a conventional example.

[Explanation of symbols]

 101 ... Active matrix panel 102 ... Source line 103 ... Gate line 104 ... Pixel 105 ... Sample and hold circuit 106 ... Gate line clock line 107 ... Gate line start signal line 108 ... Video signal line 109 ... Source line clock line 110 ... Source line start signal line 111 ... X-axis counter circuit 112 ... Y-axis counter circuit 113 ... Read / write control circuit 114 ... Data operation circuit 115 ... XY coordinate conversion circuit 116 ... Address holding circuit 117 ... Input / output control circuit 118 ... Address Buffer 119 ... Address bus 120 ... Input / output switching signal line 121 ... Bidirectional buffer 122 ... Data Gate driver circuit 124 Source driver circuit 125 Reference clock generation circuit 126 Reference clock line 127 Clock buffer 128 Averaging start signal Line 201 ... Storage device 202 ... MPU 203 ... DA conversion circuit 204 ... Storage device control line 501 ... Storage device A 502 ... Storage device B 503 ... ·· MPU 504 ··· DA conversion circuit 505 · · · storage device control line 601 · · X-axis direction mask processing start / end signal line 601 ··· Y-axis direction mask processing start / end Signal line 603 ... Masking start signal line 604 ... Subtraction circuit 605 ... Coordinate value generation circuit

Claims (8)

[Claims] 1. A first transparent substrate having a plurality of gate lines, a plurality of source lines, pixels connected to thin film transistors and arranged in a matrix, and a first transparent substrate arranged to face the first transparent substrate. A gate line driver circuit or a source line including a second transparent substrate, a liquid crystal interposed between the first transparent substrate and the second transparent substrate, and a P-type, N-type, or complementary type thin film transistor. An active matrix panel having at least one circuit of a driver circuit, comprising a processing circuit configured of P-type, N-type, or complementary type thin film transistors and processing image data supplied to the source line. Active matrix panel. 2. A first transparent substrate having a plurality of gate lines, a plurality of source lines, pixels to which thin film transistors are connected and arranged in a matrix, and a first transparent substrate which is arranged so as to face the first transparent substrate. A gate line driver circuit or a source line including a second transparent substrate, a liquid crystal interposed between the first transparent substrate and the second transparent substrate, and a P-type, N-type, or complementary type thin film transistor. An active matrix panel having at least one circuit of a driver circuit, comprising a P-type or N-type or complementary type thin film transistor, and having a processing circuit for processing image data supplied to the source line. , A P-type or N-type or complementary type thin film transistor is provided as a reference clock generating circuit. Matrix panel. 3. A first transparent substrate having a plurality of gate lines, a plurality of source lines, pixels connected to thin film transistors, and arranged in a matrix, and a first transparent substrate arranged to face the first transparent substrate. A gate line driver circuit or a source line including a second transparent substrate, a liquid crystal interposed between the first transparent substrate and the second transparent substrate, and a P-type, N-type, or complementary type thin film transistor. An active matrix panel having at least one circuit of a driver circuit, comprising a P-type or N-type or complementary type thin film transistor, and having a processing circuit for processing image data supplied to the source line. , A counter circuit composed of P-type or N-type or complementary thin film transistors. Cos panel. 4. A first transparent substrate having a plurality of gate lines, a plurality of source lines, pixels connected to thin film transistors, and arranged in a matrix; and a first transparent substrate arranged to face the first transparent substrate. A gate line driver circuit or a source line including a second transparent substrate, a liquid crystal interposed between the first transparent substrate and the second transparent substrate, and a P-type, N-type, or complementary type thin film transistor. An active matrix panel having at least one circuit of a driver circuit, comprising a P-type or N-type or complementary type thin film transistor, and having a processing circuit for processing image data supplied to the source line. , A P-type or N-type or complementary type thin film transistor having a frequency dividing circuit, panel. 5. A first transparent substrate having a plurality of gate lines, a plurality of source lines, and pixels arranged in a matrix, to which thin film transistors are connected, and a first transparent substrate arranged opposite to the first transparent substrate. A gate line driver circuit or a source line including a second transparent substrate, a liquid crystal interposed between the first transparent substrate and the second transparent substrate, and a P-type, N-type, or complementary type thin film transistor. An active matrix panel having at least one circuit of a driver circuit, comprising a P-type or N-type or complementary type thin film transistor, and having a processing circuit for processing image data supplied to the source line. , P-type or N-type or complementary type thin film transistors, and transmits signals from the outside to the active matrix panel. Active matrix panel, wherein, to have a reach circuit. 6. A first transparent substrate having a plurality of gate lines, a plurality of source lines, pixels connected to thin film transistors, and arranged in a matrix, and a first transparent substrate arranged to face the first transparent substrate. A gate line driver circuit or a source line including a second transparent substrate, a liquid crystal interposed between the first transparent substrate and the second transparent substrate, and a P-type, N-type, or complementary type thin film transistor. An active matrix panel having at least one circuit of a driver circuit, comprising a P-type or N-type or complementary type thin film transistor, and having a processing circuit for processing image data supplied to the source line. , P-type or N-type or complementary type thin film transistors, and transmits signals from the active matrix panel to the outside. Active matrix panel, wherein, to have a reach circuit. 7. A first transparent substrate having a plurality of gate lines, a plurality of source lines, and pixels to which thin film transistors are connected and arranged in a matrix; and a first transparent substrate which is arranged to face the first transparent substrate. A gate line driver circuit or a source line including a second transparent substrate, a liquid crystal interposed between the first transparent substrate and the second transparent substrate, and a P-type, N-type, or complementary type thin film transistor. An active matrix panel having at least one circuit of a driver circuit, comprising a P-type or N-type or complementary type thin film transistor, and having a processing circuit for processing image data supplied to the source line. , P-type or N-type or complementary type thin film transistors, and is connected from the active matrix panel to the outside and from the outside. Active matrix panel, wherein, to have a bidirectional transmission circuit for transmitting a signal to Restorative inner matrix panel. 8. A first transparent substrate having a plurality of gate lines, a plurality of source lines, and pixels arranged in a matrix, to which thin film transistors are connected, and a first transparent substrate arranged to face the first transparent substrate. A gate line driver circuit or a source line including a second transparent substrate, a liquid crystal interposed between the first transparent substrate and the second transparent substrate, and a P-type, N-type, or complementary type thin film transistor. An active matrix panel having at least one circuit of a driver circuit, comprising a P-type or N-type or complementary type thin film transistor, and having a processing circuit for processing image data supplied to the source line. An active maritrix panel having at least two circuits of the following circuits (1) to (6). (1) Reference clock generating circuit composed of P-type, N-type or complementary thin-film transistors (2) Counter circuit composed of P-type, N-type or complementary thin-film transistors (3) From P-type, N-type or complementary thin-film transistors (4) Transmission circuit for transmitting signals from the outside to the active matrix panel (5) P-type, N-type, or complementary thin-film transistor, active matrix Transmission circuit for transmitting signal from panel to outside (6) Bidirectional transmission circuit composed of P-type, N-type or complementary type thin film transistors and transmitting signal from active matrix panel to outside and from outside to inside of active matrix panel