JPH08212785A - Memory circuit - Google Patents

Abstract

PURPOSE: To input two kinds of address signals during one cycle time of a clock signal and to output the content of a designated address as a memory output signal in a memory circuit for a semiconductor integrated circuit. CONSTITUTION: A decoder circuit 12 which is constituted of a decoder part 13, a two-input multiplexer 10 and a control signal generation circuit, selects one out of two kinds of address signals which have been input. Then, the decoder circuit 12 decodes a word signal and a select signal. The content of an address which is selected by the word signal and the select signal is latched by a control signal from the decoder circuit 12 so as to be output as a memory output signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory circuit, and more particularly to a decoder circuit composed of a semiconductor integrated circuit.

[0002]

2. Description of the Related Art A memory circuit in a conventional semiconductor integrated circuit can be described with reference to the block diagram of FIG. 4 and the operation waveform diagram of FIG.

As shown in FIG. 4, the conventional memory circuit has an output signal (address signal 41) AD0-A of the control circuit 42.
A decoder circuit 40 that receives Dx, a memory cell array circuit 45 that receives the output signals DE0 to DEx of the decoder circuit 40, an output signal of the memory cell array circuit 45, and output signals Y0 to Y3 of the decoder circuit 40 are input. Selector circuit 44 that operates and a D-type flip-flop (DF that receives the output signals S0 to Sn of the selector circuit 44)
F) It is composed of circuits 47 and 48.

Here, the memory cell array circuit 45 has a large number of memory cells 46, and each memory cell 46 has N-channel transfer gates T13, T14, T15, ...
Have. The selector circuit 44 has N-channel transfer gates T16 to T19, ..., P-channel transfer gate TP3 and an inverter IN13.
The DFF circuits 47 and 48 output the memory output signals (0 to n) 4
3 is output.

Next, regarding the operation of the block diagram of FIG.
This will be described with reference to the operation waveform diagram of FIG. At the point A in FIG. 5, when the clock signal φ rises from the “L” level to the “H” level, the control circuit 43 causes the address signal AD0.
To ADx at the timing of
Input signal. The decoder circuit 40 uses the address signal A
The memory cell array circuit 45 is decoded by decoding D0 to ADx.
Of the word signals DE0 to DEx and the input signals Y0 to Y3 of the selector circuit 44 are output at the timings.

After that, the memory data selected by the memory cell array circuit 45 and the selector circuit 44 is output to the output signals S0 to Sn of the selector circuit 44 at the timing, and the clock signal φ (inverted value) is "H" at the point B. When rising to the level, the DFF circuits 47 and 48 latch at the timing of and output the memory output signals M0 to Mn to the control circuit 42.

[0007]

In recent years, semiconductor integrated circuits have become multi-functional, multi-pin, high-speed, and high-density.

In the conventional memory circuit of the semiconductor integrated circuit described above, of the cycle time t ₀ of the clock signal φ shown in FIG. 5, the time to actually access the memory circuit is the time t ₁ from the point A to the point B. is only, time of the t ₀ -t ₁ = t _2, there has been a drawback that wasted time, such as sported a circuit occurs.

Further, when two or more storage circuits are present in one chip, a decoder circuit 40, a memory cell array circuit 45, and a selector circuit 44 are used for each storage circuit, so that a large area is formed in the semiconductor chip. There are drawbacks that need it.

It is an object of the present invention to provide a memory circuit which solves the above-mentioned drawbacks, prevents the cycle time from being wasted, and can be configured with a small semiconductor chip.

[0011]

The structure of a memory circuit of a semiconductor integrated circuit according to the present invention comprises a multiplexer circuit which outputs two kinds of address signals as direct inputs and outputs one of the address signals, and a clock signal as an input. A control signal generating circuit for generating a control signal to the input multiplexer circuit and the flip-flop circuit; a decoder section for receiving the address signal output from the input multiplexer circuit and outputting a word signal and a select signal; and the word signal. A memory cell array circuit having memory cells each of which has two MOS transistors as common inputs, first and second selector circuits that select the output of the memory cell array circuit according to the output of the decoder circuit, and the first or second Input the output signal of the selector circuit of A latch on the control signal output, characterized in that it comprises the flip-flop circuit for outputting a memory output signal.

[0012]

1 is a circuit diagram showing a first portion of a memory circuit according to an embodiment of the present invention, and FIG. 2 is a circuit diagram showing a second portion of FIG. 1 and 2 are combined to form the entire circuit of one embodiment of the present invention. Here, A to L in FIG. 1 are connected to the same alphabet in FIG. 2, respectively.

The memory circuit in the semiconductor integrated circuit of the embodiment shown in FIGS. 1 and 2 has two types of address signals A0 to Ax, B.
2-input multiplexer circuit 1 which directly inputs 0 to Bx
0, the 2-input multiplexer circuit 10 and the DFF circuit 1
The decoder circuit 12 having the control signal generation circuit 11 for controlling the DFF circuit 2 and the decoder section 13 and the outputs D0 to Dx of the decoder circuit 12 are used as word signals, and the memory cell 1
5, a memory cell array circuit 14 having two MOS transistors each serving as a common input, an output of the memory cell array circuit 14 and an output of the decoder circuit 12 YA0 to YA
3, YB0 to YB3 each have two selector circuits 16 and a selector circuit 17, and two DFF circuits 1 and 2 for latching the outputs of the respective selector circuits 16 and 17; a control circuit 18; Memory output signal bus out 1 (n to 0) 3 and bus out 2 (m to
0) 4 and.

Here, the control signal generating circuit 11 is supplied with the clock signal φ and receives the delay clock signal (φdela).
y) and the delay circuit 5 and inverters IN7-
It has IN12 and NAND gates NA1 to NA4. Each of the DFF circuits 1 and 2 is composed of a D-type flip-flop group. The 2-input multiplexer circuit 10 has inverters IN3 to IN6 and complementary transfer gates Tr1 and Tr2.

The selector circuit 16 has an inverter IN1.
, N-channel transfer gates T1 to T4, and P
A channel transfer gate TP1. The memory cell array circuit 14 has a large number of memory cells 15, and each memory cell 15 has N-channel transfer gates T5 to T8. The selector circuit 17 has N-channel transfer gates T9 to T12 and a P-channel transfer gate TP2.

Next, FIG. 3, which is the operation waveform of FIGS. 1 and 2, will be described. At point a in FIG. 3, the clock signal φ
But when it rises from "L" level to "H" level,
From the control circuit 18, the two types of address signals A0 to Ax and B0 to Bx are input to the transistors Tr1 and Tr2 of the two multiplexer circuit 10.

At the same time, the control signal generating circuit receives the "H" level of the clock signal φ and receives the 2-input NAND gate N.
When A1 outputs the “L” level and the output signal φA of the control signal generation circuit 11 rises from the “L” level to the “H” level via the inverter IN7, the transistor Tr1 is turned on and the transistor Tr1 is turned on. Tr2 is OF
In the F state, the address signals A0 to Ax are selected,
Output signals DI0 to DIx are output from the 2-input multiplexer circuit 10 at the timing. Further, the output signals DI0 to DIx are input to the decoder unit 13,
The decoded select signals YA0 to YA3 and the word signals D0 to Dx are output at the timing. Then, the content of the address selected by the word signals D0 to Dx is input to the selector circuit 16 as a bit signal,
Further, the selection signals YA0 to YA3 are selected, and the output signals SA0 to SAn are output at the timings.

Next, at point b in FIG. 3, the clock signal φ
When the delayed signal φdelay changes from "L" level to "H" level, the NAND gate NA4 is set to "L".
The level is output, the “H” level is output to the output signal φB of the control signal generation circuit 11 via the inverter IN10, the data of the output signals SA0 to SAn is latched in the DFF circuit 1, and the memory output is performed at the timing of Output to signal bus out (BUSOUT) 1 (n to 0).

After that, at the point c in FIG. 3, when the clock signal φ falls from the "H" level to the "L" level, the output of the inverter IN12 becomes the "H" level,
NAND gate NA2 outputs "L" level and changes output signal φC of control signal generating circuit 11 from "L" level to "H" level via inverter IN8.

At this time, the transistor Tr1 is turned off, the transistor Tr2 is turned on, the address signals B0 to Bx are selected, and the output signals DI0 to DI0 are output from the 2-input multiplexer circuit 10 at the timing.
DIx is output.

Further, the output signals DI0 to DIx are input to the decoding section 13 and decoded by the select signal Y.
B0 to YB3 and word signals D0 to Dx are output at the timings. Then, the contents of the address selected by the word signals D0 to Dx are expressed as bit signals.
It is input to the selector circuit 17 and further selected signal YB
The output signals SB0 to SBm are output at timings selected by 0 to YB3.

Next, at point d in FIG. 3, the signal φdelay obtained by delaying the clock signal φ is changed from the “H” level to
When it goes to "L" level, the inverter IN11 goes to "H" level, the NAND gate NA3 outputs "L" level, and the control signal generation circuit 1 goes through the inverter IN9.
The output signal φD of 1 outputs "H" level, and the output signal S
The data of B0 to SBm is latched in the DFF circuit 2, and at the timing of, the memory output signal bus out (BUSOU
T) Output to 1 (m to 0).

In FIG. 3, the operation signals of the respective parts of FIGS. 1 and 2 are shown, and the point between points a and b is the delay T _D by the delay circuit.

The memory circuit of the semiconductor integrated circuit of this embodiment is
A two-input multiplexer circuit that directly inputs two kinds of address signals and outputs one of the address signals, and a control signal generation circuit that inputs a clock signal and generates control signals to the two-input multiplexer circuit and the DFF circuit. A decoder unit which receives the address signal output from the 2-input multiplexer circuit and outputs the word signal of the memory cell array circuit and the select signal of the selector circuit;
A memory cell array circuit having two MOS transistors each commonly inputting a word signal into the memory cell;
The selector circuit 1 and the selector circuit 2 for selecting the memory cell array circuit output by the output of the decoder circuit, and the output signal of the selector circuit 1 or the selector circuit 2 are input and latched by the control signal output from the control signal generation circuit, A DFF circuit for outputting a memory output signal is provided, and the two-input multiplexer circuit, the control signal generating circuit, and the decoder section constitute a decoder circuit.

[0025]

As described above, according to the present invention, it becomes possible to obtain memory circuit data suitable for two kinds of address signals, particularly within the cycle time t ₀ of the clock signal φ.
In a highly functional and high speed semiconductor integrated circuit, it has an effect of improving the processing speed, and also has an effect of sharing the decoder circuit when there are two or more memory circuits in one chip.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first portion of a memory circuit according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a second portion of FIG.

FIG. 3 is a waveform diagram showing the operation of each part of FIGS.

FIG. 4 is a circuit diagram showing a conventional memory circuit.

5 is a waveform diagram showing the operation of each part of FIG.

[Explanation of symbols]

IN1-IN13 Inverters NA1-NA4 NAND gates Tr1-Tr2 Complementary transfer gates T1-T19 N-channel transfer gates TP1-TP3 P-channel transfer gates DFF D-type flip-flop circuits A0-Ax, B0-Bx, AD0-ADx address signals DI0 ~ DIx Output signal of 2-input multiplexer circuit YA0-YA3, YB0-YB3 Select signal D0-Dx, DE0-DEx word signal SA0-SAn Output signal of first selector circuit SB0-SBm Output signal bus of second selector circuit out (BUSOUT) memory output signal phi, phi (inverted value) clock signals φA, φB, φC, φD control signal t ₀ 1 cycle time t ₁ clock signal of the clock signal is "H" level of the time t ₂ clock signal Is at "L" level a, c, e, A, C Change point of clock signal b, d Change point of φ delay (delay) ,,,,, Timing of change of operation waveform B Clock signal Changing point

Claims (1)

[Claims] 1. A multiplexer circuit for directly inputting two kinds of address signals and outputting one of the address signals, and a control signal for inputting a clock signal to generate control signals for the input multiplexer circuit and the flip-flop circuit. A memory having a generating circuit, a decoder section for receiving an address signal output from the input multiplexer circuit and outputting a word signal and a select signal, and a memory cell including two MOS transistors each having the word signal as a common input. A cell array circuit, first and second selector circuits that select the output of the memory cell array circuit by the output of the decoder circuit, and output signals of the first or second selector circuit are input and output from the control signal generation circuit. Before outputting the memory output signal by latching with the control signal A storage circuit having a flip-flop circuit.