JPH08220191A - Semiconductor device - Google Patents

Abstract

(57) [Summary] [Object] An object of the present invention is to provide a semiconductor device having a bonding option function, which can perform a reliable operation test in a short time. [Structure] The pad P connected to the internal circuit 1 has a high resistance R
When the pad P is maintained in a floating state, the potential of the pad P is
Maintained at the level. A switch circuit SW that is closed when the potential difference between the potential of the pad P and the power source Vs is within a predetermined value is connected between the pad P and the power source Vs.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which the operation of an internal circuit can be switched by a bonding option for selecting a connection of a bonding wire to a pad provided on a chip.

In recent semiconductor devices, due to the demand for multi-functionality in the market, internal circuits in the same chip have various functions, and a large number of pads provided on the chip are packaged during packaging of the chip. There is one in which a semiconductor device having a desired function can be configured by selecting the connection of the bonding wire with respect to. In such a semiconductor device, a probe of a test device is brought into contact with a large number of pads before a chip is packaged, and a primary test for checking the operating state of an internal circuit is performed. Then, it is necessary to perform such a primary test accurately and quickly.

[0003]

2. Description of the Related Art In a semiconductor device having a bonding option function, a pad P1 is connected to an input terminal of an internal circuit 1 and a drain of a P channel MOS transistor Tr1 as shown in FIG.

The source of the transistor Tr1 is a power source Vcc.
And the gate is connected to the ground GND. The transistor Tr1 is constantly turned on in the high resistance state based on the supply of the power source Vcc.

With such a structure, if the bonding wire is not connected to the pad P1, the pad P1 will be in a floating state, and the operation of the transistor Tr1 which is turned on based on the supply of the power supply Vcc causes the internal portion corresponding to the pad P1 to be operated. The H level is input to the input terminal of the circuit 1.

If the pad P1 is connected to an external pin via a bonding wire and an L level signal is input from the external circuit to the external pin, the L level signal is input to the input terminal of the internal circuit 1 corresponding to the pad P1. A signal can be input.

In this way, by selecting whether or not the bonding wire is connected to the pad P1, the input terminal potential of the internal circuit 1 corresponding to the pad P1 can be switched, and this input terminal potential can be switched. Due to
The function of the internal circuit 1 can be switched.

In the structure shown in FIG. 8, the pad P2 is connected to the input terminal of the internal circuit 1 and the drain of the N-channel MOS transistor Tr2. The source of the transistor Tr2 is connected to the ground GND, and the gate is connected to the power supply Vcc. The transistor Tr2 is always turned on in the high resistance state based on the supply of the power source Vcc.

With such a structure, if a bonding wire is not connected to the pad P2, the pad P2 will be in a floating state, and the operation of the transistor Tr2 which is turned on based on the supply of the power source Vcc will cause the internal portion corresponding to the pad P2 to be operated. The L level is input to the input terminal of the circuit 1.

If the pad P2 is connected to an external pin via a bonding wire and an H level signal is input from the external circuit to the external pin, the H level signal is input to the input terminal of the internal circuit 1 corresponding to the pad P2. A signal can be input.

In this way, by selecting whether or not the bonding wire is connected to the pad P2, the input terminal potential of the internal circuit 1 corresponding to the pad P2 can be switched, and this input terminal potential can be switched. Due to
The function of the internal circuit 1 can be switched.

In such a semiconductor device, a primary test for checking the operation of the internal circuit 1 is performed prior to packaging. In this primary test, a large number of pads provided on the outer peripheral portion of the chip are simultaneously brought into contact with the probe by the probe card and are connected to the test apparatus via the probe. Then, a predetermined test signal is input from the test device and an operation test is performed.

At this time, the probe in contact with the pad packaged in the floating state is kept in the floating state, and the pad to which the bonding wire is connected and the predetermined signal is inputted is connected to the pad from the test apparatus through the probe. A signal is input.

[0014]

In the primary test of the semiconductor device as described above, the floating probe 2 is brought into contact with the pad P1 shown in FIG.
Is supplied, the load capacitance of the probe 2 becomes higher than the current supply capability of the transistor Tr1. Therefore, as shown in FIG. 7, the rise of the potential V1 of the pad P1 slows down to the H level. It takes time.

Therefore, in the primary test when the pad P1 is used at the floating level, the potential V1 of the pad P1 cannot be fixed to the H level in a short time.
As a result, if the operation test is started without fixing the potential V1 of the pad P1, the chip is erroneously determined to be a defective chip.

Further, if the operation test is started after the potential V1 of the pad P1 is fixed, there is a problem that the test time becomes long. In the pad P2 shown in FIG. 8, when the operation mode is switched, the probe 2 which has been inputting the signal of H level until then is set in the floating state, and when the power supply Vcc is supplied, the probe P2 is compared with the current supply capability of the transistor Tr2. Since the load capacitance of No. 2 becomes a high load, the decrease in the potential V2 of the pad P2 becomes gentle as shown in FIG. 9, and it takes time to reach the L level.

Therefore, when the potential V2 of the pad P2 is switched from the H level to the floating level to perform the primary test, the potential V2 of the pad P2 cannot be fixed to the L level in a short time. As a result, if the operation test is started without fixing the potential V2 of the pad P2, the chip is erroneously determined as a defective chip.

Further, if the operation test is started after the potential V2 of the pad P2 is fixed, there is a problem that the test time becomes long. An object of the present invention is to provide a semiconductor device having a bonding option function, which can perform a reliable operation test in a short time.

[0019]

FIG. 1 is a diagram for explaining the principle of the invention of claim 1. That is, the pad P connected to the internal circuit 1 is connected to the power supply Vs via the high resistance R, and when the pad P is maintained in the floating state, the potential of the pad P is maintained at the power supply Vs level. A switch circuit SW that is closed when the potential difference between the pad P and the power supply Vs is within a predetermined value is connected between the pad P and the power supply Vs.

According to a second aspect of the present invention, as shown in FIG. 2, the switch circuit includes a P-channel MOS transistor Tr3 connected between the pad P1 and the high potential side power source Vcc.
An input terminal is connected to the pad P1 and an output terminal is connected to an inverter circuit 2a connected to the gate of the P-channel MOS transistor Tr3.

According to a third aspect of the present invention, as shown in FIG. 4, the switch circuit includes an N-channel MOS transistor Tr4 connected between the pad P2 and the low potential side power supply GND.
And an inverter circuit 2b having an input terminal connected to the pad P2 and an output terminal connected to the gate of the N-channel MOS transistor Tr4.

[0022]

According to the present invention, a current flows through the high resistance R,
When the potential of the pad P changes toward the power source Vs and the potential difference between the potential of the pad P and the power source Vs becomes within a predetermined value, the switch circuit SW is closed and the pad P is closed.
The potential of is rapidly raised to the power supply Vs level.

According to a second aspect of the present invention, when a current flows through the high resistance and the potential of the pad P1 changes toward the high potential side power source Vcc, the potential difference between the potential of the pad P1 and the power source Vcc is within a predetermined value. Then, the output signal of the inverter circuit 2a becomes L level, the P-channel MOS transistor Tr3 is turned on, and the potential of the pad P1 is rapidly raised to the potential of the high potential side power source Vcc.

In the third aspect, when a current flows through the high resistance and the potential of the pad P2 changes toward the low potential side power supply GND, the potential difference between the potential of the pad P2 and the low potential side power supply GND is When it is within the predetermined value, the output signal of the inverter circuit 2b becomes H level, and the N channel MO
The S transistor Tr4 is turned on, and the potential of the pad P2 is rapidly lowered to the potential of the low-potential-side power supply GND.

[0025]

FIG. 2 shows a first embodiment embodying the present invention. The same components as those of the conventional example will be described with the same reference numerals.

The pad P1 is connected to the input terminal of the internal circuit 1 and also to the drain of the P-channel MOS transistor Tr1. The source of the transistor Tr1 is connected to the power supply Vcc, and the gate is connected to the ground GND. The transistor Tr1 is constantly turned on in the high resistance state based on the supply of the power source Vcc.

The pad P1 is connected to the input terminal of the inverter circuit 2a, and the output terminal of the inverter circuit 2a is connected to the gate of the P-channel MOS transistor Tr3.

The source of the transistor Tr3 is the power source Vcc.
And the drain is connected to the pad P1.
The transistor Tr3 is formed to have a size larger than that of the transistor Tr1.

In the primary test of the semiconductor device as described above, when the floating probe 2 is brought into contact with the pad P1 and the power supply Vcc is supplied, the pad P1 is turned on by the ON operation of the transistor Tr1 as shown in FIG. Potential V3 rises.

Then, when the potential V3 of the pad P1 exceeds the threshold value Vt1 of the inverter circuit 2a, the output signal of the inverter circuit 2a becomes L level and the transistor T1.
r3 is turned on.

Then, a large current flows from the power source Vcc to the pad P1 via the transistor Tr3, the potential V3 of the pad P1 rapidly rises, and reaches the power source Vcc level in a short time.

Therefore, in the primary test when the pad P1 is used at the floating level, the potential V3 of the pad P1 can be fixed at the H level in a short time. As a result, the time from power-on to the start of the operation test can be shortened, and the potential V3 of the pad P1 can be quickly stabilized at the power supply Vcc level, so that an accurate operation test can be performed. .

FIG. 4 shows a second embodiment embodying the present invention. The same components as those of the conventional example will be described with the same reference numerals. The pad P2 is connected to the input terminal of the internal circuit 1 and the drain of the N-channel MOS transistor Tr2.

The source of the transistor Tr2 is connected to the ground GND, and the gate is connected to the power supply Vcc. The transistor Tr2 is always turned on in the high resistance state based on the supply of the power source Vcc.

The pad P2 is connected to the input terminal of the inverter circuit 2b, and the output terminal of the inverter circuit 2b is connected to the gate of the N-channel MOS transistor Tr4.

The source of the transistor Tr4 is connected to the ground GND, and the drain is connected to the pad P2. The transistor Tr4 corresponds to the transistor Tr2.
It is formed with a larger size.

In the primary test of the semiconductor device as described above, the operation mode is switched, and the probe 2 which has been inputting an H level signal until then is brought into a floating state,
Further, when the power supply Vcc is supplied, as shown in FIG. 5, first, the transistor Tr2 is turned on to turn on the potential V of the pad P2.
4 decreases.

When the potential V4 of the pad P2 becomes lower than the threshold value Vt2 of the inverter circuit 2b, the output signal of the inverter circuit 2b becomes H level and the transistor Tr4 is turned on.

Then, from the pad P2 to the transistor Tr4
A large current flows through the GND to the ground V, the potential V4 of the pad P2 is rapidly reduced, and the ground GND is short-timed.
Reach D level.

Therefore, in the primary test when the pad P2 is used at the floating level, the potential V4 of the pad P2 can be fixed to the L level in a short time. As a result, the time from power-on to the start of the operation test can be shortened, and the potential V4 of the pad P2 can be quickly stabilized at the ground GND level, so that an accurate operation test can be performed. .

In the first and second embodiments, the transistors Tr3 and Tr4 having a large size are turned on by the output signals of the inverter circuits 2a and 2b, but the potentials of the pads P1 and P2 are compared with each other. Therefore, the transistors Tr3 and Tr4 can be turned on by comparing with a preset reference voltage.

Further, instead of the transistors Tr3 and Tr4,
Many switching elements may be used. The technical ideas other than the claims that can be understood from the above embodiments will be described below along with their effects.

(1) In the present invention, the high resistance is composed of a small-sized MOS transistor, and the switch circuit is turned on when the potential difference between the pad potential and the power source is within a predetermined value. It is composed of MOS transistors. When the MOS transistor forming the switch circuit is turned on, the potential of the pad quickly shifts to the potential of the power supply.

[0044]

As described above in detail, the present invention can provide a semiconductor device having a bonding option function, which can perform a reliable operation test in a short time.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a circuit diagram showing a first embodiment.

FIG. 3 is a waveform diagram showing the operation of the first embodiment.

FIG. 4 is a circuit diagram showing a second embodiment.

FIG. 5 is a waveform diagram showing the operation of the second embodiment.

FIG. 6 is a circuit diagram showing a first conventional example.

FIG. 7 is a waveform diagram showing the operation of the first conventional example.

FIG. 8 is a circuit diagram showing a second conventional example.

FIG. 9 is a waveform diagram showing the operation of the second conventional example.

[Explanation of symbols]

 6 potential determination circuit 7 switch circuit P3 first pad P4 second pad V1 power supply voltage Tr18 P-channel MOS transistor Tr20 N-channel MOS transistor

Claims (3)

[Claims] 1. A semiconductor device in which a pad connected to an internal circuit is connected to a power supply via a high resistance to maintain the potential of the pad at a power supply level when the pad is in a floating state. A semiconductor device, wherein a switch circuit that is closed when a potential difference between the pad and the power source is within a predetermined value is connected between the pad and the power source. 2. The switch circuit has a P-channel MOS transistor connected between the pad and a high potential side power supply, an input terminal connected to the pad, and an output terminal connected to the gate of the P-channel MOS transistor. The semiconductor device according to claim 1, wherein the semiconductor device comprises an inverter circuit connected thereto. 3. The switch circuit has an N-channel MOS transistor connected between the pad and a low potential side power supply, an input terminal connected to the pad, and an output terminal connected to the gate of the N-channel MOS transistor. The semiconductor device according to claim 1, wherein the semiconductor device comprises an inverter circuit connected thereto.