JPH08221978A - Semiconductor memory device - Google Patents

Abstract

(57) [Abstract] [Purpose] To eliminate the unnecessary timing margin when switching the column select line (YS) and speed up the cycle time. [Structure] In addition to a timing control circuit (TG) that controls an input buffer (DIB), an output buffer (DOB) and the like in synchronization with an external clock (CLK), a Y decoder (Y
A timing control circuit (YTG) for switching the Y address input to DEC) asynchronously with CLK is provided. [Effect] Since YS is driven asynchronously, it is possible to remove an unnecessary timing margin while securing a timing margin when a plurality of address lines are simultaneously switched.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device. In particular, it relates to a synchronous dynamic random access memory (DRAM) which operates in synchronization with an external clock.

[0002]

2. Description of the Related Art A synchronous memory which inputs and outputs data in synchronization with a clock signal from the outside has been attracting attention as a method capable of obtaining a high data rate. A typical example thereof is a synchronous dynamic random access memory called a synchronous DRAM. The clock cycle time is determined by the cycle time of the column system circuit.

FIG. 3 shows an example of the configuration of a column circuit of a conventional synchronous DRAM. In this configuration, the timing control circuit TGc generates a control signal synchronized with the external clock signal CLK and controls other circuits. In the figure, YA
Bc is an address buffer, YACc is an address counter, YPDc is a Y address predecoder, and YDEC is Y.
It is a decoder. SMA is a sub-memory cell array, and although only one is shown in this figure for simplicity, a plurality of word lines WL and a plurality of data line pairs DLt and DLb are provided, and a large number of memory cells MC are provided at desired intersections. It is arranged. SAB is a sense amplifier block,
A plurality of sense amplifiers SA, input / output gates IOG, etc. are provided corresponding to the sub memory cell array, and the data line pair D
It is connected to Lt and DLb. In this figure, a precharge circuit and the like are omitted for simplicity. DICc is an input circuit, and DOCc is an output circuit.

The operation of the column system is performed in a state where the row system activate operation is completed. That is, a certain word line WL is driven to the word line voltage VCH to select the memory cell MC, the sense amplifier drive lines CSN and CSP become low level VSS and high level VCC, respectively, and appear on the data line pair DLt and DLb. This signal is in a state of being amplified by the sense amplifier SA. An external control signal (not shown) is taken in in synchronization with the clock CLK, and the timing control circuit TGc generates a control signal,
The Y address buffer YABc takes in the external address A. The Y address counter YACc operates using the Y address as an initial value and outputs the address. In the burst operation, the Y address counter YACc sequentially switches the Y addresses in synchronization with the clock. An address signal AY obtained by predecoding this address signal by the Y predecoder YPDc is input to the Y decoder YDEC. Furthermore, AY is decoded by the Y decoder YDEC,
The column select line YS of that address is driven. The sense amplifier SA is connected to the input / output line pair IOt, IOb by the input / output gate IOG selected by the column selection line YS.
Through the input / output line pair IOt, IOb, the sense amplifier SA
And the input circuit DICc or the output circuit DOCc are exchanged, and the input data Din is written or the output data Dout is read.

An example of the structure of the Y decoder YDEC is shown in FIG. This is 1024 column selection lines YS _{0 to} YS.
An example of a decoder that selects one from ₁₀₂₃ , Y predecoder Y
Address signal AY80 predecoded by PDc
~ AY83, AY60 to AY63, AY40 to AY4
3, AY20 to AY23, AY00 to AY03 are decoded. AY80 to AY83 and AY60 to AY63 are each ANDed to obtain 16 blocks YD.
Select one from A _{0 to} YDA ₁₅ . AY40 to AY43 and AY in the selected block (YDA _{15 in the} figure)
AND each one of 20 to AY23, and
One is selected from the six sub blocks YDB _{0 to} YDB ₁₅ . Furthermore, within the selected sub-block (YD in the figure
In B ₁₅ ), one column selection line (for example, any of YS _{1020 to} YS ₁₀₂₃ ) is selected by one of AY00 to AY03.

[0006]

When speeding up the cycle time of the burst operation, the timing margin at the time of switching the column select line becomes an obstacle. This is to prevent irrelevant column selection lines from being erroneously selected when simultaneously switching a plurality of address lines. In Figure 5,
An example of the timing when switching the column selection line is shown.
For simplicity, of the predecoded address signals,
Only AY80 to AY83 and AY00 to AY03 are shown.
The solid line shows the near end of the Y predecoder YPDc, and the broken line shows the far end. As shown in FIG. 4, the wirings of AY00 to AY03 have a large wiring delay because many NAND gates are connected. Therefore, AY80 to AY83 and AY00
The skew between AY03 and AY03 is large. Further, the number of gate stages up to the column selection line YS is different, and the gate delay is also different. Therefore, AY80 to AY83 and AY00 to AY
03, the column selection line Y from the Y predecoder YPDc.
It is difficult to make the delay times up to S uniform. for that reason,
When both AY80 to AY83 and AY00 to AY03 are switched, in order to prevent erroneous selection, the rising edge of the address signal must be delayed later than the falling edge to secure the timing margin. In addition, since the delay time of the address line in the column decoder increases with the high integration and large capacity of the memory, this timing margin must be increased. Address signal is clock CL
Since the switching is performed in synchronization with K, a timing margin is taken for the same time even when switching only AL within a burst in accordance with switching between both AH and AL between bursts.

Synchronous DRAM announced so far
In order to shorten the minimum clock cycle time, at least one of the pipeline method and the prefetch method is used. Pipelined synchronous DR
For AM, for example, IEEE Journal of Solid-State C
ircuits, vol. 29, no. 4, pp. 426-431, Apr. 1994. Even in the pipeline system, since the latch cannot be inserted between the output of the column decoder and the output of the main amplifier, it cannot be divided. For the prefetch type synchronous DRAM, for example, IEEE Journal
al of Solid-State Circuits, vol. 29, no. 4, pp. 52
9-533, Apr. 1994. In order to increase the amount of data to be read / written at the same time by the prefetch method, it is necessary to increase the number of input / output line pairs, main amplifiers, etc., so that the area penalty is large. Therefore, in addition to these, it is desired to speed up the cycle by a new method.

[0008]

The features of the present invention for achieving the above-mentioned object are that a plurality of word lines, a plurality of data lines arranged to intersect the plurality of word lines, and a plurality of words. Line and a plurality of memory cells arranged at desired intersections of the plurality of data lines, and a plurality of senses connected to the plurality of data lines for amplifying a signal read from the memory cells to the data line. An amplifier, an input / output line for exchanging signals with the plurality of sense amplifiers, a column selection line for selecting the plurality of sense amplifiers, and a Y decoder for selecting the column selection line are provided. In a semiconductor memory device in which a clock signal is input and data is exchanged with the outside in synchronization with the clock signal, it is unnecessary when only one set of address signal lines in the Y decoder is switched. It is to remove Lee timing margin. Therefore, at least one of the following methods is performed.

First method: In the case where a Y-system timing control circuit for performing timing control asynchronous with the clock signal is provided to switch the address signal lines in the Y-decoder and only one set of the address signal lines are switched. Remove timing margin.

Second method: A plurality of Y decoders are provided,
A local timing control circuit is provided corresponding to each Y decoder, and the local timing control circuit independently performs asynchronous timing control to eliminate a timing margin when only one set of the address signal lines is switched.

Third method: The address margin is removed by converting the address signal so that only one set of the address signal line is switched in the burst operation.

Fourth method: By converting an address signal, it is possible to reduce a case where a plurality of sets of the address signal lines are switched in a burst operation, and to take a timing margin when a plurality of sets of the address signal lines are switched. ,
If only one set is switched, the timing margin is removed.

[0013]

By performing at least one of the first to fourth methods, unnecessary timing margin can be removed without causing an erroneous operation of selecting an unrelated column select line in the burst operation. As a result, the burst operation cycle can be speeded up and the minimum clock cycle time can be shortened.

[0014]

【Example】

[First Embodiment] A first embodiment using an asynchronous operation,
As shown in FIG. Input / output with the outside is performed in synchronization with the clock, but operations of the Y decoder and the like are characterized by being performed asynchronously. Therefore, in addition to the timing control circuit TG which generates a control signal synchronized with the clock signal CLK, a Y-system control circuit YTG which generates a control signal asynchronous with the clock signal CLK is provided. In the figure, YAB is an address buffer, YAC is an address counter, YPD is a Y address predecoder, and YDEC is a Y decoder. SMA is a sub-memory cell array, and like the conventional example shown in FIG. 3, the word line WL and the data line pair DLt,
DLb is provided, and the memory cell MC is arranged at the desired intersection. SAB is a sense amplifier block, which is provided corresponding to the sub memory cell array as in the conventional example shown in FIG. 3, and a plurality of sense amplifiers SA and input / output gates IOG are connected to the data line pair DLt, DLb. ing. DIC is an input circuit, and DOC is an output circuit.

The operation is performed as follows. A control signal (not shown) from the outside is fetched in synchronization with the clock signal CLK, the timing control circuit TG generates the control signal, and the Y address buffer YAB fetches the external address A. The Y address counter YAC operates with the Y address as an initial value, and outputs the address. The operation of the Y address counter YAC is controlled by the Y system timing control circuit YTG, and the Y address is sequentially switched by the burst operation. At this time, the Y-system timing control circuit YTG
Are activated by the timing control circuit TG to generate a control signal asynchronously with the clock signal CLK in the burst operation, and the Y address counter YAC operates asynchronously. Y
The address signal output from the address counter YAC is Y
Predecoded by the predecoder YPD, and AY8
0-AY83, AY60-AY63, AY40-AY4
3, AY20 to AY23, AY00 to AY03 are input to the Y decoder YDEC. These are Y decoder YD
Decode with EC and select column select line YS
Drive. Y predecoder YPD and Y decoder YDE
C is composed of a static circuit having no timing signal, the operation timing of the column selection line YS is determined by the Y address counter YAC, and is asynchronous with the clock signal CLK. Then, data is transferred between the sense amplifier block SAB and the input circuit DIC or the output circuit DOC to write the input data Din or read the output data Dout. The input circuit DIC receives the input data Din in synchronization with the clock signal CLK under the control of the timing control circuit TG and asynchronously under the control of the Y-system timing control circuit YTG.
Write data is output to AB. On the other hand, the output circuit DO
C is controlled by the Y-system timing control circuit YTG to asynchronously receive read data from the sense amplifier block SAB, and is controlled by the timing control circuit TG to output the output data Dout in synchronization with the clock signal CLK. That is, the input circuit DIC and the output circuit DOC absorb the difference in operation timing between the circuit that operates synchronously and the circuit that operates asynchronously.

With the configuration described above, unnecessary timing margins at the time of switching the column selection lines can be removed, and the cycle time of burst operation can be shortened. FIG. 2 shows an example of the timing when switching the column selection line. For simplicity, of the predecoded address signals, AY
Only 80-AY83 and AY00-AY03 are shown. The solid line shows the near end of the Y predecoder YPDc, and the broken line shows the far end. As described for the conventional example shown in FIG.
The delay time from the Y predecoder YPDc to the column selection line YS is not uniform between Y80 to AY83 and AY00 to AY03. However, unlike the conventional example, it is designed so that both the rising edge and the falling edge of the address signal become faster. When only one set of address signal lines changes, for example, when only AY00 to AY03 change, switching is performed without taking a timing margin. In this case, although two column selection lines may overlap with each other, there is no possibility that an unrelated column selection line is erroneously selected. on the other hand,
When two or more sets of address signal lines change at the same time, for example, when both AY80 to AY83 and AY00 to AY03 are switched, the Y-system timing control circuit YT
The operation of the Y address counter YAC is controlled by G,
Take timing margin to prevent erroneous selection.

By the operation described above, unnecessary timing margin at the time of switching the column selection line can be removed, the cycle time of the burst operation can be speeded up, and the minimum clock cycle time can be shortened. This is because the Y decoder and other operations are performed asynchronously with the clock signal,
This is because the cycle of switching the column selection line becomes variable, and other timing margins can be removed while leaving a necessary timing margin.

[Second Embodiment] FIG. 6 shows the configuration of a second embodiment in which the Y decoder and the sub memory array are divided into a plurality of blocks, taking a 1 Gbit synchronous DRAM as an example. In the figure, the X system is omitted for simplicity. This embodiment is characterized by having a local timing control circuit for each block and performing independent timing control. In the figure, SIOC is a synchronous input / output circuit that operates in synchronization with the clock signal CLK. ABLK (AB
LK0 to ABLK7) are asynchronous blocks that operate asynchronously with the clock signal CLK. In the example of this 1-gigabit synchronous DRAM, 32 megabits each are provided with 32 pieces, and four pieces operate simultaneously. The synchronous input / output circuit SIOC and the asynchronous block ABLK are connected by a Y address bus YABUS, a read bus RBUS, and a write bus WBUS. The synchronous input / output circuit SIOC is
It is composed of a Y address buffer YAB, a Y predecoder YPD, an input buffer DIB, an input data latch DIL, an output buffer DOB, and a first-in first-out (FIFO) circuit RFIFO for output. However, F
The input side of the IFO circuit RFIFO operates asynchronously. The asynchronous block ABLK has a local timing control circuit LTG, and includes a Y decoder YDEC, a sub memory cell array, a sense amplifier block, and the like. In FIG. 6, Y
Although the decoder YDEC is simplified, it has a configuration as shown in FIG. AH is the upper Y address and is A in FIG.
Y80-AY83, AY60-AY63, AY40-A
This corresponds to Y43 and AY20 to AY23, and AL is a lower Y address and corresponds to AY00 to AY03 in FIG. YAL
Is a latch for the upper Y address AH, and YASR is a shift register for the lower Y address. Although the sub memory cell array and the sense amplifier block are also simplified and shown, they are configured similarly to FIG.
b, a sense amplifier SA, an input / output gate IOG, an input / output line pair IOt, IOb, a column selection line YS, and the like. WIL is a latch for data to be written to the input / output line pair IOt, IOb, and MA is an input / output line pair IOt, Ib.
It is a main amplifier for data read through Ob.

The read operation will be described with reference to the timing chart of FIG. The activate operation has already been completed, and the signals on the data line pair DLt and DLb are transmitted to the sense amplifier S.
In the state of being amplified by A, a read command is input by an external control signal (not shown in the figure) to perform a burst read operation. 2-bit pre-fetch is performed, burst operation of 8 clock cycles, read operation of asynchronous block ABLK is performed 4 times,
The four column selection lines YS are sequentially activated. In FIG. 7, the first burst operation is represented by a and the second burst operation is represented by b.

First, in the synchronous input / output circuit SIOC, the address signal A is taken in by the Y address buffer YAB in synchronization with the clock signal CLK, predecoded by the Y predecoder YPD, and output to the Y address bus YABUS. Sent to block ABLK. The Y predecoder YPD is a static circuit that does not use timing signals.

At this time, the latch YAL and the shift register YASR are through, and the Y address bus YA is
The BUS signal is amplified as it is, and the upper Y address A
The H and lower Y addresses AL are output to the Y decoder YDEC. Also, the local timing control circuit LTG
Detects the signal of the Y address bus YABUS and starts timing control of the asynchronous block ABLK. The control signal φ _L causes the latch YAL to latch the upper Y address (a in FIG. 7). Also, the shift register YASR
Thus, the lower Y address (0 in FIG. 7) at this time becomes the initial value. Upper Y address AH and lower Y address AL are Y
The column select line YS is decoded by the decoder YDEC.
(A0 in FIG. 7) is driven. The data line pair DLt, DLb is connected to the input / output lines IOt, IOb by the input / output gate IOG connected to the selected column selection line YS, and the read signal amplified by the sense amplifier SA is input / output lines IOt, IOb. Is transmitted to the main amplifier MA through. This signal is output to the read bus RBUS by activating the main amplifier by the control signal φ _R and amplifying it (FIG. 7).
A0, a1). Further, the control signal φ _A advances the lower Y address AL in the shift register YASR (see FIG. 7).
2) inside. This switches the column selection line (Fig. 7).
A2) inside. At this time, no timing margin is taken, but only the lower Y address AL is switched, so there is no risk of erroneous selection of the column selection line YS. Thereafter, the asynchronous block ABLK repeats the same operation. Main amplifier MA
The data output from the read bus RBUS from the
It is taken into the O circuit RFIFO at self timing.
The FIFO circuit RFIFO sends data to the output buffer DOB in synchronization with the clock signal CLK according to the desired latency. That is, by the FIFO circuit RFIFO,
The difference in operation timing between the asynchronous block ABLK and the synchronous input / output circuit SIOC is absorbed. However, in this embodiment, since 2-bit prefetch is performed, the data on the read bus RBUS fetched at one time is output in half every two cycles. The output buffer DOB outputs this as output data Dout.

At the fourth rise of the control signal φ _A, the lower address AL is reset by the shift register YASR. Further, by resetting the control signal φ _L , the latch YAL becomes through, and the higher address AH is also reset. Next, the read command is input again, so that the second burst operation is performed. In the first burst operation and the second burst operation, the address signals are generally largely different, and a plurality of address lines must be switched by the upper address AH and the lower address AL, but the lower address AL by the shift register YASR.
Is reset and then a new address is fetched, so that a timing margin is secured.

Next, the write operation will be described with reference to the timing chart of FIG. When the activate operation has already been completed, a write command is input by a control signal (not shown) from the outside to perform a burst write operation. 2-bit prefetch is performed, and the asynchronous block ABLK is read four times in a burst operation of 8 clock cycles. In FIG. 8, FIG.
Similarly, the first burst operation is represented by a and the second burst operation is represented by b.

First, in the synchronous input / output circuit SIOC, the address signal A is taken in by the Y address buffer YAB in synchronization with the clock signal CLK, predecoded by the Y predecoder YPD, and output to the Y address bus YABUS. Sent to block ABLK. Further, the input data Din is taken into the input buffer DIB,
It is output to the write bus WBUS through the latch DIL. However, since the 2-bit prefetch is performed in this embodiment, the input data Din captured in 2 cycles is acquired.
Are collectively output to the write bus WBUS at one time.

At this time, the latch YAL, the shift register YASR, and the Y decoder YDEC perform the same operation as the read operation described above, and the column select line YS (a0 in FIG. 8).
Is driven. Also, the local timing control circuit LT
G detects the signal of the Y address bus YABUS, starts the timing control of the asynchronous block ABLK, and drives the control signal φ _L. Further, the control signal φ _W causes the write data latch WIL to pass through, and the write bus WB
The data on the US is output to the input / output lines IOt and IOb.
The latch WIL latches the write data at self timing and returns the control signal φ _WN to the local timing control circuit LTG. The data output to the input / output lines IOt, IOb is sent to the data line pair DLt, DLb by the input / output gate IOG connected to the selected column selection line YS and written in the memory cell (not shown in FIG. 6). Be done. Then, the lower Y address AL is advanced in the shift register YASR by the control signal φ _A at a timing such that a desired writing time can be obtained (2 in FIG. 8). As a result, the column selection line is switched (a2 in FIG. 8). At this time, no timing margin is taken. Thereafter, the asynchronous block ABLK repeats the same operation.

Similar to the read operation, the lower address AL is reset at the fourth rise of the control signal φ _A. Further, the control signal φ _L also resets the upper address AH. Next, the write command is input again, so that the second burst operation is performed. A timing margin is automatically secured between the first burst operation and the second burst operation.

Also in this embodiment, as in the first embodiment, an unnecessary timing margin at the time of switching when selecting a column is removed, and the cycle time of the burst operation can be shortened. In this embodiment, the prefetch method is used to further shorten the minimum clock cycle time. Further, since the timing control is performed for each block, the delay time of the bus connecting the input / output circuit and the block is removed from the cycle time of the burst operation. Moreover, it is not necessary to distribute the clock to each sub array, and the load on the drive system is small. The timing signal for controlling the main amplifier and the like is closed in the sub-array, and the wiring resistance and wiring capacitance of those signal lines are small. Therefore, the rise time and fall time are short, and the pulse width can be reduced. Further, the skew between various timing signals is small.

In this embodiment, three self-timing circuits, that is, the local timing control circuit LTG,
The FIFO circuit RFIFO and the latch WIL enable subarray control asynchronous with the clock signal CLK. An example of the configuration of these three self-timing circuits is shown below.

The local timing control circuit LT shown in FIG.
A configuration example of G is shown in FIG. It detects the arrival of the Y address and operates at self timing. In FIG. 9, YALD is a rise detection circuit, BLC is a burst counter, and ROSC.
Is a ring oscillator. FF0 is a set-reset (SR) flip-flop, which outputs a low level in the initial state. Further, D0 to D5 are delay circuits, each of which is a circuit for delaying the rise of a signal, and the delay time thereof is set to a desired value corresponding to the delay time of other circuits.
These delay circuits can be omitted depending on the required delay time.

When the local write enable signal LWE is at the low level, the local timing control circuit operates as follows and generates the control signal as shown in FIG. Of the Y address bus YABUS in FIG. 6,
The rise detection circuit YALD detects that one of the lower Y address buses YALB corresponding to the lower addresses has risen, inverts the SR flip-flop FF0, and sets the control signal φ _L to the high level. The ring oscillator ROSC is activated by the control signal φ _L. Delay circuit D1, D2
Thus, the time until the signal is read out to the input / output line pair is secured, and the control signal φ _{R is set} to the high level. Next, the delay circuit D3 secures the operation time of the main amplifier, and sets the control signal φ _A to the high level. The burst counter BLC is operated by the control signal φ _A. Burst counter BL
C is a counter having a burst length control signal as an initial value,
When the control signal φ _A goes high for a desired number of times, the high level is output. After the control signal φ _A becomes high level, the delay circuit D5 secures the operation time of the shift register YASR in FIG. 6, and the control signals φ _R and φ _A
Returns to low level. At this time, if the burst counter BLC outputs a high level, the SR flip-flop is inverted and the control signal φ _{L is set} to a low level. When the low level is output, the control signal φ _L remains at the high level and the ring oscillator ROSC operates again.

On the other hand, when the write enable signal LWE is at the high level, this local timing control circuit operates in the same manner and generates the control signal as shown in FIG. However, the loop of the ring oscillator ROSC is different. After the control signal φ _L is reached, the delay circuit D1 secures the time until the column selection line is driven.
_{Set W} to high level. Next, the control signal φ _WN becomes high level by the latch WIL in FIG. Delay circuit D4
Thus, the write time is secured and the control signal φ _{A is set} to the high level. Then, the delay circuit D5 secures the operation time of the shift register YASR in FIG. 6, and the control signal φ _W becomes low level. As a result, the latch WIL in FIG.
_Causes the control signal φ _{WN to} go low and the control signal φ _WN
A gradually returns to low level.

As described above, the control signal asynchronous with the clock signal can be generated by using the ring oscillator properly provided with the delay circuit. The rise detection circuit YALD including the delay circuit D0 is used to prevent malfunction when the clock cycle time is extremely long. That is, if the first address signal continues to be output to the Y address bus YABUS even after the first burst operation is completed by this circuit, the burst operation is started again at that address. Is prevented.

FIG. 10 shows an example of the structure of an output FIFO circuit. This corresponds to one-fourth of the FIFO circuit RFIFO in FIG. 6, and takes in 8-bit data on the read bus at self timing and outputs it in units of 4 bits in synchronization with the clock. In FIG. 10, SRI is a shift register that switches input pointers PI ₀ , PI ₂ , ...
Is a shift register for switching the output pointers PO ₀ , PO ₁ , PO ₂ , PO ₃ , ... LRB _{0 to} LRB ₃ are blocks of latches, and latches LR ₀ , LR ₁ , LR ₂ , LR ₃ ,
... and a D flip-flop DFF. The number of latches is set to the required number according to latency and the like. Within each block, two latches are connected to the input pointer and one latch is connected to the output pointer. Also,
OCC is an output clock control circuit.

The operation on the input side is performed as follows. Before the burst read operation is started, the shift register SRI is reset by the reset signal Reset, and PI ₀ is selected as the input pointer. Further, all the read buses RB are at low level. Here, when one of the pair lines of the read bus RB becomes high level, the data is transmitted and taken in by the latches LR ₀ and LR ₁ in each block. For example, when one of the pair lines RB _0t and RB _0b goes high, the data is taken into the latch LR ₀ . The latches LR ₀ and LR ₁ latch the data when each pair of the read bus RB returns to the low level. At this time, the NOR circuit causes paired lines RB _0t and RB _0b.
It is detected that both have returned to the low level, and the shift register SRI advances the input pointer to PI ₂ . Then, the data transmitted from the read bus RB is fetched again in the latches LR ₀ and LR ₁ . Hereinafter, the same operation is repeated. The switching of the input pointer may be performed before the next data is transmitted to the latch, so that the risk of malfunction is small.

On the other hand, the operation on the output side is performed as follows.
Before starting the burst read operation, reset signal Res
The shift register SRO is reset by et, and PO ₀ is selected as the input pointer. Latch L
The data of R ₀ is input to the D flip-flop DFF. The output clock signal OCLK is generated by the output clock control circuit OCC. The output clock signal OCLK is a signal that is synchronized with the clock signal CLK, goes high level a number of times according to a desired burst length after a number of cycles corresponding to a desired latency from the read command. At its first rise, D flip-flop D
The output of FF (for example, DO ₀ ) is switched to the data in the latch LR ₀ . Further, the shift register SRO advances the output pointer to PO ₁ . Then, the output clock signal O
At the next rising edge of CLK, the output (eg, DO ₀ ) of the D flip-flop DFF switches to the data in the latch LR ₁ . Hereinafter, the same operation is repeated a number of times according to the desired burst length.

As described above, the input pointer is switched at the self-timing and the output pointer is switched in synchronization with the clock signal, so that the difference in the operation timing between the input and the output can be compensated. In this configuration example, multiplexing according to 2-bit prefetch is simultaneously performed,
The increase in circuit scale is suppressed. For the first data, the input pointer PI ₀ and the output pointer PO ₀ are selected so that the latch LR _{0 is} read from the read bus RB.
Is transmitted through to the D flip-flop DFF, and the influence on the access time is small.

By providing four circuits of FIG. 10, the FIFO circuit RFIFO in FIG. 6 can be constructed. FIFO
By configuring the circuit RFIFO by dividing it into four, four blocks ABL that operate simultaneously in the configuration shown in FIG.
The signal from K can be received at different timing for each block, and the difference in delay time of the read bus RBUS can be absorbed. At that time, the output clock control circuit OCC can be shared. When the data is delivered to the input / output circuit SIOC almost at the same time, it is possible to reduce the circuit scale by forming a single configuration and sharing the shift registers SRI and SRO.

FIG. 11 shows a configuration example of the write data latch in FIG. It detects the arrival of write data and operates at self timing. As shown in FIG. 6, the write bus WBUS is provided for each asynchronous block ABLK.
Take 8 bits from. In FIG. 11, WD is a rise detection circuit, and LW _0t , LW _0b , ..., LW _7t , LW _7b are latches. FF1 is an SR flip-flop, which outputs a low level to the output terminal Q and a high level to Q bar in the initial state. The delay circuit D6 is a circuit that delays the rising edge of the signal, and the delay time is set to a desired value.

When the local write enable signal LWE is at the low level, the operation is performed as follows. The rising detection circuit WD detects that one of the pair lines WB _0t and WB _0b of the write bus WB has become high level, and outputs the high level for a desired period determined by the delay circuit D6. Also,
The signal on the write bus WB is latched by LW (LW _0t , L
W _0b, ..., LW _7t, is incorporated into the LW _7b). For example,
The data of WB _0b is inverted and fetched at LW _0t . While the control signal φ _W is at the low level, the latch LW keeps the input / output line IO.
High level is output to (IO _0t , IO _0b , ..., IO _7t , IO _7b ). Here, when the control signal φ _W becomes high level by the local timing control circuit LTG (FIG. 9) in FIG. 6, the data taken in by the latch LW (eg LW _0t ) is input / output line IO (eg IO _0t ). Output to. Further, the SR flip-flop FF1 is inverted, the control signal φ _WN becomes high level, and the latch LW latches the data. Even if the write bus WB returns to the low level, the latch LW continues to output the latched data.
Next, the local timing control circuit LTG (FIG. 9) returns the control signal φ _W to the low level, whereby the latch LW outputs the high level. Further, the SR flip-flop FF1 is inverted again, the control signal φ _WN returns to the low level, and the latch LW releases the latch. Hereinafter, the same operation is repeated a number of times according to the burst length.

Although the case where the control signal φ _W becomes high level after the data arrives at the write bus WB has been described above, the operation is correct even if the order relation is reversed. In that case, the control signal φ _W goes high, causing the latch LW to go through. For example, the data WB _0b is reversed in LW _0t outputs to the input and output lines IO _0t.
Here, when the data arrives at the write bus WB, the latch LW outputs the data through, and the rising edge detection circuit WD detects the data and inverts the SR flip-flop. As a result, the control signal φ _WN goes high and the latch LW latches the data. As described above, since the order relation between the write bus WB and the control signal φ _W may be either, the operation timing margin is large. In either case, since the control signal φ _WN becomes high level after the data writing is started, the local timing control circuit L
A sufficient writing time can be secured by TG (FIG. 9).

The reason why the data on the write bus WB is inverted and output to the input / output line IO is to keep the input / output line IO at a high level while the data is not output.
As a result, as shown in FIG. 6, the column selection line is widely used in the DRAM in which the NMOS transistor is used for the input / output gate IOG and the positive feedback type amplifier common to the input and output is used as the sense amplifier SA. The static noise margin of the sense amplifier selected by YS can be secured. The rise detection circuit WD including the delay circuit D6 is used because the rise timing detection circuit YALD including the delay circuit D0 in the local timing control circuit of FIG.
This is to prevent malfunctions when the clock cycle time is very long, as in the case of using. That is, in the case where the first write data continues to be output to the write bus WB even if the column select line is switched by this circuit, the write data is sent to the data line pair selected by the next column select line. It is prevented that the data is transmitted to and written again.

Next, the effect of this embodiment will be quantitatively shown. FIG. 12 shows the effect of reducing the minimum clock cycle time according to the present embodiment, taking the 1 Gbit synchronous DRAM shown in FIG. 6 as an example. To perform 2-bit prefetch,
8 cycle burst operation, 4 column select lines YS
Are sequentially started, and read / write is performed 4 times. Since the write operation can be performed in a shorter time than the read operation, the minimum clock cycle time is determined by the read operation. The conventional method eliminates the required 2.2 ns in the intra-burst margin. In this method, the inter-burst margin becomes 0.2 ns longer than the conventional one because the signal of the Y address bus is fetched after the shift register for the lower Y address is once reset. Furthermore, by removing the delay time of the Y address bus and the read bus from the cycle, one read operation is shortened from 9.8 ns in the conventional method to 8.4 ns.
Combining the above effects, the operating time of 8 cycles is shortened from 48 ns to 36 ns. That is, the minimum clock cycle time is reduced from 6.0 ns to 3/4 of 4.5 ns.

[Third Embodiment] FIG. 13 shows a third embodiment in which the Y address is internally converted. In order to remove the timing margin at the time of switching the column selection line, the binary Y address is converted into the Gray code.
In FIG. 13, YAG is a Y address conversion circuit therefor. Others are configured similarly to the conventional example shown in FIG. That is, a timing control circuit TGg for generating a control signal synchronized with the clock signal CLK is provided, and an address buffer YAB, an address counter YACg, a Y address predecoder YPDg, a Y decoder YDEC, a sub memory cell array SMA, a sense amplifier block SAB,
It has an input circuit DICg and an output circuit DOCg.

The operation is performed as follows. This is the same as the conventional example shown in FIG. 3 except that the Y address is converted by the Y address conversion circuit YAG. The timing control circuit TGg generates a control signal in synchronization with the clock signal CLK, and the Y address buffer YAB takes in the external address A. With that as the initial value, the Y address counter YACg operates and outputs the binary Y address BY. Here, the Y address conversion circuit YAG converts the binary Y address BY into the gray code Y address CY, and the Y predecoder Y
Output to PDg. About this conversion, as an example, the lower 3
The bits are shown in Table 1.

[0045]

[Table 1]

Then, the gray code Y address CY is Y
Predecoding is performed by the predecoder YPDg, the address signal AYg is further decoded by the Y decoder YDEC, and the column selection line YS of that address is driven. Then, the sense amplifier block SAB and the input circuit D
Data is exchanged with ICg or the output circuit DOCg to write input data Din or output data Do.
ut is read.

A burst sequence of a synchronous DRAM, which is a typical synchronous DRAM, has a Hi
tachi IC Memory Data Book No.3 DRAM, Synchronous D
RAMand DRAM Module 11th Edition (Feb. 1994), pp.73
Sequence, as shown in 9-777
There are two types, Interleave, and Table 2
, The Y address is advanced.

[0048]

[Table 2]

As can be seen from the combination of Table 1 and Table 2, in both the sequence and the interleave, the binary Y address BY may change in two or more bits of the Y address at the same time. CY changes only one bit in all burst sequences. Therefore, within the burst operation, Y
Address lines AY80 to AY83 in the decoder YDEC,
AY60 to AY63, AY40 to AY43, AY20 to
Since only one set of AY23 and AY00 to AY03 changes at one time during the burst operation, a timing margin when switching the column select line is not necessary, and the minimum clock cycle time can be shortened. Moreover, the column selection line Y
Since S is switched at a constant cycle, the clock signal CLK
It is not necessary to provide a timing control circuit that is asynchronous with, and the circuit configurations of the input circuit DICg and the output circuit DOCg that exchange signals with the outside in synchronization with the clock signal are simple.

The converted address is not limited to the Gray code, and the same effect can be obtained as long as it is a code that changes only one bit in all burst sequences.

In this embodiment, the Y address counter and Y
Although the Y address conversion circuit is inserted between the predecoders, the Y address conversion circuit is inserted between the Y address buffer and the Y address counter.
It is also possible to insert an address conversion circuit and use a Gray code counter as the Y address counter. In that case,
Since it is not necessary to operate the Y address conversion circuit during the burst operation, power consumption can be reduced. In addition, since the path from the Y address counter to the output circuit becomes short, the cycle time can be shortened.

[Fourth Embodiment] FIG. 14 shows a fourth embodiment in which the first embodiment and the third embodiment are combined. A part of the binary Y address, for example, only the lower address is converted into the gray code, and the asynchronous operation is performed as in the first embodiment. In FIG. 14, YALG represents the binary lower Y address BYL and the gray code lower Y address C.
It is a lower Y address conversion circuit for converting to YL. Others are similar to those of the first embodiment shown in FIG. That is, in addition to the timing control circuit TGh that generates a control signal synchronized with the clock signal CLK, a Y-system timing control circuit YTGh that performs asynchronous timing control is provided, and the address buffer YAB and the address counter YAC are provided.
h, Y address predecoder YPDh, Y decoder YD
It has an EC, a sub memory cell array SMA, a sense amplifier block SAB, an input circuit DICh, and an output circuit DOCh.

The operation is performed as follows. The operation is the same as that of the first embodiment shown in FIG. 1 except that the Y address is converted by the Y address conversion circuit YALG. The timing control circuit TGh generates a control signal in synchronization with the clock signal CLK, and the Y address buffer YAB takes in the external address A. With that as the initial value, the Y system timing control circuit YT
The Y address counter YACh operates under the control of Gh, and the binary upper Y address BYH and the binary lower Y
The address BYL is output. However, the bit numbers of the binary upper Y address BYH and the binary lower Y address BYL are set to desired values. For example, the binary upper Y address BYH is 6 bits and the binary lower Y address BYL is 4 bits. Here, the binary upper Y address BYH is directly input to the Y decoder YDEC, while the binary lower Y address BYL is gray code lower Y address C by the lower Y address conversion circuit YALG.
It is converted to YL and input to the Y decoder YDEC. Y
The address signal output from the address counter YACh is
The address signal AYh is predecoded by the Y predecoder YPDh, further decoded by the Y decoder YDEC, and the column selection line YS of that address is driven. At this time, the Y-system timing control circuit YTGh controls the Y address counter YACh so that the timing margin is taken when a plurality of sets of the address signal AYh are switched and the timing margin is removed when only one set is switched. Then, data is transferred between the sense amplifier block SAB and the input circuit DICh or the output circuit DOCh to write the input data Din or read the output data Dout. Input circuit D
ICh and output circuit DOCh are timing control circuit TG
Controlled by both h and the Y-system timing control circuit YTGh, a signal synchronized with the clock signal CLK is sent and received by compensating for the difference in timing.

In the present embodiment, the binary lower Y address B
Since YL is converted to the gray code lower Y address CYL, the number of times of switching the column select line requiring a timing margin during the burst operation is small, and
The cycle time can be further shortened as compared with the above embodiment. Further, as compared with the case of converting the entire binary Y address BY as in the third embodiment, the configuration of the Y address conversion circuit becomes simpler, the area becomes smaller, and the operation time becomes shorter, so that the access time can be shortened.

[0055]

As described above, according to the present invention, the timing margin when the column select line is switched can be removed and the cycle time of the burst operation can be shortened without causing a malfunction.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a first embodiment using asynchronous operation.

FIG. 2 is a diagram showing the operation timing of the first embodiment.

FIG. 3 is a diagram showing a configuration example of a conventional synchronous DRAM.

FIG. 4 is a diagram showing a configuration example of a Y decoder.

FIG. 5 is a diagram showing an example of operation timing of a conventional synchronous DRAM.

FIG. 6 is a diagram showing a configuration of a second embodiment in which an asynchronous operation is performed for each block.

FIG. 7 is a diagram showing the timing of a read operation of the second embodiment.

FIG. 8 is a diagram showing the timing of the write operation of the second embodiment.

FIG. 9 is a diagram showing a configuration example of a local timing control circuit.

FIG. 10 is a diagram showing a configuration example of a FIFO circuit.

FIG. 11 is a diagram showing a configuration example of a write data latch.

FIG. 12 is a diagram showing an example of a cycle time reduction effect.

FIG. 13 is a diagram showing a configuration of a third embodiment for performing address conversion.

FIG. 14 is a diagram showing a configuration of a fourth embodiment using asynchronous operation and address translation.

[Explanation of symbols]

A ... External address. ABLK0-ABLK7 ... Asynchronous block. AH ... Higher Y address. AL ... Lower Y address. AY, AY80 to AY83, AY60 to AY63, AY
40-AY43, AY20-AY23, AY00-AY
03, AYg, AYh ... Predecoded Y address signal. BL ... Burst length control signal. BLC ... Burst counter. BY: Binary Y address. BYH ... Binary upper Y address. BYL ... Binary lower Y address. CLK ... Clock signal. CSN, CSP ... Sense amplifier drive line. CY ... Gray code Y address. CYL: Gray code lower Y address. D0 to D6 ... Delay circuit. DLt, DLb ... Data lines. DFF ... D flip-flop. DIB ... Input buffer. DIC, DICc, DICg, DICh ... Input circuit. DIL ... Input data latch. Din ... Input data. DO _{0 to} DO ₃ ... FIFO output data. DOB ... Output buffer. DOC, DOCc, DOCg, DOCh ... Output circuits. Dout ... Output data. FF0, FF1 ... SR flip-flop. IOt, IOb ... Input / output lines. IOG ... I / O gate. LR _{0 to} LR ₃ ... Latch. LRB _{0 to} LRB ₃ ... Latch block. LW _0t , LW _0b , LW _7t , LW _7b ... Latch. LTG ... Local timing control circuit. MA ... Main amplifier. MC ... Memory cell. OCC ... Clock control circuit for output. OCLK ... Output clock signal. PI ₀ , PI ₂ ... Input pointers. PO _{0 to} PI ₃ ... Output pointer. RB, RBUS ... Lead bus. RFIFO ... First-in first-out circuit. SA ... sense amplifier. SAB ... sense amplifier block. SIOC ... Synchronous input / output circuit. SMA ... Sub memory cell array. SRI, SRO ... Shift register. TG, TGc, TGg, TGh ... Timing control circuit. WB, WBUS ... Light bus. WIL ... Latch. WL ... Word line. YAB, YABc ... Y address buffer. YABUS ... Y address bus. YAC, YACc ... Y address counter. YAG ... Y address conversion circuit. YAL ... Latch. YALB ... Lower Y address bus. YALD ... Rise detection circuit. YALG ... Lower Y address conversion circuit. YASR ... Shift register. YDA _{0 to} YDA ₁₅ ... Y decoder block. YDB _{0 to} YDB ₁₅ ... Subblocks of Y decoder. YDEC ... Y decoder. YPD, YPDc, YPDg, YPDh ... Y predecoder. YS, YS _{0 to} YS ₁₀₂₃ ... Column selection line. YTG ... Y system timing control circuit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Miki Takeuchi 1-280 Higashi Koikeku, Kokubunji, Tokyo Metropolitan Institute of Hitachi, Ltd. (72) Inventor Masashi Horiguchi 1-280 Higashi Koikeku, Kokubunji, Tokyo Hitachi Ltd. Central Research Laboratory (72) Inventor Yoshinobu Nakagome 1-280, Higashi Koigokubo, Kokubunji, Tokyo Central Research Laboratory, Hitachi, Ltd. (72) Inventor Hitoshi Tanaka 5-2-1, Kamimizuhoncho, Kodaira-shi, Tokyo LSI Engineering Co., Ltd.

Claims (19)

[Claims] 1. A plurality of word lines, a plurality of data lines arranged so as to intersect with the plurality of word lines, and a plurality of data lines arranged at desired intersections of the plurality of word lines and the plurality of data lines. A memory cell; a plurality of sense amplifiers connected to the plurality of data lines for amplifying a signal read from the memory cell to the data line; a column selection line for selecting the plurality of sense amplifiers; A Y-decoder for selecting a column selection line, a timing control circuit that receives a clock signal from the outside and performs timing control in synchronization with the clock signal, and data that is input from the outside is controlled by the timing control circuit. In a semiconductor memory device having an input circuit for taking in, a Y-system timing control circuit for controlling the operation timing of the Y decoder is further provided, Serial Y-timing control circuit semiconductor memory device characterized by generating a Y-control signal independent timing with the clock signal. 2. The semiconductor memory device according to claim 1, wherein the Y-system control signal can take two or more cycles during a period in which the clock signal having a certain fixed cycle is input. And semiconductor memory device. 3. The semiconductor memory device according to claim 1, wherein the sense amplifier is a positive feedback circuit having a common input terminal and output terminal. 4. The semiconductor memory device according to claim 1, wherein the memory cell is composed of one MOS transistor and one capacitor. 5. A plurality of word lines, a plurality of data lines arranged so as to intersect the plurality of word lines, and a large number of a plurality of data lines arranged at desired intersections of the plurality of word lines and the plurality of data lines. A memory cell, a plurality of sense amplifiers connected to the plurality of data lines for amplifying a signal read from the memory cell to the data line, and a column selection line for selecting the plurality of sense amplifiers. And a timing control circuit that has a plurality of Y decoders that select the column selection lines, receives a clock signal from the outside, and performs timing control in synchronization with the clock signal, and the timing control of data input from the outside. In a semiconductor memory device having an input circuit controlled by a circuit,
Further, Y for controlling the operation timing of the Y decoder
A semiconductor memory device, wherein a plurality of system timing control circuits are provided corresponding to the Y decoders, and each Y system timing control circuit generates a Y system control signal having a timing independent of the clock signal. 6. The semiconductor memory device according to claim 5, further comprising a mechanism for performing a burst read operation of continuously reading a plurality of data by using the plurality of sense amplifiers and the output circuit, and the burst read operation. A semiconductor memory device characterized in that, when performing an operation, the minimum cycle of the Y-system control signal does not change even if the cycle of the clock signal is changed. 7. The semiconductor memory device according to claim 6, wherein when the burst read operation is performed, the cycle of the Y-system control signal is determined by the delay time of the circuit in the Y-system timing control circuit. And semiconductor memory device. 8. The semiconductor memory device according to claim 5, wherein the output circuit includes a first-in first-out circuit that takes in the data transmitted from the sense amplifier at a timing of the data and outputs the data in synchronization with the clock. A semiconductor memory device comprising: 9. The semiconductor memory device according to claim 5, further comprising a mechanism for performing a burst write operation for continuously writing a plurality of data by using the plurality of sense amplifiers and the input circuit, When performing the operation, the above Y
The system timing control circuit detects the timing of the data and generates the Y-system control signal. 10. The semiconductor memory device according to claim 5, wherein the sense amplifier is a positive feedback circuit having a common input terminal and output terminal. 11. The semiconductor memory device according to claim 5, wherein the memory cell is composed of one MOS transistor and one capacitor. 12. A plurality of word lines, a plurality of data lines arranged to intersect the plurality of word lines, and a plurality of data lines arranged at desired intersections of the plurality of word lines and the plurality of data lines. A memory cell; a plurality of sense amplifiers connected to the plurality of data lines for amplifying a signal read from the memory cell to the data line; a column selection line for selecting the plurality of sense amplifiers; A Y-decoder for selecting a column selection line, a timing control circuit that receives a clock signal from the outside and performs timing control in synchronization with the clock signal, and data that is input from the outside are controlled by the timing control circuit. Burst read for reading a plurality of data continuously by using the plurality of sense amplifiers and the output circuit It has a mechanism for performing an operation, a mechanism for performing a burst write operation for continuously writing a plurality of data using the plurality of sense amplifiers and the input circuit, and further has an address counter for the burst read operation or In the semiconductor memory device having an address buffer circuit which takes in an initial address inputted by a binary code from the outside during the burst write operation and an address counter which sequentially switches addresses, an address conversion circuit which converts the code of the address is provided. A semiconductor memory device characterized by the above. 13. The semiconductor memory device according to claim 12, wherein the address conversion circuit is provided between the address counter and the Y decoder, and the address counter is a binary counter. apparatus. 14. The semiconductor memory device according to claim 12, wherein the address signal converted by the address conversion circuit changes only bit by bit during the burst read operation or the write operation. Semiconductor memory device. 15. A semiconductor memory device according to claim 14, wherein two types of sequence and interleave are set in a burst sequence of the burst read operation or the write operation. 16. The semiconductor memory device according to claim 12, wherein the address conversion circuit converts a binary code into a Gray code. 17. The semiconductor memory device according to claim 16, wherein the address conversion circuit is provided between the address buffer and the address counter, and the address counter is a Gray code counter. Storage device. 18. The semiconductor memory device according to claim 1, further comprising: a mechanism for performing a burst read operation for continuously reading a plurality of data using the plurality of sense amplifiers and the output circuit; It has a mechanism for performing a burst write operation for continuously writing a plurality of data by using a sense amplifier and the input circuit, and further has an address counter, and when the burst read operation or the burst write operation is performed, an external A semiconductor memory device having an address buffer circuit for fetching an initial address input by a binary code from the address buffer, an address counter for sequentially switching addresses, and an address conversion circuit for converting the code of at least a part of the address. . 19. The semiconductor memory device according to claim 18, wherein the address conversion circuit converts a binary code into a Gray code.