JPH08222541A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE: To prevent the deterioration of wiring form and the generation of a stringer in a subsequent process by decreasing the level difference of an interlayer insulating film due to etching. CONSTITUTION: A silicon nitride film is formed on an interlayer insulating film 9, and the silicon nitride film 10 can be sloped by isotropically etching the silicon nitride film 10, and upon anisotropic etching of the remaining silicon nitride film and the interlayer insulating film 9, the etching start time for the interlayer insulating film 9 under the film 10 varies with the thickness of the silicon nitride film 10, and the etching state of the film 9 can also be sloped in response to the slope of the silicon nitride film 10. At the same time, absolute level difference can be decreased, a wiring layer formation state in a subsequent process can be improved, and the risk of disconnection is eliminated and the generation of a stringer can also be prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more specifically, an interlayer insulating film to be left in a region other than a contact when a contact hole is formed in a self-alignment manner of a split gate type flash memory. The purpose is to reduce the step due to.

[0002]

2. Description of the Related Art A manufacturing process of a conventional semiconductor device of this type will be described with reference to FIGS. FIG. 5 is a cross-sectional view showing a memory cell transistor in a split gate type flash memory and a state in which an interlayer insulating film covering the transistor is formed. The manufacturing process until the state shown in this sectional view is formed will be described below.

Reference numeral 51 is a P-type silicon substrate as a semiconductor substrate, and a floating gate 52 is formed on the substrate 51. This floating gate 52 is formed by first forming a polysilicon layer on the entire surface of the substrate, depositing a silicon nitride film (Si3N4 film) on the polysilicon layer, forming an opening in a predetermined region of the silicon nitride film, and then forming a polysilicon layer. The silicon layer is thermally oxidized, and the selective oxide film 53 (LO
After forming the (COS film), the silicon nitride film is removed.

Next, the polysilicon layer is etched using the selective oxide film 53 as a mask to form the floating gate 52. And this floating gate 5
A polysilicon layer 54, a tungsten silicide film 55 (WSix film) and a silicon oxide film 56 are formed on the second CVD film by CVD.
Then, the floating gate 52 is patterned so as to remain from the upper portion to the side portions as shown in FIG. The polysilicon layer 54 and the tungsten silicide film 55 form a control gate.

Then, using the control gate and the floating gate 52 as a mask, n + impurities are implanted into the semiconductor substrate 51 to form the source / drain diffusion layers 57,
58 is formed. Subsequently, an interlayer insulating film 59 made of a silicon oxide film is formed thereon, and then a photoresist 60 having an opening is formed in the self-aligned contact formation region above the source diffusion layer 57. Then, as shown in FIG. 6, the interlayer insulating film 59 is etched by using the photoresist 60 as a mask to form a contact hole 61 in a self-aligned manner, and then the photoresist 60 is removed, as shown in FIG. The wiring layer 62 that contacts the source diffusion layer 57 is formed by the Al sputtering method. The wiring layer 62 constitutes a bit line drawn from the source diffusion layer 57.

[0006]

However, a step is formed at the boundary between the masked portion and the unmasked portion of the photoresist 60 as shown in FIG. 6, and the wiring layer 61 made of aluminum or the like is formed in the next step. The shape deteriorates as shown in FIG. 7 (refer to the portion A in FIG. 7), and in a severe case, the wire may be broken.

In addition, stringers may occur. Therefore, it is an object of the present invention to reduce the step difference of the interlayer insulating film due to etching and prevent the deterioration of the wiring shape and the occurrence of stringers in the subsequent process.

[0008]

In order to solve the above-mentioned problems, the present invention forms a silicon nitride film on the interlayer insulating film when forming a contact hole in the recess of the interlayer insulating film having an uneven portion. A step of forming a photoresist having an opening above the recess on the silicon nitride film, a step of isotropically etching the silicon nitride film using the photoresist as a mask, The contact hole is formed by anisotropically etching the silicon nitride film and the interlayer insulating film remaining during the etching.

Further, according to the present invention, a step of forming a memory cell transistor in which a control gate is laminated on a floating gate, a step of forming an interlayer insulating film so as to cover the memory cell transistor, and a silicon film thereon. Forming a nitride film and forming a photoresist having an opening above the source diffusion layer of the memory cell transistor on the silicon nitride film; and isotropically etching the silicon nitride film using the photoresist as a mask A contact hole is formed by anisotropically etching the steps and the silicon nitride film and the interlayer insulating film remaining during the etching after removing the photoresist.

Further, the present invention comprises the steps of forming a polysilicon layer on a semiconductor substrate and forming a selective oxide film on the polysilicon layer, and etching and removing the polysilicon layer using the selective oxide film as a mask. Forming a floating gate, forming a control gate from the upper side of the floating gate to a side portion thereof, and implanting impurities into the semiconductor substrate by using the control gate and the floating gate as a mask to form a source / drain diffusion layer. And a step of forming an interlayer insulating film on the semiconductor substrate, a silicon nitride film is formed thereon, and a photoresist having an opening above the source diffusion layer is formed on the silicon nitride film. Process and a step of isotropically etching the silicon nitride film using the photoresist as a mask When, by anisotropically etching the silicon nitride film and the interlayer insulating film remaining on the etching after removing the photoresist, thereby forming a contact hole.

[0011]

With the above structure, the silicon nitride film 10 is formed on the interlayer insulating film 9, and the silicon nitride film 10 is isotropically etched to form a slope on the silicon nitride film 10 as shown in FIG. When the anisotropic etching of the remaining silicon nitride film 10 and the interlayer insulating film 9 in the next step is performed, the etching start time of the lower interlayer insulating film 9 is changed according to the thickness of the remaining silicon nitride film 10. Differently, the etching state can also be sloped corresponding to the slope of the silicon nitride film 10 as shown in FIG. 3, and at the same time the absolute level difference can be reduced, and as shown in FIG. The formation state of the layer 12 can be improved, the risk of disconnection can be eliminated, and the occurrence of stringers can be prevented.

[0012]

An embodiment of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a sectional view showing a state in which a memory cell transistor in a split gate type flash memory and an interlayer insulating film covering the transistor are formed.
The manufacturing process until the state shown in this sectional view is formed will be described below.

Reference numeral 1 is a P-type silicon substrate as a semiconductor substrate, and a floating gate 2 is formed on the substrate 1.
This floating gate is formed by first forming a polysilicon layer having a thickness of about 1500 Å to 2000 Å on the entire surface of the substrate and then forming a silicon nitride film (Si
3N4 film) is deposited and an opening is formed in a predetermined region of the silicon nitride film, and then the polysilicon layer is thermally oxidized at a temperature of about 900 ° C. to 950 ° C. to form a film of about 1700Å in the opening of the silicon nitride film. Thick selective oxide film 3 (LOC
After forming the OS film), the silicon nitride film is removed.

Next, the polysilicon layer is etched using the silicon oxide film 3 as a mask to form the floating gate 2 having a film thickness of about 1500Å to 2000Å. Then, on the floating gate 2, a polysilicon layer 4 having a film thickness of about 1000Å, about 1000
Å tungsten silicide film 5 (WSix film)
And CV the silicon oxide film 6 having a thickness of about 1000Å
The floating gate 2 is sequentially formed by the D method, and is patterned so as to remain from the upper portion to the side portion of the floating gate 2. The polysilicon layer 4 and the tungsten silicide film 5 form a control gate having a film thickness of about 2000Å.

Next, using the control gate and the floating gate 2 as a mask, n + impurities are implanted into the semiconductor substrate 1 to form the source / drain diffusion layers 7 and 8. Next, an interlayer insulating film 9 made of a silicon oxide film having a thickness of about 1500 Å to 2000 Å is formed thereon, and then a silicon nitride film 10 (Si3N4 film) having a thickness of about 300 Å to 500 Å is formed. Using the resist 11 as a mask, an etching gas having a flow rate of, for example, 15
As shown in FIG. 2, CDE (Chemical Dry E) was performed on the silicon nitride film 10 under the condition of RF power of 400 W using 0 SCCM of CF4 gas and 10 SCCM of N2 gas.
isotropic etching by the tching method. As shown in FIG. 2, the etching shape at this time is such that it enters the lower side of the photoresist 11 by side etching, and the etching amount of the silicon nitride film 10 decreases as it goes to the back side. In the process, the slope is gently formed toward the side where the contact hole is formed. Incidentally, the lower interlayer insulating film 9 may be slightly etched during this etching.

Further, in the present invention, since the silicon nitride film 10 is isotropically etched as described above, no side spacer remains at the portion B shown by the dotted arrow in FIG. When the insulating film 9 is etched, the etching residue of the interlayer insulating film 9 can be prevented, and a short circuit between electrodes can be prevented. Then, after removing the photoresist 11, an etching gas such as a CF4 gas with a flow rate of 30 SCCM and a CHF3 gas with a flow rate of 50 SCCM is used, and the entire surface of the substrate is subjected to RIE (Reactive Ion Et) as shown in FIG.
Ching) method is used for anisotropic etching to form the contact holes 12 in a self-aligned manner. At this time, the portion where the silicon nitride film 10 does not remain is etched first,
In the portion where the silicon nitride film 10 remains, the etching start of the interlayer insulating film 9 is delayed by the etching time of the silicon nitride film 10 and a difference in the remaining film occurs, and as shown in FIG. The slope can be added to the interlayer insulating film 9 so as to correspond to the slope, and the absolute step of the interlayer insulating film can be reduced as compared with the conventional case.

As a result, when the wiring layer 13 made of aluminum or the like forming the bit line extracted from the drain diffusion layer 8 is formed in the next step, the wiring layer 13 has a substantially uniform film thickness as shown in FIG. Can be formed with. still,
Although the split gate type flash memory has been described in the present embodiment, the present invention is not limited to this and can be applied to one in which a contact hole is formed in a self-aligned manner on an interlayer insulating film having an uneven portion.

[0018]

As described above, according to the present invention, it is possible to reduce the absolute level difference at the same time while providing a slope to the level difference at the etching location of the interlayer insulating film, and to improve the formation state of the wiring layer in the subsequent step. Therefore, it is possible to prevent the occurrence of disconnection and to prevent the occurrence of stringers.

Furthermore, since the silicon nitride film is isotropically etched, side spacers of the silicon nitride film that occur when anisotropically etching can be prevented, and etching residue of the interlayer insulating film due to the side spacers can be prevented. It is possible to prevent a short circuit from occurring between the electrodes.

[Brief description of drawings]

FIG. 1 is a first diagram illustrating a method for manufacturing a semiconductor device according to the present invention.
FIG.

FIG. 2 is a second sectional view similarly illustrating the method for manufacturing a semiconductor device.

FIG. 3 is a third sectional view similarly illustrating the method for manufacturing the semiconductor device.

FIG. 4 is a fourth cross-sectional view illustrating the same method of manufacturing a semiconductor device.

FIG. 5 is a cross-sectional view illustrating a conventional method for manufacturing a semiconductor device.

FIG. 6 is a cross-sectional view illustrating a conventional method for manufacturing a semiconductor device.

FIG. 7 is a cross-sectional view illustrating a conventional method for manufacturing a semiconductor device.

Claims (3)

[Claims] 1. A photoresist having a silicon nitride film formed on an interlayer insulating film when forming a contact hole in the concave portion of an interlayer insulating film having an uneven portion and having an opening above the recess on the silicon nitride film. And a step of isotropically etching the silicon nitride film using the photoresist as a mask, and anisotropically etching the silicon nitride film and the interlayer insulating film remaining during the etching after removing the photoresist. A method of manufacturing a semiconductor device, comprising forming a contact hole by performing the above. 2. A step of forming a memory cell transistor in which a control gate is laminated on a floating gate, a step of forming an interlayer insulating film so as to cover the memory cell transistor, and a silicon nitride film thereon. Forming a photoresist having an opening above the source diffusion layer of the memory cell transistor on the silicon nitride film, and isotropically etching the silicon nitride film using the photoresist as a mask, A method of manufacturing a semiconductor device, wherein a contact hole is formed by anisotropically etching a silicon nitride film and an interlayer insulating film remaining during the etching after removing the photoresist. 3. A step of forming a polysilicon layer on a semiconductor substrate and forming a selective oxide film on the polysilicon layer; and a step of etching / removing the polysilicon layer using the selective oxide film as a mask to make a floating gate. A step of forming a control gate from the upper side to the side of the floating gate, and implanting an impurity into the semiconductor substrate by using the control gate and the floating gate as a mask,
A step of forming a drain diffusion layer, a step of forming an interlayer insulating film on the semiconductor substrate, a silicon nitride film formed thereon, and a photoresist having an opening above the source diffusion layer on the silicon nitride film. And a step of isotropically etching the silicon nitride film using the photoresist as a mask, and anisotropically etching the silicon nitride film and the interlayer insulating film remaining during the etching after removing the photoresist. A method of manufacturing a semiconductor device, comprising forming a contact hole by performing the above.