JPH0822964A - Method for manufacturing semiconductor device - Google Patents

Abstract

(57) [Summary] [Object] According to the present invention, a desired resistance value is obtained by amorphization of a polycrystalline silicon film by an ion implantation method and recrystallization of the amorphous layer by a subsequent heat treatment. [Structure] In the first step, the polycrystalline silicon layer 12 is formed on the substrate 11.
After forming, the polycrystalline silicon layer by ion implantation method
Impurity ions 61 are selectively implanted into 12. At this time, the ion implantation energy is controlled to set the implantation depth of the impurity ions 61, so that the amorphous layer 13 corresponding to the ion implantation depth is formed on the polycrystalline silicon layer 12. And the second
In the step, recrystallization by heat treatment forms a polycrystalline silicon layer 14 having a crystal grain size corresponding to the thickness of the polycrystalline silicon layer 12 below the amorphous layer 13. The ion implantation energy can also be controlled by controlling the thickness of a coating layer (not shown) that transmits the impurity ions 61 and selectively covers the polycrystalline silicon layer 12.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device which is used as a resistance, a wiring, a diffusion layer, etc. of the semiconductor device.

[0002]

2. Description of the Related Art A polycrystalline silicon film in a semiconductor device is a gate electrode, a diffusion source, a contact opening, a wiring, a resistor, a thin film transistor [TFT (Thin Film Transistor).
or)] and so on. Then, according to the use, after forming a polycrystalline silicon film, the polycrystalline silicon film is doped with impurities by an ion implantation method, a diffusion method, or the like. Alternatively, a polycrystalline silicon film is formed in a state containing impurity ions. For example, the CVD method was used.

[0003]

However, when the polycrystalline silicon film is ion-implanted, the crystal grain size of the polycrystalline silicon film is not precisely controlled. Therefore, the resistance value of the polycrystalline silicon film does not meet the designed value. For example, even if a process that uses ion-implanted polycrystalline silicon instead of using DOPOS (doped polycrystalline silicon) as a diffusion source is developed, the subsequent heat treatment causes diffusion of ion-implanted impurity ions and a polycrystalline silicon film. Crystallization occurs simultaneously. Therefore, polycrystalline silicon having characteristics (for example, resistance value) different from the case of using DOPOS is formed. When such a polycrystalline silicon film is used as the electrode material, the characteristics as designed cannot be obtained. Further, the resistance value of the polycrystalline silicon film varies depending on the grain size of crystals formed by crystallization. Therefore, it is not possible to form a polycrystalline silicon film having a desired resistance value.

An object of the present invention is to provide a method of manufacturing a semiconductor device in which a polycrystalline silicon film partially having a desired resistance value can be obtained by partially controlling the crystal grain size of the polycrystalline silicon film. And

[0005]

The present invention is a method of manufacturing a semiconductor device, which has been made to achieve the above object. That is, in the first method, first, in the first step, a polycrystalline silicon layer is formed on a substrate, and then impurity ions are selectively implanted into the polycrystalline silicon layer by an ion implantation method. At that time, the ion implantation energy is controlled to set the implantation depth of the impurity ions, so that an amorphous layer corresponding to the ion implantation depth is formed at least above the polycrystalline silicon layer. Then, in the second step, a heat treatment is performed to crystallize the amorphous layer corresponding to the thickness of the polycrystalline silicon layer left below the amorphous layer, which is different from the initial polycrystalline silicon layer. A polycrystalline silicon layer having a crystal grain size is formed.

In the second method, in the first step, after forming a polycrystalline silicon layer on the substrate, a coating layer that selectively covers the polycrystalline silicon layer is formed. Then, in a second step, impurity ions are implanted into the polycrystalline silicon layer through the coating layer by the ion implantation method. At the same time, impurity ions are implanted into the portion of the polycrystalline silicon layer that is not covered with the coating layer. Then, a first amorphous layer is formed on the upper portion of the polycrystalline silicon layer covered with the coating layer, and the first amorphous layer is formed on the upper layer of the polycrystalline silicon layer not covered by the coating layer. Forming a thick second amorphous layer. Then in the third step,
Heat treatment is performed to crystallize the first amorphous layer and the second amorphous layer to form a first polycrystalline silicon layer on the first amorphous layer side. At the same time, a second polycrystalline silicon layer having a larger crystal grain size than the first polycrystalline silicon layer is formed on the second amorphous layer side.

In the third method, after the polycrystalline silicon layer is formed on the semiconductor substrate in the first step, when the impurity ions are selectively implanted into the polycrystalline silicon layer by the ion implantation method, By controlling the implantation energy and setting the implantation depth of the impurity ions, an amorphous layer corresponding to the ion implantation depth is formed at least above the polycrystalline silicon layer. Next, in a second step, a heat treatment is performed to crystallize the amorphous layer according to the thickness of the polycrystalline silicon layer left below the amorphous layer to form the polycrystalline silicon layer formed first. A polycrystalline silicon layer having a different crystal grain size is formed. At the same time, the impurity ions implanted in the polycrystalline silicon layer are diffused into the surface layer of the semiconductor substrate to form an impurity diffusion layer.

According to a fourth method, after the polycrystalline silicon layer is formed on the semiconductor substrate in the first step, the impurity ions are selectively and ion-implanted in the entire region of the polycrystalline silicon layer in the film thickness direction by the ion implantation method. Then, the region where the impurity ions are implanted is modified into an amorphous layer. Then, in a second step, heat treatment is performed to reform the amorphous layer into a single crystal silicon layer. At the same time, the impurity ions in the amorphous layer are diffused into the surface layer of the semiconductor substrate to form an impurity diffusion layer.

The control of the depth t of the amorphous layer at the time of the ion implantation is based on the LSS (Lindhard, Scharff, Schiott) theory, and the projected range Rp of the ions and the projected range dispersion ΔR.
Using p, the ion implantation energy is set by the equation t = Rp + κ · ΔRp, 2 ≦ κ ≦ 5.

The ion implantation is performed by an oblique ion implantation method in which the incident angle of impurity ions is set to a predetermined angle.

As the impurity ions, at least one or more ions of silicon and elements heavier than silicon are used.

[0012]

In the first method, when the impurity ions are selectively implanted into the polycrystalline silicon layer by the ion implantation method, the ion implantation energy is controlled to set the implantation depth of the impurity ions. An amorphous layer corresponding to the ion implantation depth is formed at least above the polycrystalline silicon layer. Then, since the heat treatment is performed, the amorphous layer is formed of polycrystalline silicon having a crystal grain size different from that of the initially formed polycrystalline silicon layer in accordance with the thickness of the polycrystalline silicon layer left under the amorphous layer. Become a layer.

In the second method, after forming a coating layer that selectively covers the polycrystalline silicon layer, impurity ions are implanted into the polycrystalline silicon layer including the portion covered with the coating layer by an ion implantation method. Therefore, impurity ions are shallowly implanted into the upper layer of the polycrystalline silicon layer covered with the coating layer to form a shallow first amorphous layer. On the other hand, impurity ions are deeply implanted into the upper layer of the polycrystalline silicon layer that is not covered by the coating layer, and the second thicker than the first amorphous layer.
An amorphous layer is formed. Since heat treatment is performed after that,
The first and second amorphous layers are crystallized by taking over the crystal of the polycrystalline silicon layer remaining on each lower surface side. At that time, since the size of the crystal grain size is determined in accordance with the thickness of the remaining polycrystalline silicon layer, more polycrystalline silicon layers are formed on the remaining first amorphous layer side. The crystal grain size of the first polycrystalline silicon layer is smaller than that of the second polycrystalline silicon layer formed on the second amorphous layer side.

In the third method, since the ion implantation energy for selectively implanting the impurity ions into the polycrystalline silicon layer is controlled, the implantation depth of the impurity ions is changed. Therefore, an amorphous layer corresponding to the ion implantation depth is formed in the polycrystalline silicon layer. Then, by performing heat treatment, the amorphous layer is crystallized. At the same time, the impurity ions implanted in the polycrystalline silicon layer diffuse into the semiconductor substrate, so that an impurity diffusion layer is formed in the surface layer of this semiconductor substrate.

In the fourth method, after the polycrystalline silicon layer is formed on the semiconductor substrate, the impurity ions are selectively and ion-implanted into the entire area of the polycrystalline silicon layer in the film thickness direction. The entire region in the film thickness direction of the polycrystalline silicon layer into which the impurity ions are implanted becomes an amorphous layer. Since the heat treatment is performed, the amorphous layer takes over the crystal of the semiconductor substrate, and becomes a monocrystalline silicon layer if the semiconductor substrate is crystallized as a single crystal, for example. At the same time, the impurity ions in the amorphous layer diffuse into the surface layer of the semiconductor substrate to form an impurity diffusion layer.

The depth t of the amorphous layer formed by the above-mentioned ion implantation is controlled by t = Rp + κ using the projected range Rp of ions and the projected range dispersion ΔRp based on the LSS theory.
Since the ion implantation energy is set by the equation ΔRp, 4 ≦ κ ≦ 5, the implantation depth of the impurity ions is set almost accurately. Therefore, the film thickness of the polycrystalline silicon layer which is not amorphized is also set.

Further, since the ion implantation is performed by an oblique ion implantation method in which the incident angle of the impurity ions is set to a predetermined angle, the impurity ions are implanted even if the polycrystalline silicon layer is formed in the step portion. It

Since at least one ion of silicon and an element heavier than silicon is used as the impurity ions, the portion of the polycrystalline silicon layer in which the impurity ions are implanted becomes an amorphous layer.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the first invention will be described with reference to the manufacturing process diagram of FIG.

As shown in (1) of FIG. 1, in the first step, first, a polycrystalline silicon film (not shown) is formed on the substrate 11 by a film forming technique such as a CVD method, a vapor deposition method, and a sputtering method. Then, the polycrystalline silicon film is patterned by the lithography technique and etching to form the polycrystalline silicon layer 12.

Then, as shown in (2) of FIG.
Forming film (not shown) for covering the polycrystalline silicon layer 12 by a film forming technique such as a vapor deposition method, a vapor deposition method, or a sputtering method.
Is formed of, for example, silicon oxide. After that, the mask forming film is patterned by a lithography technique and etching to form a mask 51 that selectively covers the polycrystalline silicon layer 12. Then, impurity ions 61 are selectively implanted into the polycrystalline silicon layer 12 by the ion implantation method using the mask 51. At this time, the ion implantation energy is controlled to change the implantation depth of the impurity ions 61, so that the amorphous layer 13 corresponding to the ion implantation depth is formed on at least the upper layer of the polycrystalline silicon layer 12. In this figure, the impurity ions 61 are distributed over the entire area in the film thickness direction.
Is implanted to make the region amorphous.

As the impurity ions 61, one or more ions of at least one of silicon and elements heavier than silicon are used in order to make the polycrystalline silicon layer 12 amorphous. For example, the ions include silicon ions (Si ⁺ ), arsenic ions (As ⁺ ), phosphorus ions (P ⁺ ), antimony ions (Sb ⁺ ), and the like.

By the same ion implantation method as described above,
After selectively amorphizing the polycrystalline silicon film, the polycrystalline silicon film may be patterned to form the polycrystalline silicon layer 12 including the amorphized portion.

After that, the mask 51 may be removed by etching. If the mask 51 is made of resist, at least one of ashing and wet processing is performed to remove the mask 51.

Subsequently, the second step shown in FIG. 1C is performed. In this figure, the state after the mask (51) is removed is shown. In this step, heat treatment is performed to polycrystallize the amorphous layer (13). And the amorphous layer (13) is
A polycrystalline silicon layer 14 having a crystal grain size different from that of the polycrystalline silicon layer 12 is formed corresponding to the thickness of the polycrystalline silicon layer 12 left under the polycrystalline silicon layer 12. Also, the mask (5
The crystal grain size of the polycrystalline silicon layer 12 in the portion covered by 1) does not change.

In the embodiment described with reference to FIG. 1 above, since the ion implantation energy is controlled to set the implantation depth of the impurity ions 61, the ion implantation energy determines the ion implantation depth. Then, the depth of the amorphous layer 13 is determined according to the ion implantation depth. That is,
The thickness of the polycrystalline silicon layer 12 left below the amorphous layer 13 is also determined. Since the heat treatment is performed, the amorphous layer 13 is crystallized. At this time, the thinner the remaining polycrystalline silicon layer 12 is, the larger the grain size of the formed crystal is. Therefore, the polycrystalline silicon layer 14 formed by recrystallizing the amorphous layer 13 has the impurity ions 61.
Since the crystal grain size is larger than that of the polycrystalline silicon layer 12 in which is not implanted, the resistance is low. Further, since the impurity ions 61 are ions of silicon and an element heavier than silicon, the region of the polycrystalline silicon layer 12 into which the impurity ions 61 are implanted is made amorphous.

Next, an example of a specific method for simultaneously forming the wiring and the resistance using the first invention will be described. Note that FIG. 1 is used in the description.

First, the first step is performed. By the low pressure CVD method (the film forming temperature is 620 ° C.), the film thickness of 110 is formed on the substrate 11.
A polycrystalline silicon film having a thickness of nm is formed. After that, the polycrystalline silicon film is patterned by a lithography technique and etching to form a polycrystalline silicon layer 12. Then, the polycrystalline silicon layer 12 is formed by the CVD method.
A mask forming film (not shown) for covering
Then, a mask 51 is formed to selectively cover the polycrystalline silicon layer 12 with the mask forming film by lithography and etching.

Impurity ions (for example, silicon ions) 61 are selectively implanted into the polycrystalline silicon layer 12 by the ion implantation method using the mask 51. In this ion implantation, the ion implantation energy is 25
keV, the dose amount is 3P (peta) ions / cm ^2.
Set to. When the ion implantation is performed in this manner, the polycrystalline silicon layer 12 into which the silicon ions are implanted is wholly amorphized in the film thickness direction to become the amorphous layer 13. Further, the portion of the polycrystalline silicon layer 12 covered by the mask 51 maintains the initial crystal grain size (about 50 nm).

Then, the second step is performed. That is, heat treatment for recrystallization (eg, heating at 600 ° C. for 80 hours)
Then, the amorphous layer 13 is crystallized. The polycrystalline silicon layer 14 formed by crystallization has a larger crystal grain size than the non-amorphous polycrystalline silicon layer 12. The resistance value of the polycrystalline silicon layer 14 is about 200.
It became Ω / □. On the other hand, the crystal grain size of the non-amorphous polycrystalline silicon layer 12 was about 50 nm, and its resistance value was about 900 Ω / □.

Next, an embodiment of the second invention will be described with reference to the manufacturing process chart of FIG. The same components as those described with reference to FIG. 1 are designated by the same reference numerals.

As shown in (1) of FIG. 2, in the first step, first, a polycrystalline silicon film (not shown) is formed on the substrate 11 by a film forming technique such as a CVD method, a vapor deposition method, and a sputtering method. To do. After that, the polycrystalline silicon film is patterned by a lithography technique and etching to form a polycrystalline silicon layer 12. Next, a coating layer forming film 21 that covers the polycrystalline silicon layer 12 is formed of, for example, silicon oxide by a film forming technique such as a CVD method, a vapor deposition method, or a sputtering method. Thereafter, a portion indicated by a chain double-dashed line of the coating layer forming film 21 is removed by a lithography technique and etching to form a coating layer 22 which selectively covers the polycrystalline silicon layer 12.

Then, the second step shown in FIG. 2B is performed. In this step, impurity ions 62 are introduced into the polycrystalline silicon layer 12 through the coating layer 22 by the ion implantation method.
Inject. At the same time, the impurity ions 62 are also implanted into the polycrystalline silicon layer 12 which is not covered with the coating layer 22. As a result, the polycrystalline silicon layer 12 implanted with the impurity ions 62 is made amorphous, and the first amorphous layer 23 is formed on the polycrystalline silicon layer 12 covered with the coating layer 22. A second amorphous layer 24 is formed on the polycrystalline silicon layer 12 which is not covered with the coating layer 22. Here, a case is shown in which the first amorphous layer 23 is formed on the upper layer of the polycrystalline silicon layer 12, and the second amorphous layer 24 is formed over the entire area of the polycrystalline silicon layer in the film thickness direction.

After the polycrystalline silicon film is selectively covered with the coating layer, the polycrystalline silicon film is made amorphous by the same ion implantation method as described above. Then, the polycrystalline silicon film may be patterned to form a polycrystalline silicon layer 12 having an amorphized portion. Further, as the impurity ions 62, the same ions as those described in the embodiment of the first invention are used.

After that, the coating layer 22 may be removed by etching, for example. Then, the third step shown in FIG. 2C is performed. This figure shows the state after removing the coating layer (22). In this step, heat treatment is performed to crystallize the first and second amorphous layers (23) and (24). Then, the first polycrystalline silicon layer 25 is formed in the portion covered with the coating layer (22), and the crystal grain size is larger than that in the first polycrystalline silicon layer 25 in the portion not covered with the coating layer (22). A large second polycrystalline silicon layer 26 is formed.

In the second invention, the polycrystalline silicon layer 1
2 is selectively covered with the coating layer 22, and then the impurity ions 6
Since 2 is implanted, the implantation depth of the impurity ions 62 is controlled by the thickness of the coating layer 22. Therefore, the impurity ions 62 are implanted deeper into the polycrystalline silicon layer 12 not covered with the coating layer 22 than the portion covered with the coating layer 22. By controlling the depth of the impurity ions 62 in this manner, the thickness of the amorphous layer formed is controlled. That is, the polycrystalline silicon layer 12 not covered with the coating layer 22 is thicker than the first amorphous layer 23 formed on the polycrystalline silicon layer 12 covered with the coating layer 22 in the second non-layer. A crystalline layer 24 is formed. Therefore, the polycrystalline silicon layer 12 remains thicker below the first amorphous layer 23 than below the second amorphous layer 24. Then, since the heat treatment is performed, the first and second amorphous layers 23 and 24 are formed.
Is crystallized by taking over the crystal of the polycrystalline silicon layer 12 remaining therebelow. Therefore, the first polycrystalline silicon layer 25 formed by crystallizing the first amorphous layer 23 side where a large amount of the polycrystalline silicon layer 12 remains is formed by crystallizing the second amorphous layer 24 side. 2 The crystal grain size is smaller than that of the polycrystalline silicon layer 26. Therefore, the first polycrystalline silicon layer 25 has a higher resistance than the second polycrystalline silicon layer 26.

Next, an example of a specific method for simultaneously forming wirings and resistors using the second invention will be described. Note that FIG. 2 is used in the description.

First, the first step is performed. By the low pressure CVD method (the film forming temperature is 620 ° C.), the film thickness of 110 is formed on the substrate 11.
A polycrystalline silicon film having a thickness of nm is formed. After that, the polycrystalline silicon film is patterned by a lithography technique and etching to form a polycrystalline silicon layer 12. Then, the polycrystalline silicon layer 12 is formed by the CVD method.
After forming the coating layer forming film 21 covering the polycrystalline silicon layer 12 by a lithographic technique and etching, a coating layer 22 that selectively covers the polycrystalline silicon layer 12 is formed by a lithography technique and etching. To do.

Then, the implantation depth of impurity ions (for example, arsenic ions) 61 is selectively controlled in the polycrystalline silicon layer 12 by the ion implantation method using the coating layer 22. In this ion implantation, for example, the ion implantation energy is 70 keV and the dose is 3P (peta) i.
Set to ons / cm ² . When the ion implantation is performed in this manner, arsenic ions are implanted into the upper layer of the polycrystalline silicon layer 12 in the portion covered by the coating layer 22, and the region 70 nm deep from the surface is amorphized to be the first layer. 1 amorphous layer 23
Is formed. The polycrystalline silicon layer 12 is formed in the lower layer
Remains 0 nm thick. Further, arsenic ions are implanted into the entire area of the polycrystalline silicon layer 12 not covered with the coating layer 22 in the film thickness direction, and all the area in the film thickness direction becomes amorphous so that the second amorphous film is formed. Layer 24 is formed.

Then, the second step is performed. That is, heat treatment for recrystallization (eg, heating at 700 ° C. for 2 hours and
Heating at 00 ° C. for 20 minutes) to form the first and second amorphous layers 2
Crystallize 3,24. The portion covered with the coating layer 22 becomes the first polycrystalline silicon layer 25 having a small grain size.
The portion of the second amorphous layer 24 not covered by 2 becomes the second polycrystalline silicon layer 26 having a large grain size. The resistance value of the first polycrystalline silicon layer 25 is about 650 Ω / □, and the resistance value of the one second polycrystalline silicon layer 26 is about 450.
It became Ω / □.

Next, an embodiment of the third invention will be described with reference to the manufacturing process chart of FIG. The same components as those described with reference to FIG. 1 are designated by the same reference numerals.

As shown in FIG. 3A, the semiconductor substrate 3
An insulating film 32 is formed on the insulating film 1.
The first opening 33 is formed in the second part 2. First, in the first step, a polycrystalline silicon film (not shown) is formed on the insulating film 32 including the inside of the first opening 33 by a film forming technique such as a CVD method, a vapor deposition method, and a sputtering method. After that, the polycrystalline silicon film is patterned by a lithography technique and etching to form a polycrystalline silicon layer 12.

Then, as shown in (2) of FIG.
A mask 53 that covers the polycrystalline silicon layer 12 is formed of, for example, silicon oxide by a film forming technique such as a vapor deposition method, a vapor deposition method, or a sputtering method. Then, the mask 53 is patterned by the lithography technique and the etching,
A second opening 54 is formed in the mask 53 on the first opening 33. Then, impurity ions 63 are selectively implanted into the polycrystalline silicon layer 12 by an ion implantation method using the mask 53. At that time, the ion implantation energy is controlled to set the implantation depth of the impurity ions 63. Thus, the amorphous layer 13 corresponding to the ion implantation depth is formed on at least the upper layer of the polycrystalline silicon layer 12. As the impurity ions 63, the same ions as those described in the first embodiment of the invention are used.

After that, the mask 53 may be removed by etching. When the mask 53 is formed of a resist, at least one of ashing processing and wet processing is performed to remove the mask 53.

Subsequently, the second step shown in FIG. 3C is performed. This figure shows the state after the mask 53 is removed.
In this step, heat treatment is performed to polycrystallize the amorphous layer (13) to form a polycrystalline silicon layer 14. that time,
The impurity ions (63) implanted in the amorphous layer (13) are diffused into the surface layer of the semiconductor substrate 31 to form the impurity diffusion layer 16.

In the third aspect of the invention, the ion implantation energy is controlled to set the implantation depth of the impurity ions 63, so that the ion implantation energy determines the ion implantation depth. Then, the depth of the amorphous layer 13 is determined according to the ion implantation depth. That is, the thickness of the polycrystalline silicon layer 12 left below the amorphous layer 13 is also determined. Since the heat treatment is performed, the amorphous layer 13 is crystallized. At this time, the polycrystalline silicon layer 14 is formed by taking over the crystallinity of the remaining polycrystalline silicon layer 12.
Further, the impurity ions 63 implanted in the polycrystalline silicon layer 12 diffuse into the semiconductor substrate 31. Therefore, the impurity diffusion layer 16 is formed on the surface layer of the semiconductor substrate 31.

The process described above can be applied when forming the emitter of an npn bipolar transistor. One example thereof will be specifically described with reference to the explanatory view of the method for forming the emitter in FIG.

As shown in FIG. 4A, a normal npn
Type bipolar transistor process, ap ⁺ type base layer 36 is formed on the upper layer of the semiconductor substrate 31 having the n type epitaxial layer 34 and the n ⁺ type buried layer 35 thereunder, that is, on a part of the upper layer of the n type epitaxial layer 34. Has been done. An insulating film 32 is formed on the semiconductor substrate 31.
Is formed, and the first opening 33 is formed on a part of the p ⁺ type base layer 36.

First, in the first step, a polycrystalline silicon film (not shown) having a thickness of, for example, 110 nm is formed on the insulating film 32 including the inside of the first opening 33 by a low pressure CVD method (film forming temperature is 620 ° C.). Form a thick film. After that, the polycrystalline silicon film is patterned by a lithography technique and etching to form a polycrystalline silicon layer 12.

Then, as shown in (2) of FIG.
Mask 5 for covering the polycrystalline silicon layer 12 by a method
3 is formed of silicon oxide having a film thickness of 150 nm, for example. Then, the mask 53 is patterned by a lithography technique and etching to form a second opening 54 in the mask 53 on the first opening 34. Then, impurity ions (for example, arsenic ions) 63 are selectively implanted into the polycrystalline silicon layer 12 by an ion implantation method using the mask 53. In this ion implantation, for example, the ion implantation energy is set to 40 keV and the dose amount is set to 6 P (peta) ions / cm ² . When the ion implantation is carried out in this manner, the portion of the polycrystalline silicon layer 12 which is not covered with the mask 53 is amorphized to a depth of 76 nm from the surface in the film thickness direction. Then, the amorphous layer 13 is formed, and the polycrystalline silicon layer 12 is left below the amorphous layer 13 in a thickness of 34 nm. When the thickness of the polycrystalline silicon layer 12 is 100 nm and the ion implantation energy is 30 keV, the thickness of the amorphous layer 13 is 62.
nm, and the thickness of the polycrystalline silicon layer 12 thereunder is 38 nm. On the other hand, arsenic ions are not implanted in the portion of the polycrystalline silicon layer 12 covered by the mask 53. Then, the mask 53 is removed by etching, for example.

Then, as shown in FIG. 4C, the second step is performed. That is, a heat treatment for recrystallization (for example, heating at 700 ° C. for 2 hours and heating at 900 ° C. for 20 minutes) is performed to make the amorphous layer (13) almost equal to the initial polycrystalline silicon layer 12. To obtain a polycrystalline silicon layer 14 having a crystal grain size of. At this time, the impurity ions (63) implanted in the polycrystalline silicon layer 12 are diffused into a part of the surface layer of the p ⁺ type base layer 36 to diffuse the n ⁺ type emitter layer 3
7 (corresponding to the impurity diffusion layer 16) is formed. The polycrystalline silicon layer 14 can be used as an emitter electrode.

Next, an embodiment of the fourth invention will be described with reference to the manufacturing process chart of FIG. The same components as those described with reference to FIG. 1 are designated by the same reference numerals.

As shown in FIG. 5A, an insulating film 32 is formed on the semiconductor substrate 31 in the same manner as described with reference to FIG. 3A, and the first opening is formed in the insulating film 32. Three
3 is formed. Then, the polycrystalline silicon layer 12 is formed on the insulating film 32 including the inside of the first opening 33.

Then, as shown in FIG. 5B, the mask 53 for covering the polycrystalline silicon layer 12 is formed of silicon oxide in the same manner as described in FIG. The second opening 54 is formed in the mask 53 on the first opening 33. After that, by the ion implantation method, the impurity ions 64 are selectively implanted into the polycrystalline silicon layer 12 from the second opening 54 and over the entire region in the thickness direction of the polycrystalline silicon layer 12. The region into which the impurity ions 64 are implanted is made amorphous and the amorphous layer 1 is formed.
It will be 3. As the impurity ions 64, the same ions as those described in the first invention are used.

After that, the mask 51 may be removed by etching. If the mask 51 is formed of a resist, at least one of ashing and wet processing is performed to remove the mask 53.

Then, the second step shown in FIG. 5C is performed. In addition, in this figure, the case where the mask 53 is removed is shown. In this step, heat treatment is performed to form the amorphous layer (13).
Is reformed into a monocrystalline silicon layer 17. At that time, the impurity ions (6
In 4), the impurity diffusion layer 16 is formed by diffusing into a part of the surface layer of the semiconductor substrate 11.

In the fourth aspect of the invention, the impurity ions 64 are selectively implanted by ion implantation into the entire region of the polycrystalline silicon layer 12 in the film thickness direction, so that the implanted region is the amorphous layer 13. Is reformed to. And the amorphous layer 1
Since No. 3 is formed so as to reach the semiconductor substrate 31, the amorphous layer 13 is crystallized by inheriting the single crystallinity of the semiconductor substrate 31 by performing heat treatment. Therefore, the amorphous layer 13 is reformed into the single crystal silicon layer 17. At the same time, the impurity ions 64 in the amorphous layer 13
Diffuses into the surface layer of the semiconductor substrate 11, so that the semiconductor substrate 3
The impurity diffusion layer 16 is formed on the first surface layer.

The process described with reference to FIG.
It can be applied when forming the emitter of a pn-type bipolar transistor. An example will be described.

This process is almost the same as the process described with reference to FIG. The difference from the process described in FIG. 4 is the condition of the ion implantation method using the mask 53. That is, arsenic ions are used as the impurity ions 64, the ion implantation energy is set to 70 keV, and the dose amount is set to 6 P (peta) ions / cm ² . When the ion implantation is performed in this manner, as shown in FIG. 6A, the polycrystalline silicon layer 12 in the portion not covered with the mask 53 has impurity ions 64 over the entire area in the film thickness direction.
Are implanted to become amorphous, and the region becomes an amorphous layer 13. On the other hand, impurity ions are not implanted into the polycrystalline silicon layer 12 in the portion covered by the mask 53.

Then, as shown in (2) of FIG. 6, heat treatment for recrystallization (for example, heating at 550 ° C. for 2 hours and
The amorphous layer (1
3) is modified into a single crystal silicon layer 17. Thus, the amorphous layer (13) is transformed into the semiconductor substrate 3 by the heat treatment.
Since epitaxial growth occurs between 1 and 1, it becomes a monocrystalline silicon layer 17. Therefore, the contact resistance with the semiconductor substrate 31 is reduced. Further, during the heat treatment, the impurity ions 6 implanted in the polycrystalline silicon layer 12
4 diffuses into a part of the surface layer of the diffusion layer 36 serving as the p ⁺ -type base, the n ⁺ -type emitter layer 37 (impurity diffusion layer 16
Corresponding to) is formed.

The control of the depth t of the amorphous layer 13 described in each of the first to fourth embodiments of the invention is performed by adjusting the implantation depth of the impurity ions in the ion implantation by the LSS theory (Lindhard, Schar.
ff, Schiott) and the theory regarding calculation of range parameters of particles driven into a solid). That is, the projection range Rp of the ions and the projection range dispersion ΔRp are used to perform the ion implantation energy derived from the following equation.

[0062]

[Equation 1]

[0063]

[Equation 2]

The depth t of the amorphous layer at the time of the ion implantation is controlled by the formulas (1) and (2) using the projected range Rp of ions and the projected range dispersion ΔRp based on the LSS theory. Since the ion implantation energy is set by, the implantation depth of the impurity ions is set almost accurately. Therefore, the film thickness of the polycrystalline silicon layer which is not amorphized is also set. By setting the ion implantation energy in this way, the thickness of the polycrystalline silicon film remaining after the ion implantation is arbitrarily controlled. Thereby, the crystal grain size of the recrystallized polycrystalline silicon layer is controlled, and finally the resistance value of the polycrystalline silicon layer is controlled.

Next, an application example in which the polycrystalline silicon layer 12 is used as a wiring will be described. Usually, the polycrystalline silicon layer 12 is rarely formed in a flat region. For example, as shown in FIG. 7, it is often formed on the surface of the base 11 having the step portion 41. In such a case, the ion implantation is performed by the so-called oblique ion implantation method. That is, the incident angle θ of the impurity ions 61 (62 to 64) is set to a predetermined angle, and ion implantation is performed while rotating the substrate 11 in the direction of arrow A, for example. Angle of incidence θ
Is set to a certain angle within the range of, for example, 30 ° to 60 °.

An example of amorphization by the above-mentioned oblique ion implantation method will be described below. Silicon ions are obliquely ion-implanted at an incident angle of 60 ° into a polycrystalline silicon layer 12 formed by a low pressure CVD method on the surface of a step portion 41 having a height of 200 nm and then formed by a lithography technique and etching. . In this case, the relative film thickness is 120 nm to 200 nm. Therefore, by setting the implantation energy of silicon ions to 45 keV and performing ion implantation, all layers of the polycrystalline silicon layer 12 can be amorphized to form the amorphous layer 14. In this way, the film which has been made into an amorphous layer is subjected to a recrystallization heat treatment (for example, 60
By heating at 0 ° C. for 80 hours, a film having a low resistance (for example, 200Ω / □) is obtained.

As described above, the impurity ions 61 (62 ...
Since the oblique ion implantation method in which the incident angle θ of 64) is set to a predetermined angle is used, even if the polycrystalline silicon layer 12 is formed in the step portion 41, the impurity ions 61 ( 62-64) is injected.

[0068]

As described above, according to the first aspect of the present invention, the ion implantation energy during the selective ion implantation is controlled, and the implantation depth of the impurity ions is determined to form the amorphous layer. Determine the thickness. Therefore, a polycrystalline silicon layer having a desired thickness can be left below the amorphous layer. In addition, the amorphous layer is recrystallized to have a crystal grain size corresponding to the remaining polycrystalline silicon layer, and the resistance value of the polycrystalline silicon layer corresponds to the crystal grain size. It is possible to control the resistance value of the polycrystalline silicon layer after recrystallization. Therefore, it is possible to form a polycrystalline silicon layer that selectively has portions having different resistance values.

According to the second aspect of the present invention, the impurity ions are shallowly implanted into the polycrystalline silicon layer covered with the covering layer, and the impurity ions are deeply implanted into the polycrystalline silicon layer not covered with the covering layer. To be done. Therefore, the thickness of the amorphous layer can be changed depending on the presence or absence of the coating layer, so that the polycrystalline silicon layer having a desired thickness can be left below the amorphous layer. The amorphous layer is recrystallized to have a crystal grain size corresponding to the remaining polycrystalline silicon layer, and the resistance value of the polycrystalline silicon layer corresponds to the crystal grain size. Therefore, control the film thickness of the coating layer. This makes it possible to control the resistance value of the polycrystalline silicon layer after recrystallization. Therefore, it is possible to form a polycrystalline silicon layer that selectively has portions having different resistance values.

According to the invention of claim 3, the same effect as that of the invention of claim 1 can be obtained. At the same time, the impurity ions injected into the polycrystalline silicon layer can be diffused into the semiconductor substrate, so that a diffusion layer can be formed on the surface layer of the semiconductor substrate.

According to the fourth aspect of the present invention, impurity ions are selectively and entirely implanted in the film thickness direction of the polycrystalline silicon layer to modify the region into an amorphous layer and then recrystallized. Since this is performed, the amorphous layer is crystallized in a state where the crystallinity of the semiconductor substrate is taken over. Therefore, if the semiconductor substrate is a single crystal, it can be modified into a single crystal silicon layer, and the resistance value of this portion can be lowered. Moreover, since the impurity ions in the amorphous layer can be diffused into the surface layer of the semiconductor substrate by the heat treatment, it is possible to form a diffusion layer in the surface layer of the semiconductor substrate.

According to the fifth aspect of the present invention, the depth t of the amorphous layer at the time of the ion implantation is the relational expression between the projected range Rp of the ions and the projected range dispersion ΔRp based on the LSS theory.
It can be set by t = Rp + κ · ΔRp, 2 ≦ κ ≦ 5. Therefore, since the implantation depth of the impurity ions can be set almost accurately by the ion implantation energy, the thickness of the amorphous layer and the thickness of the polycrystalline silicon layer left below this amorphous layer can be determined. It can be set almost accurately. Therefore, it is possible to easily design a polycrystalline silicon layer obtained by recrystallization.

According to the sixth aspect of the present invention, since the ion implantation is performed by the oblique ion implantation method, impurity ions are implanted from the entire surface of the polycrystalline silicon layer even if the polycrystalline silicon layer is formed in the step portion. It becomes possible to do.

According to the invention of claim 7, as the impurity ions, at least one or more ions of silicon and elements heavier than silicon are used. Therefore, the portion of the polycrystalline silicon layer in which the impurity ions are implanted is used. Can be made amorphous.

[Brief description of drawings]

FIG. 1 is a manufacturing process diagram showing an embodiment of the first invention.

FIG. 2 is a manufacturing process diagram showing an embodiment of the second invention.

FIG. 3 is a manufacturing process diagram showing an embodiment of the third invention.

FIG. 4 is an explanatory view of a method of forming an emitter according to the third invention.

FIG. 5 is a manufacturing process chart showing an embodiment of the fourth invention.

FIG. 6 is an explanatory diagram of a method of forming an emitter according to a fourth invention.

FIG. 7 is an explanatory diagram of amorphization by the oblique ion implantation method.

[Explanation of symbols]

11 Base 12 Polycrystalline Silicon Layer 13 Amorphous Layer 14 Polycrystalline Silicon Layer 22 Covering Layer 23 First Amorphous Layer 24 Second Amorphous Layer 25 First Polycrystalline Silicon Layer 26 Second Polycrystalline Silicon Layer 31 Semiconductor Substrate 16 Impurity diffusion layer 17 Single crystal silicon layer 61 Impurity ion 62 Impurity ion 63 Impurity ion 64 Impurity ion θ Incident angle

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Yasuyoshi Inoda 6-735 Kitashinagawa, Shinagawa-ku, Tokyo Sony Corporation

Claims (7)

[Claims] 1. When a polycrystalline silicon layer is formed on a substrate and then impurity ions are selectively implanted into the polycrystalline silicon layer by an ion implantation method, ion implantation energy is controlled to control the impurity ion A first step of forming an amorphous layer corresponding to the ion implantation depth in at least an upper layer of the polycrystalline silicon layer by setting the implantation depth, and a heat treatment is performed to form a lower layer below the amorphous layer. The amorphous layer is crystallized according to the thickness of the remaining polycrystalline silicon layer,
And a second step of forming a polycrystalline silicon layer having a crystal grain size different from that of the polycrystalline silicon layer. 2. A first step of forming a polycrystalline silicon layer on a substrate and then forming a coating layer for selectively covering the polycrystalline silicon layer, and a polycrystalline silicon layer through the coating layer by an ion implantation method. By implanting impurity ions into the polycrystalline silicon layer in a portion not covered with the coating layer, and by implanting impurity ions into the polycrystalline silicon layer in a portion not covered with the coating layer, A second step of forming a crystalline layer and forming a second amorphous layer thicker than the first amorphous layer on the polycrystalline silicon layer not covered by the coating layer, and performing a heat treatment. The first amorphous layer and the second amorphous layer are crystallized to form a first polycrystalline silicon layer on the first amorphous layer side, and on the second amorphous layer side. A second polycrystalline silicon layer having a crystal grain size larger than that of the first polycrystalline silicon layer. The method of manufacturing a semiconductor device characterized by comprising a third step of forming a con layer. 3. When a polycrystalline silicon layer is formed on a semiconductor substrate and then impurity ions are selectively implanted into the polycrystalline silicon layer by an ion implantation method, the ion implantation energy is controlled to control the impurity ions. A first step of forming an amorphous layer corresponding to the ion implantation depth in at least an upper layer of the polycrystalline silicon layer by setting the implantation depth of The amorphous layer is crystallized according to the thickness of the polycrystalline silicon layer left in
A polycrystalline silicon layer having a crystal grain size different from that of the polycrystalline silicon layer is formed, and the impurity ions implanted in the polycrystalline silicon layer are diffused into the surface layer of the semiconductor substrate to form an impurity diffusion layer. A method of manufacturing a semiconductor device, comprising: a second step. 4. A polycrystalline silicon layer is formed on a semiconductor substrate, and then impurity ions are selectively implanted into the polycrystalline silicon layer by an ion implantation method and in the entire thickness direction of the polycrystalline silicon layer. Then, a first step of modifying the region into which the impurity ions are implanted into an amorphous layer, and a heat treatment are carried out to modify the amorphous layer into a monocrystalline silicon layer and the amorphous layer. And a second step of forming impurity diffusion layers by diffusing the impurity ions therein to the surface layer of the semiconductor substrate. 5. The method of manufacturing a semiconductor device according to claim 1, wherein the control of the depth t of the amorphous layer formed by the ion implantation is based on LSS theory. Using the projected range Rp of ions and the projected range variance ΔRp, t = Rp + κ · ΔRp,
A method of manufacturing a semiconductor device, which is performed by ion implantation energy set by the formula 2 ≦ κ ≦ 5. 6. The method of manufacturing a semiconductor device according to claim 1, wherein the ion implantation is performed by an oblique ion implantation method in which an incident angle of impurity ions is set to a predetermined angle. A method of manufacturing a semiconductor device, comprising: 7. The method of manufacturing a semiconductor device according to claim 1, wherein at least one ion selected from silicon and elements heavier than silicon is used as the impurity ions. A method of manufacturing a semiconductor device, comprising: