JPH08233903A - Logic integrated circuit - Google Patents

Abstract

PURPOSE: To divert from a printed circuit board and a diagnosing software of a register definition if the number and the positions of placing logic integrated circuits in which logic packages of a plurality of types having scan paths are placed on the board are altered and to reduce uninspected circuits as much as possible at the time of solely testing even in the logic packages of any type. CONSTITUTION: The logic integrated circuit comprises a plurality of scan path input circuits 111 to 114, open checking circuits 115 to 117 for deciding whether logic binary signals are input to the scan path input circuits 111 to 114 or input open states, a switching unit for selecting which of a plurality of the scan path inputs is transferred to a logic unit, shift registers 121 to 123 disposed so that the number of total flip-flops on the paths becomes the same even if any scan path input is selected, and a forcible switching instructing circuit 53 for forcibly switching the switching unit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic integrated circuit having a scan path, and in particular, a plurality of types of logic packages are formed by using the same type of printed wiring board or the like and changing the number and the mounting position of the logic integrated circuits. Logic integrated circuit.

[0002]

2. Description of the Related Art A conventional logic integrated circuit having a scan path is disclosed in Japanese Patent Laid-Open No. 4-18115.

In the semiconductor integrated circuit described in this publication, under the scan mode, "the Q outputs of the scan registers 7a-7f are propagated to the next stage according to the scan clock to form a scan path." Mode, the D inputs of the scan registers 7a-7f are propagated to the next stage in response to the scan clock, and as a result, are excluded from the serial transmission line. This selection is made by the 3to1 selectors 9a-9e.
Done in.

[0004]

The above-mentioned technique has a plurality of systems only inside the logic IC for the purpose of selecting whether or not some of the flip-flops are included in the scan path in order to shorten the test time. Therefore, it does not have a plurality of scan path input circuits.

Since the logic integrated circuit having the scan path described above has only one scan path input circuit, the scan path is divided unless the preceding logic integrated circuit on the scan path is mounted. That is, it is impossible to configure different types of logic packages by changing the number of mounted logic integrated circuits or the mounting positions of the same type of printed wiring boards. Therefore, it is necessary to design and manufacture a printed wiring board and diagnostic software for each type of logic package.

An object of the present invention is to provide diagnostic software for defining printed wiring boards and registers even when the number of logical integrated circuits mounted on the printed wiring boards of the same type and the mounting positions differ depending on the type of logic package. It is to provide a logic integrated circuit that can be used.

Another object of the present invention is that even if the number and the mounting position of the logic integrated circuits mounted on the printed wiring boards of the same type differ depending on the type of the logical package, any type of logical package is not tested during the unit test. It is to provide a logic integrated circuit in which the number of circuit elements to be inspected is minimized.

[0008]

A first logic integrated circuit according to the present invention comprises a plurality of scan path input means (hereinafter referred to as a scan path input circuit) for receiving a scan path signal from an arbitrary point of a circuit forming a scan path. ), And open check means (hereinafter referred to as an open check circuit) for determining whether each of these scan path input circuits is in a binary state or is in an open state, and the open check. A selection circuit that selects which of the plurality of scan path input circuits to transmit the scan path signal to the logic unit based on the determination result of the circuit.

The second logic integrated circuit of the present invention is characterized in that the scan path input circuit inputs a scan path signal from an input or an output of an arbitrary chip constituting the scan path circuit.

A third logical integrated circuit according to the present invention is a scan path among circuits constituting a scan path regardless of which scan path input circuit the selection circuit of the first logical integrated circuit selects a scan path signal from. A signal holding circuit (shift register of the embodiment) connected to the selection circuit is provided so that the number of circuit elements holding signals is the same.

A fourth logic integrated circuit of the present invention is the third logic integrated circuit.
The number of stages of the signal holding circuit in the logic integrated circuit is the first scan path signal and the second scan path signal applied to the selection circuit.
Is equal to the number of signal holding circuits forming the scan path between the scan path signal and the scan path signal.

A fifth logic integrated circuit of the present invention is a test of a forced switching signal generating means for generating a forced switching signal and a circuit constituting a scan path based on the forced switching signal generated by the forced switching signal generating means. Selecting means for selecting a scan path signal flowing through the target circuit element.

[0013]

The present invention will be described in detail with reference to the drawings.

FIG. 1 shows a logic package 6 having a logic integrated circuit according to an embodiment of the present invention. The IC1, which is one of the logic integrated circuits (hereinafter referred to as logic ICs), determines whether a plurality of scan path input circuits 111 to 114 and logic binary signals are input to the scan path input circuits 111 to 114 or an open state. Open check circuit 115
To 117, a selector 124 to 126 for selecting which of the plurality of scan path inputs is to be transferred to the logic section, and a total flip-flop on the scan path regardless of which scan path input is selected. Shift register 121 arranged such that the number of groups is the same.
1 to 123, a forced switching instruction unit 13 for forcibly switching the switching unit 12, and a logic unit 14. Also, as with IC1, IC2, 3, and 4
Is a scan data receiving unit 21, 31, and 41, a switching unit 22, 32, and 42, and a forced switching instruction circuit 2
3, 33, and 43, and logic units 24, 34, and 4
4 and.

In the present embodiment, the printed wiring board 5 has a pattern of the scan path from the scan data input terminal 51 to the scan data output terminal 52, and a forced switching signal generating section composed of a dual in-line package switch or the like. The pattern of forced switching signals from 53 to ICs 1, 2, 3 and 4 are wired as shown in FIG.
, Any of ICs 2, 3, and 4 and the forced switching signal generator 53 are mounted to configure the logic package 1.

Next, the detailed configuration of the forced switching signal generator 53 will be described in detail with reference to the drawings.

Referring to FIG. 2, the forced switching signal generator 5
Reference numeral 3 denotes switches S ₁₁ , S ₁₂ , S ₁₃ , S ₂₁ , which are arranged via resistors between the power supply signal line V and the ground line G.
S ₂₂ , S ₂₃ , S ₃₁ , S ₃₂ , S ₃₃ , S ₄₁ , S ₄₂ and S ₄₃
It has.

Next, the operation of the embodiment of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 1, the logic package 6 is I
If the product is equipped with C1, 2, 3, and 4, I
In the input circuits 111, 112, 113 and 114 of C1, the logic unit 24 of IC2, the logic unit 34 of IC3,
The scan data sent from the logic unit 44 of the IC 4 and the scan data input terminal 51 of the printed wiring board 5 is input through the pattern, and the selector 126 and the selector 1 are respectively input.
25, the selector 124, and the shift register 121. At this time, the open check circuit 115 outputs “0” because the input of the input circuit 111 is not in the open state and the logic binary signal is input, and the selector 126 selects the scan data transferred from the input circuit 111. And sends it to the logic unit 14.

In the case of a product type in which ICs 1, 3, and 4 are mounted but IC2 is not mounted, the input of the input circuit 111 is in an open state, so the open check circuit 115 outputs "1". On the other hand, since the input of the input circuit 112 is not in the open state, the open check circuit 116 outputs "0". Input circuit 1 from logic unit 34 of IC3
The scan data transferred to the selector 125 via 12 is selected and sent to the K-stage shift register 123, and its output is selected by the selector 126 and sent to the logic unit 114.

ICs 1 and 4 are mounted and ICs 2 and 3 are mounted.
If the product is not equipped with the
Since the input of 2 is in the open state, the open check circuits 115 and 116 output "1". on the other hand,
Since the input of the input circuit 113 is not in the open state, the open check circuit 117 outputs "0". The scan data transferred from the logic unit 44 of the IC 4 to the selector 124 via the input circuit 113 is selected and sent to the shift register 122, and its output is selected by the selector 125 and sent to the shift register 123, and its output is It is selected by the selector 126 and sent to the logic unit 14.

In the case of the type in which the IC1 is mounted and the ICs 2, 3, and 4 are not mounted, the inputs of the input circuits 111, 112, and 113 are in an open state, so that the open check circuits 115, 116, and 117 output "1". To do. Therefore, the scan data input to the scan data input terminal 51 is transferred to the shift register 121 via the input circuit 114, and its output is selected by the selector 124 and sent to the shift register 122. further,
The output is transferred to the logic unit 14 via the selector 125, the shift register 123 and the selector 126.

Here, the shift registers 123, 122,
And 121 of the flip-flop stages are k stages and j, respectively, like the number of flip-flop stages on the scan paths of the logic units 24, 34 and 44 of the ICs 2, 3 and 4, respectively.
If the number of stages is set to i and the number of stages is set to i, the total number of flip-flops on the scan path can be the same regardless of the mounting state of the IC.

In addition, for example, in the IC1 of the logic package of the type in which the ICs 1, 2, 3 and 4 are mounted, the compulsory switching instruction unit 13 normally operates the compulsory switching signal generation unit 5
By receiving 3 bits of logic "0", "0", and "0" from 3, each selector 126 in the switching unit 12,
Open check circuit 11 for 125 and 124
The output data of 5, 116, and 117 are sent as they are. In the logic package unit test, the forced switching signal generator 53 outputs logic "1", "0", and "0", logic "1", "1", and "0", and logic "1".
By receiving "1" and "1", it becomes possible to switch the selectors 126, 125 and 124 to arbitrary states and carry out the test regardless of the mounting state of the IC. The same compulsory switching instruction unit 2 is also provided in the ICs 2, 3 and 4.
3, 33 and 43.

Next, the operation associated with the forced switching signal generator 53 will be described in detail with reference to the drawings.

Referring to FIG. 2, forced switching signal generator 53
When the switches S _{11 to} S _{43 in the above} are on, a logic "1" is output from each output pin, or a logic "0" is output when the switches are off. For example, in the IC1 of the logic package of the type in which the ICs 1, 2, 3, and 4 are mounted, the switches S ₁₁ , S ₁₂ , and S _{13 in the} forced switching signal generation unit 53 are normally operated.
Off, off, off, input pin 1 of IC1
10, 120, and 130 receive the logic "0", "0", and "0", and the forced switching instructing unit 13 switches the switching unit 12
The output data of the open check circuits 115, 116, and 117 are sent to the respective selectors 126, 125, and 124 therein as they are. At the time of the unit test of the logic package, first, the switches S ₁₁ , S ₁₂ , and S ₁₃ are turned on, off, and off, and the input pin 11 of the IC 1 is turned on.
0, 120 and 130 are made to receive logic "1", "0", and "0", the selector 126 is switched to the k-stage shift register 123 side, and a test is carried out. Shift register 12
3, and a functional test of the selector 126 can be performed. Next, the switches S ₁₁ , S ₁₂ , and S ₁₃ are turned on,
It is turned off and turned off, and the input pins 1, 2 and 3 of the IC1 are made to receive logic "1", "1" and "0", the selector 126 is the k-stage shift register 123 side, and the selector 125 is the j-stage shift register. By switching to the 122 side and performing the test, the input circuit 113 and the selector 12
4, j-stage shift register 122, and selector 125
The functional test of can be performed. Next, the switches S ₁₁ , S ₁₂ , and S ₁₃ are turned on, on, and on to cause the input pins 110, 120, and 130 of the IC1 to receive the logic 1, 1, and 1, and the selector 126 is set to k.
The test is performed by switching the stage shift register 123 side, the selector 125 to the j stage shift register 122 side, and the selector 124 to the i stage shift register 121 side.
The function test of the input circuit 114, the i-stage shift register 121, and the selector 124 can be performed. IC2
A functional test is similarly performed for 3 and 4.

[0027]

According to the present invention, even when the number of mounted logic ICs mounted on the same type of printed wiring board and the mounting position differ depending on the type of the logical package, the division of the scan path and the variation of the number of flip-flops on the scan path are performed. Since it does not occur, it is possible to use diagnostic software such as a printed wiring board and register definition, and it is possible to minimize the number of untested circuits in a unit test in any type of logic package.

[Brief description of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a diagram showing a specific configuration example of a forced switching signal generation unit 53 in FIG.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 logic IC 11 scan data receiving part 111-114 input circuit 115-117 open check circuit 12 switching part 121-123 shift register 124-126 selector 13 forced switching instruction part 14 logic part 12 logic IC 21 scan data receiving part 22 switching part 23 forced switching instruction section 24 logical section 3 logical IC 31 scan data receiving section 32 switching section 33 forced switching instructing section 34 logical section 4 logical IC 41 scan data receiving section 42 switching section 43 forced switching instructing section 44 logical section 5 printed wiring board 51 scan data input terminal 52 scan data output terminal 53 forced switching signal generation section 6 logic package S _{11 to} S ₄₃ switch

Claims (3)

[Claims] 1. A plurality of scanpath input means for receiving a scanpath signal from an arbitrary point of a circuit forming a scan path, and a logic value of one of binary states is given to each of these scanpath input means. Open check means for determining whether the scan path input means is in the open state or the open state, and a scan path signal from any one of the plurality of scan path input means based on the determination result of the open check means. Is transmitted to the logic unit, and a logic integrated circuit is included. 2. The selection so that the number of circuit elements holding the scan path signal among the circuits forming the scan path is the same regardless of which scan path input circuit the selection circuit selects the scan path signal from. 2. The logic integrated circuit according to claim 1, further comprising a signal holding circuit connected to the circuit. 3. A forced switching signal generating means for generating a forced switching signal, and a scan path flowing through a circuit element to be tested by a circuit constituting the scan path based on the forced switching signal generated by the forced switching signal generating means. A logic integrated circuit comprising: a selecting means for selecting a signal.