JPH0824185B2 - Thin film transistor device and manufacturing method thereof - Google Patents
Thin film transistor device and manufacturing method thereofInfo
- Publication number
- JPH0824185B2 JPH0824185B2 JP60045865A JP4586585A JPH0824185B2 JP H0824185 B2 JPH0824185 B2 JP H0824185B2 JP 60045865 A JP60045865 A JP 60045865A JP 4586585 A JP4586585 A JP 4586585A JP H0824185 B2 JPH0824185 B2 JP H0824185B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- thin film
- substrate
- insulating film
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
- H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、非晶質シリコン（ａ−si）や多結晶シリコ
ン（ｐ−si）等の半導体薄膜を用いた薄膜トランジスタ
（TFT）の特にソース及びドレイン電極の構造とその製
造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a thin film transistor (TFT) using a semiconductor thin film such as amorphous silicon (a-si) or polycrystalline silicon (p-si). And a structure of a drain electrode and a manufacturing method thereof.
絶縁基板上に形成された第１導電膜と低抵抗半導体薄
膜の多層膜から成るソース及びドレイン電極と、両電極
に接する半導体薄膜と、半導体薄膜上に設けられたゲー
ト絶縁膜とゲート電極とから成るTFTにおいて、前記多
層膜の少なく共側面を絶縁膜で被つてソース及びドレイ
ン電極と半導体薄膜の接触を低抵抗半導体薄膜のみを介
して行なうTFT構造を提供している。それにより、逆方
向リーク電流の少ない特性が得られ、かつ前記多層膜に
よる段差が緩和されるためゲート耐圧が向上する。製造
においては、前記多層膜またはその段差を利用して裏面
露光や全面エツチ等でセルフアライン的に前記絶縁膜を
選択的に除去し、多層膜の側面をカバーする前記絶縁膜
を残している。From a source and drain electrode formed of a multilayer film of a low resistance semiconductor thin film and a first conductive film formed on an insulating substrate, a semiconductor thin film in contact with both electrodes, and a gate insulating film and a gate electrode provided on the semiconductor thin film. In a TFT having the above structure, a TFT structure is provided in which at least the side surfaces of the multilayer film are covered with an insulating film, and the source and drain electrodes are in contact with the semiconductor thin film only through the low resistance semiconductor thin film. As a result, a characteristic that a reverse leakage current is small is obtained, and the step due to the multilayer film is relaxed, so that the gate breakdown voltage is improved. In the manufacturing process, the insulating film is selectively removed in a self-aligned manner by backside exposure or etching of the entire surface by utilizing the multilayer film or its step, leaving the insulating film covering the side surface of the multilayer film.
TFTは、現在液晶表示装置等に応用されており、その
用途はさらに拡大しつつある。ａ−siを用いたTFTにつ
いて主に述べれば、低温で堆積できる特徴をもつので多
くの構造が可能である。第２図にはその１断面例を示し
た。TFTは、絶縁基板１上のソース・ドレイン電極2,3
と、その上に設けられた半導体薄膜であるａ−si:H膜
４、ゲート絶縁膜５、ゲート電極６とから成る。ソース
・ドレイン電極2,3は通常第１導電膜12,13と低抵抗半導
体薄膜であるn+a−si:H膜22,23から成る多層膜で形成さ
れ、抵抗低減化と工程の簡単化を図つている。TFTを液
晶表示装置に適用する場合には、第１導電膜12,13にITO
等の透明導電膜を用いるこが多い。または、第２図の様
にソース・ドレイン配線32,33を設けることがあり、n+a
−si膜22,23を介したり、第１導電膜12,13と直接接触さ
せる。製造工程の簡単化の現め、第１導電膜12,13とn+a
−si膜22,23から成る多層膜は同一形状に選択エツチさ
れるため、ａ−si膜４はn+a−si膜22,23と接触すると共
に、多層膜の側面で第１導電膜12,13とも接触する。後
者の接触はゲート電圧を負にしたとき流れるソース・ド
レイン電極間電流にいわゆる逆方向リーク電流の増加の
原因になつていて、オフ特性上好ましくない。一方、前
記多層膜の選択エツチは、n+a−si膜22,23のエツチ後第
１導電膜12,13の選択エツチを行なうため、多層膜の側
面は急峻、もしくは逆テーパー状になりやすい。この様
な側面をもつソース・ドレイン電極2,3上にａ−si膜
４、ゲート絶縁膜５、ゲート電極６を形成すると、これ
らの膜の段差被覆性が充分でないため段差部でゲート電
極６とａ−si膜４の短絡、または耐圧不良を生じてしま
う。その結果、TFT装置の製造歩留りが向上しないとい
う問題点があつた。TFTs are currently applied to liquid crystal display devices and the like, and their applications are expanding further. A TFT using a-si will be mainly described. Since it has a feature that it can be deposited at a low temperature, many structures are possible. FIG. 2 shows an example of the cross section. The TFT is a source / drain electrode 2, 3 on the insulating substrate 1.
And an a-si: H film 4, which is a semiconductor thin film, a gate insulating film 5, and a gate electrode 6 provided thereon. The source / drain electrodes 2 and 3 are usually formed by a multi-layer film composed of the first conductive films 12 and 13 and the low resistance semiconductor thin film n + a-si: H films 22 and 23 to reduce the resistance and simplify the process. I am trying. When the TFT is applied to a liquid crystal display device, ITO is formed on the first conductive films 12 and 13.
In many cases, a transparent conductive film such as Or, it may as in FIG. 2 provided the source and drain lines 32, 33, n + a
It is directly contacted with the first conductive films 12 and 13 through the -si films 22 and 23. Aiming to simplify the manufacturing process, the first conductive films 12, 13 and n + a
Since the multilayer film including the -si films 22 and 23 is selectively etched into the same shape, the a-si film 4 contacts the n + a-si films 22 and 23, and the first conductive film 12 is formed on the side surface of the multilayer film. , 13 also contact. The latter contact causes an increase in so-called reverse leak current in the source-drain electrode current that flows when the gate voltage is made negative, which is not preferable in terms of off characteristics. On the other hand, in the selective etching of the multilayer film, since the first conductive films 12 and 13 are selectively etched after the etching of the n + a-si films 22 and 23, the side surfaces of the multilayer film are likely to be steep or inversely tapered. . When the a-si film 4, the gate insulating film 5, and the gate electrode 6 are formed on the source / drain electrodes 2 and 3 having such side surfaces, the step coverage of these films is not sufficient, so that the gate electrode 6 is formed at the step portion. And the a-si film 4 is short-circuited or the withstand voltage is defective. As a result, there is a problem that the manufacturing yield of the TFT device is not improved.
本発明は叙上の問題点に鑑みてなされ、第１の目的は
逆方向リーク電流の少ないTFTを提供することである。
第２の目的はゲート耐圧を改善すること。第３の目的は
前記目的のための容易な製造方法を提供するものであ
る。The present invention has been made in view of the above problems, and a first object thereof is to provide a TFT having a small reverse leakage current.
The second purpose is to improve the gate breakdown voltage. A third object is to provide an easy manufacturing method for said purpose.
本発明によるTFTは、絶縁基板上に設けられた第１導
電膜及び低抵抗半導体薄膜から成る多層膜で形成された
ソース・ドレイン電極を有し、この多層膜の側面とその
間の基板表面を絶縁膜で被覆した構造を有している。そ
の上に半導体薄膜、ゲート絶縁膜、ゲート電極が設けら
れるので、半導体薄膜は多層膜のうち低抵抗半導体薄膜
とのみ接する。A TFT according to the present invention has a source / drain electrode formed of a multilayer film composed of a first conductive film and a low resistance semiconductor thin film provided on an insulating substrate, and insulates a side surface of the multilayer film and a substrate surface therebetween. It has a structure covered with a film. Since the semiconductor thin film, the gate insulating film, and the gate electrode are provided thereon, the semiconductor thin film contacts only the low resistance semiconductor thin film of the multilayer film.
上記の構造のため、低抵抗半導体薄膜（例えばn+a−s
i膜）が例えば正孔阻止機能を有するため逆方向リーク
電流が少なくできる。また、絶縁膜の存在がソース・ド
レイン電極である多層膜の段差を緩和するので、上に堆
積する膜のステツプカバー性を改善できる。Due to the above structure, a low resistance semiconductor thin film (for example, n + a-s
Since the i film) has a hole blocking function, the reverse leakage current can be reduced. Further, since the presence of the insulating film alleviates the step difference of the multilayer film which is the source / drain electrodes, the step coverage of the film deposited on the multilayer film can be improved.
（ａ） 実施例１ TFT断面（第１図） 本発明によるTFT構造断面例を第１図に示した。TFT
は、絶縁基板１上の第１導電膜12,13とn+a−si膜22,23
とから成る多層膜であるソース電極２とドレイン電極３
と、多層膜の側面端部とソース・ドレイン電極2,3間の
基板１の表面とを被う絶縁膜７と、n+a−si膜22,23に両
端を接するａ−si膜４と、ａ−si膜４上のゲート絶縁膜
５及びゲート電極６とから成つている。必要に応じ設け
られるソース・ドレイン配線32,33は、この例ではそれ
ぞれの電極2,3の第１導電膜12,13に接している。絶縁基
板１としては、ガラス，石英，セラミツクス等の絶縁材
料の他にsiや金属等に絶縁物コートしたものが用いられ
る。第１導電膜12,13には、Cr,W,Mo,Ti等の金属、特に
高融点金属やその硅素化物が用いられる他、ITO等の透
明導電膜も用いられるし、これらの多層膜でもよい。絶
縁膜７は、SiOx,SiNx等の他にポリイミド等の有機絶縁
膜も用いられる。n+a−si膜22,23やａ−si膜４は、ａ−
si:H合金、ａ−si:F合金等が用いられるが、ｐ−siやビ
ームアニールされたsi薄膜も適用できる。n+a−si膜22,
23は、p+a−si膜に置きかえることも可能である。(A) Example 1 TFT cross section (FIG. 1) An example of a TFT structure cross section according to the present invention is shown in FIG. TFT
Is the first conductive film 12, 13 and the n + a-si film 22, 23 on the insulating substrate 1.
A source electrode 2 and a drain electrode 3 which are a multilayer film composed of
And an insulating film 7 covering the side edges of the multilayer film and the surface of the substrate 1 between the source / drain electrodes 2 and 3, and an a-si film 4 contacting both ends of the n + a-si films 22 and 23. , A-si film 4 and a gate insulating film 5 and a gate electrode 6. The source / drain wirings 32, 33 provided as necessary are in contact with the first conductive films 12, 13 of the electrodes 2, 3 in this example. As the insulating substrate 1, there is used an insulating material such as glass, quartz, ceramics, etc., or a material such as si or metal coated with an insulating material. For the first conductive films 12 and 13, metals such as Cr, W, Mo, and Ti, especially refractory metals and their silicides are used, and also transparent conductive films such as ITO are used, and multilayer films of these are also used. Good. As the insulating film 7, an organic insulating film such as polyimide is used in addition to SiOx, SiNx and the like. The n + a-si films 22 and 23 and the a-si film 4 are a-
An si: H alloy, an a-si: F alloy, or the like is used, but a p-si or beam-annealed si thin film is also applicable. n + a-si film 22,
23 can also be replaced by a p + a-si membrane.
以下に本発明を液晶表示装置用TFT基板に適用した場
合の製造方法を説明しつつ、本発明をさらに明らかにし
たい。The present invention will be further clarified while explaining a manufacturing method when the present invention is applied to a TFT substrate for a liquid crystal display device.
（ｂ） 実施例２ 単位画素断面（第３図） 第３図（ａ）は、ガラス・石英等の透明絶縁基板１上
に第１導電膜12,13である透明導電膜（例えばITO 0.1
μ）102,103と不透明導電膜（例えば金属膜0.1μ）112,
113の２層膜と、n+a−si膜22,23（例えば500Å）とを堆
積した後これらの多層膜をソース電極２、ドレイン電極
３の形状に選択的に残した断面である。第３図（ｂ）
は、絶縁膜７を全面堆積後、ネガレジスト８をコートし
裏面から光露光し、現像した状態を示す。絶縁膜７はSi
Ox,やSiNx等のCVD膜が用いられるが表面平坦化の上では
塗布絶縁物（例えばスピンオングラスやポリイミド系樹
脂）をソース・ドレイン電極の段差以上の厚みに形成す
ることが望ましい。基板１の裏面からの光源光光により
金属膜112,113がマスクとなり、セルフアライン的にレ
ジスト８を残せる。各電極2,3の多層膜側面を絶縁膜７
で充分カバーするには、裏面光露光をオーバーにする
か、レジスト８が変形する温度でベークするかして、n+
a−si膜22,23の表面までレジスト８を拡げることが望ま
しい。第３図（ｃ）は、レジスト８をマスクにして絶縁
膜７を選択エツチした状態を示す。絶縁膜７の端部17
は、なだらかに加工することが有効で、スパツター、イ
オンエツチ等が有効である。第３図（ｄ）は、ａ−si膜
４、ゲート絶縁膜５、ゲート電極用金属膜（例えばAl）
16を順次堆積した状態を示す。ａ−si膜（例えば500
Å）４、ゲート絶縁膜（例えばSiNx膜0.2μ）５はプラ
ズマCVD等で堆積できるが、ａ−si膜４堆積前にn+a−si
膜22,23表面をH2やAr等で清浄化することが望ましい。
第３図（ｅ）は完成したTFT構造の１例であるが、ゲー
ト電極６を選択エツチで形成後、次のマスク工程によつ
てゲート絶縁膜５、ａ−si膜４を選択エツチし、さらに
露出したn+a−si膜23、金属膜113を除去したものであ
る。この最終工程により、ドレイン電極３の一部である
ITO膜103が透明画素となる。金属膜112,113はn+a−si膜
22,23が充分厚ければ必ずしも必要ないが、第３図
（ｆ）における裏面露光のマスク効果の向上や、配線抵
抗の減少に有効である。(B) Example 2 Cross-section of unit pixel (Fig. 3) Fig. 3 (a) shows a transparent conductive film (for example, ITO 0.12) which is the first conductive film 12 and 13 on the transparent insulating substrate 1 such as glass and quartz.
μ) 102, 103 and an opaque conductive film (for example, a metal film 0.1 μ) 112,
This is a cross section in which the two-layer film of 113 and the n + a-si films 22 and 23 (for example, 500 Å) are deposited, and then these multilayer films are selectively left in the shapes of the source electrode 2 and the drain electrode 3. Fig. 3 (b)
Shows a state in which after the insulating film 7 is deposited on the entire surface, the negative resist 8 is coated, and the back surface is exposed to light and developed. Insulating film 7 is Si
Although a CVD film such as Ox or SiNx is used, it is desirable to form a coating insulator (for example, spin-on-glass or polyimide resin) with a thickness equal to or larger than the step difference between the source / drain electrodes in order to flatten the surface. The metal films 112 and 113 serve as masks by the light source light from the back surface of the substrate 1, and the resist 8 can be left in a self-aligned manner. Insulating film 7 on the side of the multilayer film of each electrode 2, 3
In order to adequately cover, either over-the back surface light exposure, and whether the resist 8 is baked at a temperature of deformation, n +
It is desirable to extend the resist 8 to the surfaces of the a-si films 22 and 23. FIG. 3C shows a state where the insulating film 7 is selectively etched using the resist 8 as a mask. Edge 17 of insulating film 7
It is effective to process gently, and sputter, ion etching, etc. are effective. FIG. 3D shows an a-si film 4, a gate insulating film 5, a metal film for a gate electrode (eg, Al).
16 shows a state in which 16 are sequentially deposited. a-si membrane (eg 500
Å) 4, the gate insulating film (for example, SiNx film 0.2μ) 5 can be deposited by plasma CVD or the like, but n + a-si before deposition of the a-si film 4
It is desirable to clean the surfaces of the films 22 and 23 with H 2 or Ar.
FIG. 3 (e) is an example of the completed TFT structure. After the gate electrode 6 is formed by selective etching, the gate insulating film 5 and the a-si film 4 are selectively etched by the next mask process. Further, the exposed n + a-si film 23 and the metal film 113 are removed. By this final step, it is a part of the drain electrode 3.
The ITO film 103 becomes a transparent pixel. The metal films 112 and 113 are n + a-si films
Although not necessary if 22, 23 are sufficiently thick, they are effective for improving the mask effect of the backside exposure in FIG. 3 (f) and reducing the wiring resistance.
（ｃ） 実施例３ ソース・ドレイン電極の形成（第４
図） 第４図には本発明によるソース・ドレイン電極の他の
形成方法を示した。第４図（ａ）は、絶縁基板１（透明
である必要はない）上に、第１導電膜12,13とn+a−si膜
22,23の多層膜から成るソース・ドレイン電極2,3を形成
した状態を示す。第４図（ｆ）は、凹部により厚く堆積
できる絶縁膜７をつけた状態である。この場合、前述の
塗布絶縁膜の他にRFバイアススパツター法による絶縁膜
も有効である。次に、全面についた絶縁膜７の除去の途
中でエツチを止めることにより、第４図（ｃ）の様に絶
縁膜７をソース・ドレイン電極2,3の間に埋めた形状に
残すことができる。この後、ａ−si膜４形成、ゲート絶
縁膜５形成、ゲート電極６形成を行なえばTFTは完成す
る。(C) Example 3 Formation of Source / Drain Electrodes (Fourth Example)
FIG. 4 shows another method of forming source / drain electrodes according to the present invention. FIG. 4 (a) shows the first conductive films 12 and 13 and the n + a-si film on the insulating substrate 1 (which need not be transparent).
Shown is a state in which the source / drain electrodes 2 and 3 composed of 22,23 multilayer films are formed. FIG. 4 (f) shows a state in which the insulating film 7 that can be deposited thicker is attached to the recess. In this case, an insulating film formed by the RF bias sputtering method is also effective in addition to the above-mentioned coated insulating film. Next, by stopping the etching during the removal of the insulating film 7 on the entire surface, the insulating film 7 can be left in a shape buried between the source / drain electrodes 2 and 3 as shown in FIG. 4 (c). it can. After that, the a-si film 4, the gate insulating film 5, and the gate electrode 6 are formed to complete the TFT.
この例の応用としては、第４図（ｆ）の状態にさらに
レジスト等をコートして表面を平坦化して、レジスト及
び絶縁膜７に対しほぼ同じエツチ速度でトライエツチ等
で全面エツチすることも行なえる。As an application of this example, the surface of FIG. 4 (f) may be further coated with a resist or the like to planarize the surface, and the resist and the insulating film 7 may be entirely etched with a trietch or the like at substantially the same etching speed. It
（ｄ） 実施例４ ソース・ドレイン電極の形成（第５
図） 第５図には、絶縁膜７に感光性絶縁膜を用いた例を示
した。第５図（ａ）には、透明絶縁基板１に、ITO102,1
03、金属膜112,113、n+a−si膜22,23から成るソース・
ドレイン電極2,3を形成後、感光性絶縁膜（例えばネガ
型ポリイミド系樹脂）７を全面コートした状態を示す。
この状態で基板裏面から光露光し、現像することによつ
て第５図（ｆ）の様にソース・ドレイン電極2,3の側面
を被つた絶縁膜７を形成することができる。この場合
も、オーバー露光が望ましい。また、絶縁膜７の端部17
をさらになだらかにするため、酸素プラズマ等によるエ
ツチ，イオンエツチ，スパツタエツチ等が有効である。(D) Example 4 Formation of Source / Drain Electrodes (Fifth Example)
FIG. 5 shows an example in which a photosensitive insulating film is used as the insulating film 7. As shown in FIG. 5 (a), ITO 102, 1 is formed on the transparent insulating substrate 1.
03, metal film 112, 113, n + a-si film 22, 23
After the drain electrodes 2 and 3 are formed, a state in which a photosensitive insulating film (for example, a negative polyimide resin) 7 is entirely coated is shown.
In this state, the back surface of the substrate is exposed to light and developed to form the insulating film 7 covering the side surfaces of the source / drain electrodes 2 and 3 as shown in FIG. 5 (f). Also in this case, overexposure is desirable. In addition, the end portion 17 of the insulating film 7
In order to make the temperature even more gentle, it is effective to use an etch with oxygen plasma or the like, an ion etch, a spatula etch, or the like.
以上の如く、本発明は簡単な工程で逆方向リーク電流
の減少、平坦化によるゲート耐圧向上が図れる。本発明
は主にソース・ドレイン電極構造とその製法にあるの
で、ソース・ドレイン電極形成後ａ−si、ゲート絶縁
膜、ゲート電極を形成する構造・製法のTFTにすべて適
用できる。本発明においては、絶縁膜７の選択形成がセ
ルフアライン的にできるので、大面積TFT装置、微細TFT
装置等に適用でき、特性向上と歩留り向上が行なえる。As described above, according to the present invention, the reverse breakdown current can be reduced and the gate breakdown voltage can be improved by flattening with a simple process. Since the present invention is mainly in the source / drain electrode structure and the manufacturing method thereof, it can be applied to all the TFTs of the structure / manufacturing method of forming a-si, the gate insulating film, and the gate electrode after forming the source / drain electrodes. In the present invention, since the selective formation of the insulating film 7 can be performed in a self-aligned manner, a large area TFT device and a fine TFT can be obtained.
It can be applied to devices, etc., and can improve characteristics and yield.
主にａ−siを半導体薄膜に用いる例を述べてきたが、
ｐ−si、ビームアニールされた半導体薄膜、さらにsiに
限らず他の半導体薄膜に適用できる。We have mainly described examples of using a-si for semiconductor thin films.
The present invention can be applied not only to p-si and beam-annealed semiconductor thin films, but also to other semiconductor thin films other than si.
本発明によるTFTはさらに、ソース・ドレイン電極が
平坦化しやすいので、半導体薄膜が数10Å〜数100Åと
極めて薄い場合に有効で、工程の簡単化と共に高い製造
歩留りを得ることができる。Further, since the source / drain electrodes are easily flattened, the TFT according to the present invention is effective when the semiconductor thin film is extremely thin, such as several tens of liters to several hundred liters, and can simplify the process and obtain a high manufacturing yield.
第１図は本発明によるTFTの断面図、第２図は従来のTFT
の断面図、第３図（ａ）〜（ｅ）は本発明の実施例を単
位画素形成について説明するための工程順断面図、第４
図（ａ）〜（ｃ）及び第５図（ａ）及び（ｂ）はそれぞ
れソース・ドレイン電極の形成方法の実施例の工程順の
断面図である。 １……基板、２……ソース電極、３……ドレイン電極、
４……ａ−si膜、５……ゲート絶縁膜、６……ゲート電
極、７……絶縁膜、12,13……第１導電膜、22,23……n+
a−si膜、102,103……ITO、112,113……金属膜FIG. 1 is a sectional view of a TFT according to the present invention, and FIG. 2 is a conventional TFT.
3A to 3E are cross-sectional views in order of the steps for explaining the unit pixel formation according to the embodiment of the present invention.
5A to 5C and FIGS. 5A and 5B are cross-sectional views in order of the steps of the embodiment of the method for forming the source / drain electrodes. 1 ... Substrate, 2 ... Source electrode, 3 ... Drain electrode,
4 ... a-si film, 5 ... gate insulating film, 6 ... gate electrode, 7 ... insulating film, 12,13 ... first conductive film, 22,23 ... n +
a-si film, 102,103 ... ITO, 112,113 ... metal film
Claims (6)
成されたソース電極及びドレイン電極と、前記ソース及
びドレイン電極に両端を接する半導体薄膜と、該薄膜上
に設けられたゲート絶縁膜と、該絶縁膜上に設けられた
ゲート電極とから少なくとも成る薄膜トランジスタにお
いて 前記ソース及びドレイン電極が前記基板側から第１導電
膜、低抵抗半導体薄膜からなる多層膜であり、 前記ソース及びドレイン電極の間の前記基板表面と前記
ソース及びドレイン電極である多層膜の少なくとも両側
面と前記低抵抗半導体薄膜の上側１部を被覆する絶縁膜
を設け、 前記半導体薄膜と前記ソース及びドレイン電極とは直接
接触しておらず、全て前記低抵抗半導体薄膜を介してな
されることを特徴とする薄膜トランジスタ装置。1. An insulating substrate, a source electrode and a drain electrode formed on the substrate so as to be separated from each other, a semiconductor thin film having both ends in contact with the source and drain electrodes, and a gate insulating film provided on the thin film. And a thin film transistor comprising at least a gate electrode provided on the insulating film, wherein the source and drain electrodes are a multilayer film including a first conductive film and a low resistance semiconductor thin film from the substrate side. An insulating film is provided to cover the substrate surface between and at least both side surfaces of the multi-layer film that is the source and drain electrodes and an upper part of the low resistance semiconductor thin film, and the semiconductor thin film and the source and drain electrodes are in direct contact with each other. The thin-film transistor device is characterized in that it is not formed, and all are formed through the low resistance semiconductor thin film.
板表面から第１層目が、透明導電膜であることを特徴と
する特許請求の範囲第１項記載の薄膜トランジスタ装
置。2. The thin film transistor device according to claim 1, wherein the first conductive film is composed of two layers, and the first layer from the surface of the substrate is a transparent conductive film.
体薄膜を順次堆積し、多層膜とする第１工程と、 前記多層膜をソース及びドレイン電極形状に島状領
域に選択形成する第２工程と、 全面に絶縁膜を堆積する第３工程と、 前記多層膜または多層膜の段差を利用して、前記多
層膜上の前記絶縁膜の１部を残して除去し、前記基板上
及び前記多層膜の側面及び前記低抵抗半導体薄膜の上側
の１部を被う如く前記絶縁膜を残す第４工程と、 半導体薄膜、ゲート絶縁膜、ゲート電極を順次形成
する第５工程 より少なくとも成る薄膜トランジスタ装置の製造方法。3. A first step of sequentially depositing a first conductive film and a low-resistance semiconductor thin film on an insulating substrate to form a multilayer film, and a step of selectively forming the multilayer film in a source and drain electrode shape in an island region. 2 steps, a third step of depositing an insulating film on the entire surface, and a part of the insulating film on the multilayer film is removed by using the multilayer film or the step of the multilayer film to remove the insulating film on the substrate. A thin film transistor comprising at least a fourth step of leaving the insulating film so as to cover the side surface of the multilayer film and a part of the upper side of the low resistance semiconductor thin film, and a fifth step of sequentially forming a semiconductor thin film, a gate insulating film and a gate electrode. Device manufacturing method.
記多層膜をマスクとして用いた基板裏面よりの光露光を
利用することを特徴とする特許請求の範囲第３項記載の
薄膜トランジスタ装置の製造方法。4. The thin film transistor device according to claim 3, wherein the substrate is transparent, and the fourth step utilizes light exposure from the back surface of the substrate using the multilayer film as a mask. Manufacturing method.
により堆積されることを特徴とする特許請求の範囲第３
項または第５項記載の薄膜トランジスタ装置の製造方
法。5. The method according to claim 3, wherein the insulating film is deposited by coating in the third step.
Item 5. A method of manufacturing a thin film transistor device according to Item 5.
て生じる前記基板上と前記多層膜上の前記絶縁膜の厚さ
の差を利用し、前記絶縁膜の全面にエッチによることを
特徴とする特許請求の範囲第５項記載の薄膜トランジス
タ装置の製造方法。6. The fourth step is characterized in that the entire surface of the insulating film is etched by utilizing a difference in thickness of the insulating film on the substrate and on the multilayer film caused by a step of the multilayer film. A method of manufacturing a thin film transistor device according to claim 5.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60045865A JPH0824185B2 (en) | 1985-03-08 | 1985-03-08 | Thin film transistor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60045865A JPH0824185B2 (en) | 1985-03-08 | 1985-03-08 | Thin film transistor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61204976A JPS61204976A (en) | 1986-09-11 |
| JPH0824185B2 true JPH0824185B2 (en) | 1996-03-06 |
Family
ID=12731103
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60045865A Expired - Lifetime JPH0824185B2 (en) | 1985-03-08 | 1985-03-08 | Thin film transistor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0824185B2 (en) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62216372A (en) * | 1986-03-18 | 1987-09-22 | Fujitsu Ltd | A-si thin film transistor |
| EP0473988A1 (en) * | 1990-08-29 | 1992-03-11 | International Business Machines Corporation | Method of fabricating a thin film transistor having amorphous/polycrystalline semiconductor channel region |
| JP2722890B2 (en) * | 1991-10-01 | 1998-03-09 | 日本電気株式会社 | Thin film transistor and method of manufacturing the same |
| US5614731A (en) * | 1993-03-15 | 1997-03-25 | Kabushiki Kaisha Toshiba | Thin-film transistor element having a structure promoting reduction of light-induced leakage current |
| KR102220018B1 (en) * | 2010-03-08 | 2021-02-26 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Semiconductor device and method for manufacturing semiconductor device |
| CN110718557B (en) * | 2010-03-08 | 2023-12-26 | 株式会社半导体能源研究所 | Semiconductor device and method for manufacturing semiconductor device |
| CN102822978B (en) * | 2010-03-12 | 2015-07-22 | 株式会社半导体能源研究所 | Semiconductor device and method for manufacturing the same |
| US8207025B2 (en) * | 2010-04-09 | 2012-06-26 | Semiconductor Energy Laboratory Co., Ltd. | Manufacturing method of semiconductor device |
| JP5739257B2 (en) * | 2010-08-05 | 2015-06-24 | 株式会社半導体エネルギー研究所 | Method for manufacturing semiconductor device |
| KR101963226B1 (en) * | 2012-02-29 | 2019-04-01 | 삼성전자주식회사 | Transistor, method of manufacturing the same and electronic device including transistor |
| JP6798173B2 (en) * | 2016-07-19 | 2020-12-09 | 株式会社リコー | Field-effect transistor and its manufacturing method, display element, display device, system |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54141581A (en) * | 1978-04-26 | 1979-11-02 | Matsushita Electric Ind Co Ltd | Thin film transistor |
| JPS5936944A (en) * | 1982-08-25 | 1984-02-29 | Fujitsu Ltd | Formation of multilayer wiring |
| JPS59225569A (en) * | 1983-06-06 | 1984-12-18 | Fujitsu Ltd | Manufacture of self-aligning thin film transistor |
-
1985
- 1985-03-08 JP JP60045865A patent/JPH0824185B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61204976A (en) | 1986-09-11 |
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